SN65LBC180ADRG4 [TI]
Low-Power Differential Line Driver And Receiver Pair 14-SOIC -40 to 85;
| 型号： | SN65LBC180ADRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low-Power Differential Line Driver And Receiver Pair 14-SOIC -40 to 85 驱动 信息通信管理 光电二极管 接口集成电路 驱动器 |
| 文件： | 总20页 (文件大小：468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LBC180A
SN75LBC180A
www.ti.com............................................................................................................................................................... SLLS378D–MAY 2000–REVISED APRIL 2009
LOW-POWER DIFFERENTIAL LINE DRIVER AND RECEIVER PAIRS
1
FEATURES
SN65LBC180AD (Marked as BL180A)
2
•
High-Speed Low-Power LinBICMOS™ Circuitry
Designed for Signaling Rates(1) of up to
30 Mbps
SN65LBC180AN (Marked as 65LBC180A)
SN75LBC180AD (Marked as LB180A)
SN75LBC180AN (Marked as 75LBC180A)
(TOP VIEW)
•
•
Bus-Pin ESD Protection 15 kV HBM
NC
R
VCC
VCC
A
1
2
3
4
5
6
7
14
13
12
11
10
9
Low Disabled Supply-Current Requirements:
700 µA Maximum
RE
•
Designed for High-Speed Multipoint Data
Transmission Over Long Cables
DE
B
D
Z
•
•
•
Common-Mode Voltage Range of –7 V to 12 V
Low Supply Current: 15 mA Max
GND
GND
Y
8
NC
Compatible With ANSI Standard TIA/EIA-485-A
and ISO 8482:1987(E)
NC−No internal connection
Pins 6 and 7 are connected together internally
Pins 13 and 14 are connected together internally
•
Positive and Negative Output Current Limiting
Driver Thermal Shutdown Protection
•
(1)
Signaling rate by TIA/EIA-485-A definition restrict transition
times to 30% of the bit duration, and much higher signaling
rates may be achieved without this requirement as displayed
in the TYPICAL CHARACTERISTICS of this device.
DESCRIPTION
The SN65LBC180A and SN75LBC180A differential driver and receiver pairs are monolithic integrated circuits
designed for bidirectional data communication over long cables that take on the characteristics of transmission
lines. They are balanced, or differential, voltage mode devices that are compatible with ANSI standard
TIA/EIA-485-A and ISO 8482:1987(E). The A version offers improved switching performance over its
predecessors without sacrificing significantly more power.
These devices combine a differential line driver and differential input line receiver and operate from a single 5-V
power supply. The driver differential outputs and the receiver differential inputs are connected to separate
terminals for full-duplex operation and are designed to present minimum loading to the bus when powered off
(VCC = 0). These parts feature wide positive and negative common-mode voltage ranges, making them suitable
for point-to-point or multipoint data bus applications. The devices also provide positive and negative current
limiting for protection from line fault conditions. The SN65LBC180A is characterized for operation from –40°C to
85°C, and the SN75LBC180A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE(1)
DRIVER
RECEIVER
DIFFERENTIAL INPUTS
ENABLE
RE
OUTPUT
R
OUTPUTS
INPUT
D
ENABLE
DE
A – B
Y
H
L
Z
L
VID ≥ 0.2 V
L
L
L
H
L
H
?
H
L
H
H
L
-0.2 V < VID < 0.2 V
H
Z
L
VID ≤ -0.2 V
L
X
Z
H
X
Z
H
OPEN
H
Open circuit
(1) H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
LinBICMOS is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2009, Texas Instruments Incorporated
SN65LBC180A
SN75LBC180A
SLLS378D–MAY 2000–REVISED APRIL 2009............................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
LOGIC SYMBOL(1)
LOGIC DIAGRAM (POSITIVE LOGIC)
4
4
5
9
DE
DE
D
EN1
Y
Z
1
1
9
10
Y
Z
5
3
D
10
3
2
12
11
RE
R
EN2
2
A
B
RE
12
11
2
A
B
R
(1) This symbol is in accordance with
ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
AVAILABLE OPTIONS(1)
PACKAGE
PLASTIC
DUAL-IN-LINE
(N)
SMALL OUTLINE(2)
(D)
TA
0°C to 70°C
–40°C to 85°C
SN75LBC180AD
SN65LBC180AD
SN75LBC180AN
SN65LBC180AN
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com.
(2) The D package is available taped and reeled. Add an R suffix to the part number (i.e.,
SN65LBC180ADR).
2
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SCHEMATICS OF INPUTS AND OUTPUTS
D, DE, and RE Inputs
V
CC
100 kΩ
1 kΩ
Input
8 V
A Input
B Input
V
CC
V
CC
16 V
100 kΩ
4 kΩ
4 kΩ
16 V
18 kΩ
18 kΩ
Input
Input
100 kΩ
4 kΩ
16 V
16 V
4 kΩ
Y AND Z Outputs
V
CC
R Output
V
CC
16 V
40 Ω
Output
Output
8 V
16 V
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VCC
VI
Supply voltage range(2)
Input voltage range
Voltage range
–0.3 V to 6 V
–10 V to 15 V
–0.3 V to VCC + 0.5 V
±10 mA
A, B
D, R, DE, RE
IO
Receiver output current
Continuous total power dissipation(3)
Internally limited
See Dissipation Rating Table
±15 kV
Total power dissipation
Bus terminals and GND
All pins
HBM (Human Body Model) EIA/JESD22-A114(4)
HBM (Human Body Model) EIA/JESD22-A114(4)
±3 kV
ESD
MM (Machine Model) EIA/JESD22-A115
±400 V
CDM (Charge Device Model) EIA/JESD22-C101
±1.5 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND except for differential input or output voltages.
(3) The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature.
(4) Tested in accordance with MIL-STD-883C, Method 3015.7.
DISSIPATION RATINGS
T
A ≤ 25°C
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
D
N
950 mW
7.6 mW/°C
9.2 mW/°C
608 mW
736 mW
494 mW
598 mW
1150 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
5.25
VCC
0.8
UNIT
VCC
VIH
VIL
VID
VO
VI
Supply voltage
4.75
5
V
V
V
V
High-level input voltage
Low-level input voltage
Differential input voltage(1)
D, DE, and RE
D, DE, and RE
2
0
–12(2)
12
Voltage at any bus terminal (separately or common mode)
A, B, Y, or Z
–7
12
V
VIC
Y or Z
–60
–8
IOH
IOL
TA
High-level output current
Low-level output current
Operating free-air temperature
mA
mA
°C
R
Y or Z
60
8
R
SN65LBC180A
SN75LBC180A
–40
0
85
70
(1) Differential input/output bus voltage is measured at the noninverting terminal with respect to the inverting terminal.
(2) The algebraic convention, where the least positive (more negative) limit is designated minimum, is used in this data sheet.
4
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www.ti.com............................................................................................................................................................... SLLS378D–MAY 2000–REVISED APRIL 2009
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VIK
Input clamp voltage
II = –18 mA
–1.5
1
–0.8
1.5
1.5
1.5
1.5
V
SN65LBC180A
SN75LBC180A
SN65LBC180A
SN75LBC180A
3
V
3
RL = 54 Ω,
See Figure 1
1.1
1
|VOD
|
Differential output voltage magnitude
3
V
3
RL = 60 Ω,
See Figure 2
1.1
Change in magnitude of differential output
voltage(2)
Δ| VOD
VOC(ss)
ΔVOC
|
See Figure 1 and Figure 2
See Figure 1
–0.2
1.8
0.2
2.8
V
V
Steady-state common-mode output
voltage
2.4
Change in steady-state common-mode
output voltage(2)
V
–0.1
0.1
10
IO
Output current with power off
High-level input current
Low-level input current
VCC = 0 ,
VO = –7 V to 12 V
–10
–100
–100
–250
µA
µA
µA
mA
IIH
IIL
VI = 2 V
VI = 0.8 V
IOS
Short-circuit output current
–7 V ≤ VO ≤ 12 V
±70
5.5
250
9
Receiver disabled and
driver enabled
VI = 0 or VCC
No load
,
Receiver disabled and
driver disabled
ICC
Supply current
0.5
8.5
1
mA
Receiver enabled and
driver enabled
15
(1) All typical values are at VCC = 5 V, TA = 25°C.
(2) Δ | VOD | and Δ | VOC | are the changes in the steady-state magnitude of VOD and VOC, respectively, that occur when the input is
changed from a high level to a low level.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2
TYP
6
MAX
12
12
1
UNIT
ns
tPLH
tPHL
tsk(p)
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Pulse skew ( | tPLH – tPHL | )
2
6
ns
RL = 54 Ω, CL = 50 pF,
See Figure 3
0.3
7.5
7.5
12
12
12
12
ns
Differential output signal rise time
4
4
11
11
22
22
22
22
ns
tf
Differential output signal fall time
ns
tPZH
tPZL
tPHZ
tPLZ
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
RL = 110 Ω, See Figure 4
RL = 110 Ω, See Figure 5
RL = 110 Ω, See Figure 4
RL = 110 Ω, See Figure 5
ns
ns
ns
ns
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RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1) MAX UNIT
VIT+ Positive-going input threshold voltage
VIT– Negative-going input threshold voltage
IO = –8 mA
IO = 8 mA
0.2
V
V
–0.2
Vhys Hysteresis voltage ( VIT+ – VIT–
)
50
–0.8
4.9
mV
V
VIK Enable-input clamp voltage
II = –18 mA
–1.5
4
VOH High-level output voltage
VOL Low-level output voltage
VID = 200 mV, IOH = –8 mA
VID = –200 mV, IOL = 8 mA
VO = 0 V to VCC
V
0.1
0.8
1
V
IOZ
IIH
IIL
High-impedance-state output current
High-level enable-input current
Low-level enable-input current
–1
–100
–100
µA
µA
µA
VIH = 2.4 V
VIL = 0.4 V
VI = 12 V,
VCC = 5 V
0.4
0.5
1
1
VI = 12 V,
VCC = 0
II
Bus input current
Supply current
Other input at 0 V
mA
mA
VI = –7 V,
VCC = 5 V
–0.8
–0.8
–0.4
–0.3
VI = –7 V,
VCC = 0
Receiver enabled and driver disabled
Receiver disabled and driver disabled
Receiver enabled and driver enabled
4.5
0.5
8.5
7.5
1
VI = 0 or VCC
No load
,
ICC
15
(1) All typical values are at VCC = 5 V and TA = 25°C.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VID = –1.5 V to 1.5 V, See Figure 7
See Figure 7
MIN TYP
MAX
UNIT
ns
tPLH
tPHL
tsk(p)
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Pulse skew ( | tPHL – tPLH | )
7
7
13
13
20
20
ns
0.5
2.1
2.1
30
1.5
3.3
3.3
45
ns
Output signal rise time
ns
tf
Output signal fall time
ns
tPZH
tPZL
tPHZ
tPLZ
Output enable time to high level
Output enable time to low level
Output disable time from high level
Output disable time from low level
ns
30
45
ns
CL = 10 pF, See Figure 8
20
40
ns
20
40
ns
PARAMETER MEASUREMENT INFORMATION
Ω
Ω
27
27
V
OD
0 or 3 V
V
OC
Figure 1. Driver VOD and VOC
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PARAMETER MEASUREMENT INFORMATION (continued)
V
test
R1
375 Ω
Y
Z
D
R
L
= 60 Ω
V
OD
0 V or 3 V
R2
375 Ω
−7 V < V
< 12 V
test
V
test
Figure 2. Driver VOD
3 V
Input
t
1.5 V
1.5 V
C = 50 pF
(see Note B)
L
0 V
R
L
= 54 Ω
t
PLH
PHL
Generator
(see Note A)
V
O
50 Ω
≈ 1.5 V
10%
90%
50%
Output
3 V
≈ − 1.5 V
t
r
t
f
TEST CIRCUIT
VOLTAGE WAVEFORMS
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 3. Driver Test Circuit and Voltage Waveforms
Output
3 V
S1
Input
1.5 V
1.5 V
3 V
0 V
0.5 V
t
PZH
R = 110 Ω
L
C = 50 pF
(see Note B)
L
V
OH
Generator
(see Note A)
Output
50 Ω
2.3 V
V
off
≈ 0 V
t
PHZ
TEST CIRCUIT
VOLTAGE WAVEFORMS
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 4. Driver Test Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
5 V
3 V
0 V
Input
1.5 V
1.5 V
R = 110 Ω
L
S1
Output
0 V
t
PZL
t
PLZ
C = 50 pF
(see Note B)
L
5 V
0.5 V
Generator
(see Note A)
50 Ω
2.3 V
Output
V
OL
TEST CIRCUIT
VOLTAGE WAVEFORMS
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 5. Driver Test Circuit and Voltage Waveforms
I
O
V
ID
V
O
Figure 6. Receiver VOH and VOL
3 V
0 V
Input
1.5 V
1.5 V
Input
Generator
(see Note A)
Output
50 Ω
t
1.5 V
0 V
PHL
t
PLH
C
L
= 10 pF
(see Note B)
V
OH
90%
Output
1.3 V
10%
1.3 V
V
OL
t
r
t
f
TEST CIRCUIT
VOLTAGE WAVEFORMS
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 7. Receiver Test Circuit and Voltage Waveforms
8
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PARAMETER MEASUREMENT INFORMATION (continued)
S1
1.5 V
S2
2 kΩ
−1.5 V
5 V
C
= 10 pF
L
5 kΩ
(see Note B)
Input
Generator
(see Note A)
50 Ω
S3
TEST CIRCUIT
3 V
S1 to 1.5 V
S2 Open
3 V
S1 to −1.5 V
S2 Closed
S3 Open
Input
Input
1.5 V
1.5 V
S3 Closed
0 V
0 V
t
PZH
t
PZL
V
OH
≈ 4.5 V
1.5 V
Output
Output
Input
1.5 V
0 V
V
OL
3 V
3 V
S1 to 1.5 V
S2 Closed
S3 Closed
S1 to −1.5 V
S2 Closed
S3 Closed
1.5 V
1.5 V
Input
t
0 V
0 V
PHZ
t
PLZ
≈ 1.3 V
V
OH
0.5 V
Output
0.5 V
Output
V
OL
≈ 1.3 V
VOLTAGE WAVEFORMS
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 8. Receiver Output Enable and Disable Times
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TYPICAL CHARACTERISTICS
Receiver Output
Driver Input
120 Ω
120 Ω
Driver Input
Receiver Output
Figure 9. Typical Waveform of Nonreturn-to-Zero (NRZ), Pseudorandom Binary Sequence (PRBS) Data at
100 Mbps Through 15m, of CAT 5 Unshielded Twisted Pair (UTP) Cable
TIA/EIA-485-A defines a maximum signaling rate as that in which the transition time of the voltage transition of a
logic-state change remains less than or equal to 30% of the bit length. Transition times of greater length perform
quite well even though they do not meet the standard by definition.
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TYPICAL CHARACTERISTICS (continued)
AVERAGE SUPPLY CURRENT
LOGIC INPUT CURRENT
vs
vs
FREQUENCY
INPUT VOLTAGE
40
35
−30
−25
−20
V
T
A
= 5 V
= 25°C
CC
Driver
R
L
C
L
= 54 Ω
= 50 pF
30
25
V
T
= 5 V
= 25°C
CC
−15
−10
20
15
10
A
50% Duty Cycle
Receiver
−5
0
C
L
= 10 pF
0.5
5
0
0
1
2
3
4
5
0.05
1
2
5
10
20
30
V − Input Voltage − V
I
f − Frequency − MHz
Figure 10.
Figure 11.
BUS INPUT CURRENT
vs
INPUT VOLTAGE
DRIVER LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
800
600
400
200
0
2
V
T
= 5 V
= 25°C
CC
V
T
A
= 5 V
= 25°C
A
CC
1.75
1.50
1.25
1
0.75
0.50
−200
−400
−600
0.25
0
0
10
I
20
30
40
50
60
70
80
−8 −6 −4 −2
0
2
4
6
8
10 12
− Low-Level Output Current − mA
V − Input Voltage − V
I
OL
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
PROPAGATION DELAY TIME
vs
vs
HIGH-LEVEL OUTPUT CURRENT
CASE TEMPERATURE
5
4.5
4
14
13
T
= 25°C
A
Receiver
12
V
CC
= 5.25 V
V
CC
= 5 V
Driver Tested Per Figure 3
Receiver Tested Per Figure 7
Square Wave Input at 50%
Duty Cycle
3.5
3
11
10
2.5
V
CC
= 5 V
9
8
2
V
CC
= 4.75 V
1.5
1
7
Driver
6
5
0.5
0
−50
0
50
100
0
−10 −20 −30 −40 −50 −60 −70 −80
Case Temperature −
C
°
I
− High-Level Output Current − mA
OH
Figure 14.
Figure 15.
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APPLICATION INFORMATION
SN65LBC180A
SN75LBC180A
SN65LBC180A
SN75LBC180A
R
T
R
T
Up to 32
Unit Loads
A. The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line
should be kept as short as possible. One SN65LBC180A typically represents less than one unit load.
Figure 16. Typical Application Circuit
Revision History
Copyright © 2000–2009, Texas Instruments Incorporated
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Product Folder Link(s): SN65LBC180A SN75LBC180A
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
SN65LBC180AD
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
D
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
BL180A
SN65LBC180ADG4
SN65LBC180ADR
SN65LBC180ADRG4
SN65LBC180AN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
D
N
50
2500
2500
25
Green (RoHS
& no Sb/Br)
-40 to 85
BL180A
Green (RoHS
& no Sb/Br)
-40 to 85
BL180A
Green (RoHS
& no Sb/Br)
-40 to 85
BL180A
Pb-Free
(RoHS)
-40 to 85
65LBC180A
SN65LBC180ANE4
SN75LBC180AD
ACTIVE
ACTIVE
PDIP
SOIC
N
D
14
14
TBD
Call TI
Call TI
-40 to 85
0 to 70
50
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LB180A
SN75LBC180ADG4
SN75LBC180ADR
SN75LBC180ADRG4
SN75LBC180AN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
D
D
D
N
14
14
14
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
LB180A
2500
2500
25
Green (RoHS
& no Sb/Br)
LB180A
Green (RoHS
& no Sb/Br)
LB180A
Pb-Free
(RoHS)
75LBC180A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Apr-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN65LBC180ADR
SN75LBC180ADR
SOIC
SOIC
D
D
14
14
2500
2500
330.0
330.0
16.4
16.4
6.5
6.5
9.0
9.0
2.1
2.1
8.0
8.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Apr-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65LBC180ADR
SN75LBC180ADR
SOIC
SOIC
D
D
14
14
2500
2500
333.2
333.2
345.9
345.9
28.6
28.6
Pack Materials-Page 2
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