SN65LVCP1414RLJR [TI]

14.2Gbps 四通道、双模线性均衡器 | RLJ | 38 | -40 to 85;


型号：	SN65LVCP1414RLJR
厂家：	TEXAS INSTRUMENTS
描述：	14.2Gbps 四通道、双模线性均衡器 \| RLJ \| 38 \| -40 to 85 电信电信集成电路
文件：	总27页 (文件大小：776K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN65LVCP1414

www.ti.com.cn

ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

14.2Gbps 四通道、双模式线性均衡器

查询样片: SN65LVCP1414

特性

说明

•

背板和线缆连接串行运行数据速率高达 14.2Gbps

的四通道、单向、多速率、双模式线性均衡器

SN65LVCP1414 是一款异步、协议无关、低延迟、四

通道线性均衡器，此均衡器针对高达 14.2Gbps 的数据

速率，以及针对背板或有源线缆应用中的损耗补偿进行

了优化。 SN65LVCP1414 的架构设计用于与一个特定

用途集成电路 (ASIC) 或者一个现场可编程栅极阵列

(FPGA)（采用判决反馈均衡器 (DFE) 来实现数字均

衡）一起运行。 SN65LVCP1414 线性均衡器保持已发

送信号的波形，以确保最优 DFE 性能。

线性均衡增加了系统执行判决反馈均衡器 (DFE) 时

的链路裕量

针对背板模式或者线缆模式，在具有 1dB 阶跃控制

的 7.1GHz 上可实现 17dB 模拟均衡

•

输出线性动态范围：1200mV

带宽：> 20GHz - 典型值

7.1GHz 上，好于 15dB 的回波损耗

支持带外 (OOB) 信令

SN65LVCP1414 在充分发挥 DFE 效率的同时提供了

一个低功耗解决方案。

低功耗，2.5V VCC 时，每通道为 80mW（典型

值）

SN65LVCP1414 可经由 I²C 或者 GPIO 接口进行配

置。 SN65LVCP1414 的 I²C 接口使得用户能够独立地

控制均衡、路径增益、和针对每个独立通道的输出动态

范围。在 GPIO 模式下，通过使用 GPIO 输入引脚，

可为所有通道设置均衡、路径增益、和输出动态范围。

•

38 端子 QFN（四方扁平、无引线）5mm x 7mm

x 0.75mm，0.5mm 端子间距

到 100Ω 差分印刷电路板 (PCB) 传输线路的出色阻

抗匹配

•

通用输入输出接口 (GPIO) 或者 I²C 控制

SN65LVCP1414 输出可由 I²C 单独禁用。

2.5V 和 3.3V±5% 单电源

SN65LVCP1414 在一个 2.5V 或者 3.3V 单电源下运

行。

2kV 静电放电 (ESD) 人体模型 (HBM)

流经阳引脚的数据流简化了路由访问

小型封装尺寸节省了电路板空间

低功率

SN65LVCP1414 采用 38 引脚 5mm x 7mm x 0.75mm

QFN（四方扁平无引线）无铅 0.5mm 焊球间距封装，

额定运行温度范围 -40°C 至 85°C。

应用范围

•

电信和数据通信中的高速连接

针对 10GbE，16GFC，10G 同步光网络

(SONET)，SAS，SATA，通用公共无线接口

(CPRI)，开放基站架构协议

(OBSAI)，Infiniband，10GBase-KR，和 XFI/SFI

的背板和线缆连接

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

English Data Sheet: SLLSEC5

SN65LVCP1414

ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

www.ti.com.cn

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Backplane Application

LVCP1414

ASP

Serdes

ASIC

ASP

Serdes

ASIC

LVCP1414

Figure 1. Typical Backplane Application – Trace Mode

Cable Application

Active Cable

ASP

Serdes

ASIC

Serdes

ASIC

Figure 2. Typical Cable Application – Cable Mode

SN65LVCP1414

www.ti.com.cn

ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

Block Diagram (GPIO or I²C Mode)

A simplified block diagram of the SN65LVCP1414 is shown in Figure 3 for GPIO or I²C input control mode. This

compact, low power, 14.2Gbps quad-channel dual-mode linear analog equalizer consists of four high-speed data

paths and an input GPIO pin logic-control block and a two-wire interface with a control-logic block.

VCC

GND

VBB

VCC

Input Buffer

with

Selectable

Equalizer

50 ꢀ 50 ꢀ

50 ꢀ

Output

Driver

50 ꢀ

IN[3:0]_P

IN[3:0]_N

OUT[3:0]_P

OUT[3:0]_N

Band-Gap Voltage

Reference and Bias

Current Generation

Power-On

Reset

REXT

1.2 kꢀ

VCC

200 kꢀ 200 kꢀ

General Setting

EQ Control

Channel Enable

VOD Swing

DC Gain

6 Bit Register

DRV_PK#/SCL

3 Bit Register

4 Bit Register

1 Bit Register

2 Bit Register

AC Gain

I2C_EN

SDA

I2C_EN

SDA

PWD#

EQ0/ADD0

PWD#

VOD/CS

GAIN

EQ1/ADD1

VOD/CS

GAIN

EQ_MODE/ADD2

2-Wire Interface & Control Logic

200 kꢀ

Figure 3. Simplified Block Diagram of the SN65LVCP1414

SN65LVCP1414

ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

www.ti.com.cn

Package

The package pin locations and assignments are shown in Figure 4. The SN65LVCP1414 is packaged in a 5mm

x 7mm x 0.75mm, 38 pin, 0.5mm pitch lead-free QFN.

IN0_P

IN0_N

VCC

OUT0_P

OUT0_N

VCC

SN65LVCP1414 Pinout

38 pin QFN (RLJ) Package

5mm x 7mm with 0.5mm pitch

IN1_P

IN1_N

VCC

OUT1_P

OUT1_N

VCC

It is required for thermal pad to be soldered to ground

for better thermal performance

VCC

OUT2_P

OUT2_N

IN2_P

IN2_N

VCC

OUT3_P

IN3_P

IN3_N

OUT3_N

Figure 4. Package Drawing (Top View)

SN65LVCP1414

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ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

Pin Descriptions

PINS

DIRECTION TYPE

SUPPLY

DESCRIPTION

NAME

NO.

DIFFERENTIAL HIGH-SPEED I/O

Input, (with 50 Ω

termination to input

common mode)

IN0_P

IN0_N

Differential input, lane 0

Input, (with 50 Ω

termination to input

common mode)

IN1_P

IN1_N

Differential input, lane 1

Differential input, lane 2

Differential input, lane 3

Input, (with 50 Ω

termination to input

common mode)

IN2_P

IN2_N

Input, (with 50 Ω

termination to input

common mode)

IN3_P

IN3_N

OUT0_P

OUT0_N

Output

Differential output, lane 0

Differential output, lane 1

Differential output, lane 2

Differential output, lane 3

OUT1_P

OUT1_N

OUT2_P

OUT2_N

OUT3_P

OUT3_N

CONTROL SIGNALS

SDA 14

I²C mode

Input Output, Open

drain

GPIO mode

No action needed

I²C data. Connect a 10kΩ pull-up resistor externally

I²C mode

DRV_PK#/SCL 15

Input. (with 200kΩ

pull-up)

GPIO mode

HIGH: disable Driver peaking

I²C clock. Connect a 10kΩ pull-up resistor externally

LOW: enables Driver 6dB AC

peaking

Configures the device operation for I²C or GPIO mode:

HIGH: enables I²C mode

I2C_EN

VOD/CS

Input, (wtih 200kΩ

pull-down)

2.5V/3.3V CMOS

LOW: enables GPIO mode

I²C mode

Input, (with 200kΩ

pull-down)

2.5V/3.3V CMOS

GPIO mode

HIGH: set high VOD range

LOW: set low VOD range

HIGH: acts as Chip Select

LOW: disables I²C interface

REXT

Input, Analog

External Bias Resistor:

1,200 Ω to GND

I²C mode

EQ0/ADD0

Input, 2.5V/3.3V

CMOS - 3-state

GPIO mode

Working with EQ1 to determine input

EQ gain.

ADD0 along with pins ADD1 and ADD2 comprise the three bits of

I²C slave address.

ADD2:ADD1:ADD0:XXX

SN65LVCP1414

ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

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Pin Descriptions (continued)

PINS

DIRECTION TYPE

DESCRIPTION

SUPPLY

NAME

NO.

I²C mode

EQ1/ADD1

Input, 2.5V/3.3V

CMOS - 3-state

GPIO mode

Working with EQ0 to determine input

EQ gain steps of approximately 2dB

ADD1 along with pins ADD0 and ADD2 comprise the three bits of

I²C slave address

ADD2:ADD1:ADD0:XXX

EQ1

EQ0

GAIN

GND

HiZ

GND

HiZ

000

001

010

011

100

101

110

111

VCC

GND

HiZ

VCC

GND

HiZ

VCC

EQ1 and EQ0 works with AC_GAIN and DC_GAIN to determine final EQ gain as this:

EQ1/

EQ0

GAIN

(dB)

EQ GAIN

(dB)

000 ~ 111

LOW

HiZ

-6

1 ~ 9

7 ~ 17

1 ~ 9

HiGH

I²C mode

EQ_MODE/

ADD2

Input, (with 200kΩ

pull-down),

2.5V/3.3V CMOS

GPIO mode

HIGH: Trace mode

LOW: Cable mode

ADD2 along with pins ADD1 and ADD0 comprise the three bits of

I²C slave address.

ADD2:ADD1:ADD0:XXX

I²C mode

No action needed

GAIN

Input, 2.5V/3.3V

CMOS - 3-state

GPIO mode

Work with EQ1/EQ0 to set total EQ

Gain. See table above.

PWD#

Input, (with 200kΩ

HIGH: Normal Operation

LOW: Power downs the device, inputs off and outputs disabled, resets I²C

pull-up),

2.5V/3.3V CMOS

POWER SUPPLY

VCC

3, 6, 7,

10, 13,

19, 22,

25, 26,

29, 32,

Power

Power supply 2.5V±5%, 3.3V±5%

GND Center

Pad

Ground

The ground center pad is the metal contact at the bottom of the package. This pad must be connected to

the GND plane. At least 15 PCB vias are recommended to minimize inductance and provide a solid

ground. Refer to the package drawing (RLJ-package) for the via placement.

SN65LVCP1414

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ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUES

UNIT

V_CC

Supply voltage range⁽²⁾

–0.3 to 4

V_IN,DIFF

V_{IN+, IN–}

V_IO

Differential voltage between INx_P and INx_N

Voltage at Inx_P and fINx_N

±2.5

–0.5 V to VCC+0.5

Voltage on control IO pins

–0.5 V to VCC+0.5

I_IN+I_IN–

I_OUT+I_OUT–

Continuous current at high speed differential data inputs (differential)

Continuous current at high speed differential data outputs

Human Body Model⁽³⁾(All Pins)

–25 to 25

2.0

ESD

Charged-Device Model⁽⁴⁾(All Pins)

500

Moisture sensitivity level

Reflow temperature package soldering, 4 sec

260

°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.

(4) Tested in accordance with JEDEC Standard 22, Test Method C101.

Thermal Information

SN65LVCP1414

THERMAL METRIC⁽¹⁾

UNITS

RLJ (38 PINS)

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

36.9

22.3

10.7

0.3

θ_JCtop

θ_JB

°C/W

ψ_JT

ψ_JB

10.6

1.9

θ_JCbot

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

SN65LVCP1414

ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

www.ti.com.cn

Recommended Operating Conditions

MIN

NOM

MAX

UNIT

Gbps

Operating data rate

Supply voltage

14.2

2.625

3.465

125

V_CC

2.375

3.135

–10

2.5

3.3

Supply voltage

Junction temperature

Maximum board temperature

°C

CMOS DC SPECIFICATIONS

V_IH

High-level input voltage

0.8×V_CC

V_CC×0.4

–0.5

V_MID

Mid-level input voltage

Low-level input voltage

Bandgap circuit PSNR

V_CC×0.6

0.2×V_CC

V_IL

PSNR BG

Electrical Characteristics (VCC 2.5V ±5%)

over operating free-air temperature range, all parameters are referenced to package pins (unless otherwise noted)

PARAMETER

POWER CONSUMPTION

TEST CONDITIONS

MIN TYP⁽¹⁾

MAX UNIT

PD_L

PD_H

Device power dissipation

VOD = LOW at 2.5V VCC with all 4 channels active

VOD = HIGH, at 2.5V VCC with all 4 channels active

317

485

475

675

Device power with all 4 channels

switched off

PD_OFF

Refer to I²C section for device configuration. 2.5V VCC

(1) All typical values are at 25°C and with 2.5V supply unless otherwise noted.

Electrical Characteristics (VCC 3.3V ±5%)

over operating free-air temperature range, all parameters are referenced to package pins (unless otherwise noted)

PARAMETER

POWER CONSUMPTION

TEST CONDITIONS

MIN TYP⁽¹⁾

MAX UNIT

PD_L

PD_H

Device power dissipation

VOD = LOW at 3.3V VCC with all 4 channels active

VOD = HIGH, at 3.3V VCC with all 4 channels active

450

697

625

925

Device power with all 4 channels

switched off

Refer to I²C section for device configuration, 3.3V

VCC

PD_OFF

(1) All typical values are at 25°C and with 2.5V supply unless otherwise noted.

Electrical Characteristics (VCC 2.5V ±5%, 3.3V ±5%)

over operating free-air temperature range, all parameters are referenced to package pins (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾MAX

UNIT

CMOS DC SPECIFICATIONS

I_IH

I_IL

High level input current

Low level input current

VIN = 0.9 × V_CC

VIN = 0.1 × V_CC

-40

µA

CML INPUTS (IN[3:0]_P, IN[3:0]_N)

r_IN

Differential input resistance

Input linear dynamic range

Input common mode voltage

INx_P to INx_N

Gain = 0.5

100

1200

mV_pp

V_IN

V_ICM

Internally biased

V_CC–0.8

Input differential to common mode

conversion

SCD11

SDD11

100MHz to 7.1GHz

–20

–15

Differential input return loss

(1) All typical values are at 25°C and with 2.5V and 3.3V supply unless otherwise noted.

SN65LVCP1414

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ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

Electrical Characteristics (VCC 2.5V ±5%, 3.3V ±5%) (continued)

over operating free-air temperature range, all parameters are referenced to package pins (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾MAX

UNIT

CML OUTPUTS (OUT[3:0]_P, OUT[3:0]_N)

R_L= 100 Ω, V_OD= HIGH

1200

600

mV_pp

V_OD

Output linear dynamic range

R_L= 100 Ω, V_OD= LOW

R_L= 100 Ω, 0 V applied at inputs

See Figure 5

V_OS

Output offset voltage

V_OCM

Output common mode voltage

V_CC-0.4

K28.5 pattern at 14.2Gbps on all 4 channels,

No interconnect loss, VOD = HIGH

V_CM,RIP

V_OD,RIP

Common mode output ripple

Differential path output ripple

20 mV_RMS

K28.5 pattern at 14.2Gbps on all channels,

No interconnect loss, VIN = 1200mVpp.

mV_pp

Change in steady-state common-

mode output voltage between logic

states

V_OC(SS)

±10

t_R

Rise time⁽²⁾

Fall time⁽²⁾

Input signal with 30ps rise time, 20% to 80%, See Figure 7

Input signal with 30ps fall time, 20% to 80%, See Figure 7

100MHz to 7.1GHz

–15

–5

t_F

SDD22

SCC22

t_PLH

Differential output return loss

Common-mode output return loss

Low-to-high propagation delay

High-to-low propagation delay

Inter-Pair (lane to lane) output skew⁽³⁾All outputs terminated with 100 Ω, See Figure 8

Part-to-part skew⁽⁴⁾

100MHz to 7.1GHz

See Figure 6

t_PHL

t_SK(O)

t_SK(PP)

All outputs terminated with 100 Ω

Single ended on-chip termination to VCC, Outputs will be AC

coupled

r_OT

Single ended output resistance

rp - rn

Drom = 2´

´100

r_OM

Output termination mismatch at 1MHz

Channel-to-channel isolation

rp + rn

Ch_iso

Frequency at 7.1GHz

400

500

10MHz to 7.1GHz, No other noise source present, VOD = LOW

10MHz to 7.1GHz, No other noise source present, VOD = HIGH

µVRMS

OUT_NOISEOutput referred noise⁽⁵⁾

EQUALIZATION

EQ_Gain

At 7.1GHz input signal

Equalization Gain, EQ = MAX

Input signal with 3.75 pre-cursor and measure it on the output

signal,

Vpre

Output pre-cursor pre-emphasis

3.75

Refer Figure 9. Vpre = 20log(V3/V2)

Input signal with 12dB post-cursor and measure it on the output

signal,

Refer Figure 9, Vpst = 20log(V1/V2)

Vpst

DJ1

Output post-cursor pre-emphasis

Transmit Side application

Residual deterministic jitter at 10.3125

Gbps

Tx launch Amplitude = 0.6Vpp, EQ=0, ACGain and DCgain =

Low and VOD = High, Trace Mode Test Channel -> 0”, See

Figure 11

0.016

UIp-p

Receive Side Application

Residual deterministic jitter at 10.3125

Gbps

Tx launch Amplitude = 0.6Vpp, EQ=7, ACGain and VOD = High

and DCGain = High, Trace Mode Test Channel -> 12” (9dB loss

at 5GHz), See Figure 10

DJ2

DJ3

DJ4

0.11

0.041

0.13

UIp-p

Transmit Side Application

Residual deterministic jitter at 14.2

Gbps

Tx launch Amplitude = 0.6Vpp, EQ=0, ACGain and DCgain =

Low and VOD = High, Trace Mode Test Channel -> 0”, See

Figure 11

Receive Side Application

Residual deterministic jitter at 14.2

Gbps

Tx launch Amplitude = 0.6Vpp, EQ=7, ACGain and VOD = High

and DCGain = High, Trace Mode Test Channel -> 8” (9dB loss

at 7GHz), See Figure 10

(2) Rise and Fall measurements include board and channel effects of the test environment, refer to Figure 10 and Figure 11.

(3) t_SK(O)is the magnitude of the time difference between the channels.

(4) t_SK(PP)is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(5) All noise sources added.

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Parameter Measurement Information

49.9 W

OUT+

OCM

OUT-

49.9 W

1pF

Figure 5. Common Mode Output Voltage Test Circuit

= 0 V

PHL

PLH

= 0 V

OUT

Figure 6. Propagation Delay Input to Output

Figure 7. Output Rise and Fall Times

OUTx

SK(0)

OUTy

Figure 8. Output Inter-Pair Skew

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ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

Not drawn to scale

Figure 9. Vpre and Vpost (test pattern is 1111111100000000 (8-1s, 8-0s))

TEST

CHANNEL

CHARACTERIZATION

BOARD

SN65LVCP1414

PATTERN

OSCILLOSCOPE

L = 2"

OUT

GENERATOR

Figure 10. Receive Side Performance Test Circuit

CHARACTERIZATION

BOARD

TEST

CHANNEL

SN65LVCP1414

PATTERN

GENERATOR

OSCILLOSCOPE

L = 2"

OUT

Figure 11. Transmit Side Performance Test Circuit

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Equivalent Input and Output Schematic Diagrams

VCC

IN+

R_T(SE)

= 50 W

Gain

Stage

+EQ

VCC

RBBDC

R_T(SE)

= 50 W

IN-

LineEndTermination

VBB

ESD

Self-Biasing Network

Figure 12. Equivalent Input Circuit Design

VCC

48 kW

ESD

48 kW

Figure 13. 3-Level Input Biasing Network

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Typical Characteristics

Typical operating condition is at V_CC= 2.5V and T_A= 25°C, no interconnect line at the output, and with default device settings

(unless otherwise noted).

EQ=7, DCGAIN=LOW, ACGAIN=HIGH, VDD=HIGH

EQ=0, ACGAIN=LOW, DCGAIN=LOW, VDD=LOW

EQ=3, ACGAIN=LOW, DCGAIN=LOW, VDD=LOW

EQ=7, ACGAIN=LOW, DCGAIN=LOW, VDD=LOW

EQ=0, ACGAIN=HIGH, DCGAIN=LOW, VDD=LOW

EQ=3, ACGAIN=HIGH, DCGAIN=LOW, VDD=LOW

EQ=7, ACGAIN=HIGH, DCGAIN=LOW, VDD=LOW

−2

−4

−6

−8

0.1

100

Frequency (GHz)

G001

Figure 14. Typical EQ Gain Profile Curve

−5

−10

−20

−30

−40

−50

−60

−70

−10

−15

−20

−25

−30

−35

−40

−45

Frequency (GHz)

G002

G003

Figure 15. Differential Input Return Loss

Figure 16. Differential to Common Mode Conversion

SN65LVCP1414

ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

www.ti.com.cn

Typical Characteristics (continued)

Typical operating condition is at V_CC= 2.5V and T_A= 25°C, no interconnect line at the output, and with default device settings

(unless otherwise noted).

−5

−10

−15

−20

−25

−30

−35

−40

−45

−10

−15

−20

−25

−30

−35

−40

Frequency (GHz)

G004

G005

Figure 17. Differential Output Return Loss

Figure 18. Common Mode Output Return Loss

0.25

0.2

0.15

0.1

0.05

−5

3 meter

6 meter

6 meter (See Note A)

3 meter

6 meter

6 meter (See Note A)

−10

−15

−20

−25

−30

−35

−40

−45

200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k

Time (ps)

Frequency (GHz)

G006

G007

A. With SN65LVCP1414 -> EQ = 4, VOD = High, ACGain = HiZ,

DCGain = Low

Figure 19. Cable Mode – Symbol Response

Figure 20. Cable Mode – Frequency Domain

SN65LVCP1414

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ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

Typical Characteristics (continued)

Typical operating condition is at V_CC= 2.5V and T_A= 25°C, no interconnect line at the output, and with default device settings

(unless otherwise noted).

0.35

3 meter

6 meter

6 meter (See Note A)

6 meter

6 meter (See Note A)

−5

0.3

−10

−15

−20

−25

−30

−35

−40

−45

−50

0.25

0.2

0.15

0.1

0.05

200 400 600 800 1k

Time (ps)

Frequency (GHz)

G008

G009

A. With SN65LVCP1414 -> EQ = 7, VOD = High, ACGain = High,

DCGain = Low

Figure 21. Trace Mode – Symbol Response

Figure 22. Trace Mode - Frequency Domain

Table 1. Control Settings Descriptions

EQ GAIN

(dB)

MODE

DCGAIN

ACGAIN<1:0>

EQ<2:0>

000 to 111

DC GAIN (dB)

APPLICATION

Short Input Trace; Large Input

Swing

–6

1 to 9

7 to 17

1 to 9

Long Input Trace; Large Input

Swing

Short Input Trace; Small Input

Swing

Short Input Trace; Small Input

Swing

2 to 10

1 to 9

Short Input Cable; Large Input

Swing

–6

Long Input Cable; Large Input

Swing

7 to 17

1 to 9

Short Input Cable; Small Input

Swing

Short Input Cable; Small Input

Swing

2 to 10

Table 2. Control Settings Descriptions

GAIN

Low

DC GAIN

ACGAIN<1:0>

HighZ

High

SN65LVCP1414

ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

www.ti.com.cn

Two-Wire Serial Interface and Control Logic

The SN65LVCP1414 uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCL, are

driven, respectively, by the serial data and serial clock from a microcontroller, for example. The SDA and SCK

pins require external 10kΩ pull-ups to VCC.

The 2-wire interface allows write access to the internal memory map to modify control registers and read access

to read out control and status signals. The SN65LVCP1414 is a slave device only which means that it cannot

initiate a transmission itself; it always relies on the availability of the SCK signal for the duration of the

transmission. The master device provides the clock signal as well as the START and STOP commands. The

protocol for a data transmission is as follows:

1. START command

2. 7 bit slave address (0000ADD[2:0]) followed by an eighth bit which is the data direction bit (R/W). A zero

indicates a WRITE and a 1 indicates a READ. The ADD[2:0] address bits change with the status of the

ADD2, ADD1, and ADD0 device pins, respectively. If the pins are left floating or pulled down, the 7 bit slave

address is 0000000.

3. 8 bit register address

4. 8 bit register data word

5. STOP command

Regarding timing, the SN65LVCP1414 is I²C compatible. The typical timing is shown in Figure 9 and a complete

data transfer is shown in Figure 10. Parameters for Figure 9 are defined in Table 3.

Bus Idle: Both SDA and SCL lines remain HIGH

Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH,

defines a START condition (S). Each data transfer is initiated with a START condition.

Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH

defines a STOP condition (P). Each data transfer is terminated with a STOP condition; however, if the master still

wishes to communicate on the bus, it can generate a repeated START condition and address another slave

without first generating a STOP condition.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and

is determined by the master device. The receiver acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. The

transmitter releases the SDA line and a device that acknowledges must pull down the SDA line during the

acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the

acknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver doesn’t

acknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate a

STOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some time

later in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated by

the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the

master generates the STOP condition.

Figure 23. Two-Wire Serial Interface Timing Diagram

SN65LVCP1414

www.ti.com.cn

SYMBOL

ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

Table 3. Two-Wire Serial Interface Timing Diagram Definitions

PARAMETER

MIN

MAX UNIT

f_SCL

SCL clock frequency

400

kHz

μs

t_BUF

Bus free time between START and STOP conditions

Hold time after repeated START condition. After this period, the first clock pulse is generated

Low period of the SCL clock

1.3

0.6

1.3

0.6

t_HDSTA

t_LOW

t_HIGH

t_SUSTA

t_HDDAT

t_SUDAT

t_R

High period of the SCL clock

Setup time for a repeated START condition

Data HOLD time

Data setup time

100

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

300

t_F

t_SUSTO

0.6

Figure 24. Two-Wire Serial Interface Data Transfer

SN65LVCP1414

ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

www.ti.com.cn

The register mapping for read/write register addresses 0 (0x00) through 22 (0x18) are shown in Table 4. Table 5

describes the circuit functionality based on the register settings.

Table 4. SN65LVCP1414 Register Mapping Information

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

SW_GPIO

PWRDOWN

SYNC_01

SYNC_ 23

SYNC_ALL

EQ_MODE

RSVD

bit 7 bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

LN_EN_CH3

LN_EN_CH2

LN_EN_CH1

LN_EN_CH0

bit 7

bit 6

EQ2

bit 5

EQ1

bit 4

EQ0

bit 3

bit 2

bit 1

bit 0

RSVD

VOD_CTRL

DC_GAIN

AC_GAIN1

AC_GAIN0

bit 7 bit 6 bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

DRV_PEAK

EQ_EN

DRV_EN

bit 7

bit 6

EQ2

bit 5

EQ1

bit 4

EQ0

bit 3

bit 2

bit 1

bit 0

RSVD

VOD_CTRL

DC_GAIN

AC_GAIN1

AC_GAIN0

bit 7 bit 6 bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

DRV_PEAK

EQ_EN

DRV_EN

bit 7

bit 6

EQ2

bit 5

EQ1

bit 4

EQ0

bit 3

bit 2

bit 1

bit 0

RSVD

VOD_CTRL

DC_GAIN

AC_GAIN1

AC_GAIN0

bit 7 bit 6 bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

DRV_PEAK

EQ_EN

DRV_EN

bit 7

bit 6

EQ2

bit 5

EQ1

bit 4

EQ0

bit 3

bit 2

bit 1

bit 0

RSVD

VOD_CTRL

DC_GAIN

AC_GAIN1

AC_GAIN0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

DRV_PEAK

EQ_EN

DRV_EN

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

RSVD

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

RSVD

bit 7

bit 6

RSVD

SN65LVCP1414

www.ti.com.cn

ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

Table 5. SN65LVCP1414 Register Description

BIT

SYMBOL

FUNCTION

DEFAULT

Switching logic is controlled by GPIO or I²C:

0 = I²C control

SW_GPIO

1 = GPIO control

Power down the device:

0 = Normal operation

1 = Powerdown

PWRDOWN

SYNC_01

SYNC_23

All settings from channel 1 will be used for channel 0 and 1:

0 = Channel 0 tracking channel 1 settings

1 = No tracking tracking

All settings from channel 2 will be used for channel 2 and 3:

0 = Channel 3 tracking channel 2 settings

1 = No channel tracking

0x00

00000000

All settings from channel 1 will be used on all channels:

0 = All channels tracking channel 1

1 = No channel tracking

SYNC_ALL

Overwrites SYNC_01 and SYNC_23

Set EQ mode:

0 = Cable mode

1 = Trace mode

EQ_MD

RSVD

For TI use only

Channel 3 enable:

0 = Enable

1 = Disable

LN_EN_CH3

LN_EN_CH2

LN_EN_CH1

LN_EN_CH0

Channel 2 enable:

0 = Enable

1 = Disable

0x01

00000000

Channel 1 enable:

0 = Enable

1 = Disable

Channel 0 enable:

0 = Enable

1 = Disable

RSVD

EQ2

EQ1

EQ0

Equalizer adjustment setting:

000 = Minimum equalization setting

111 = Maximum equalization setting

Channel [x] VOD control:

0 = Low VOD range

1 = High VOD range

0x02

0x05

0x08

0x0B

VOD_CTRL

00000000

Channel [x] EQ DC gain:

0 = Set EQ DC gain to 0.5x

1 = Set EQ DC gain to 1x

DC_GAIN_CTRL

AC_GAIN_CTRL1

AC_GAIN_CTRL0

AC Gain Control:

00 = Low

01 = HiZ

11 = High

SN65LVCP1414

ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

www.ti.com.cn

DEFAULT

Table 5. SN65LVCP1414 Register Description (continued)

BIT

SYMBOL

FUNCTION

0x03

0x06

0x09

0x0C

Channel [x] driver peaking:

0 = Disables driver Peaking

DRV_PEAK

00000000

1 = Enables driver 6db AC Peaking

Channel [x] EQ stage enable:

0 = Enable

EQ_EN

1 = Disable

Channel [x] driver stage enable:

0 = Enable

DRV_EN

1 = Disable

RSVD

For TI use only

0x0F

0x11

0x12

00110000

00000000

RSVD

For TI use only

RSVD

For TI use only

SN65LVCP1414

www.ti.com.cn

ZHCSA35A –AUGUST 2012–REVISED JANUARY 2014

REVISION HISTORY

Changes from Original (August 2012) to Revision A

Page

•

Changed OUT2_P pin number from 23 to 24 ....................................................................................................................... 5

Changed OUT2_N pin number from 24 to 23 ...................................................................................................................... 5

Changed OUT3_P pin number from 20 to 21 ....................................................................................................................... 5

Changed OUT3_N pin number from 21 to 20 ...................................................................................................................... 5

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SN65LVCP1414RLJR

SN65LVCP1414RLJT

ACTIVE

WQFN

RLJ

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 85

LVCP

1414

ACTIVE

RLJ

NIPDAU

LVCP

1414

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Dec-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN65LVCP1414RLJR

SN65LVCP1414RLJT

WQFN

RLJ

3000

250

330.0

16.4

5.25

7.25

1.45

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Dec-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN65LVCP1414RLJR

SN65LVCP1414RLJT

WQFN

RLJ

3000

250

367.0

38.0

Pack Materials-Page 2

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SN65LVCP1414RLJR [TI]

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