SN65LVCP40RGZG4 [TI]
DC TO 4-GBPS DUAL 1:2 MULTIPLEXER/REPEATER/EQUALIZER; DC到4 Gbps的双1 ： 2多路复用器/中继器/均衡器
| 型号： | SN65LVCP40RGZG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DC TO 4-GBPS DUAL 1:2 MULTIPLEXER/REPEATER/EQUALIZER |
| 文件： | 总23页 (文件大小：1197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
DC TO 4-GBPS DUAL 1:2 MULTIPLEXER/REPEATER/EQUALIZER
FEATURES
•
48-Terminal QFN (Quad Flatpack)
7 mm × 7 mm × 1 mm, 0.5-mm Terminal Pitch
•
Receiver Equalization and Selectable Driver
Preemphasis to Counteract High-Frequency
Transmission Line Losses
•
Temperature Range: -40°C to 85°C
APPLICATIONS
•
•
•
•
•
Integration of Two-Serial Port
Selectable Loopback
•
•
•
Bidirectional Link Replicator
Signal Conditioner
XAUI 802.3ae Protocol Backplane
Redundancy
Typical Power Consumption 650 mW
30-ps Deterministic Jitter
On-Chip 100-Ω Receiver and Driver
Differential Termination Resistors Eliminate
External Components and Reflection from
Stubs
•
•
Host Adapter (Applications With Internal and
External Connection to SERDES)
Signaling Rates DC to 4 Gbps Including XAUI,
GbE, FC, HDTV
•
3.3-V Nominal Power Supply
DESCRIPTION
The SN65LVCP40 is a signal conditioner and data multiplexer optimized for backplanes. Input equalization and
programmable output preemphasis support data rates up to 4 Gbps. Common applications are redundancy
switching, signal buffering, or performance improvements on legacy backplane hardware.
The SN65LVCP40 combines a pair of 1:2 buffers with a pair of 2:1 multiplexers (mux). Selectable switch-side
loopback supports system testing. System interconnects and serial backplane applications of up to 4 Gbps are
supported. Each of the two independent channels consists of a transmitter with a fan-out of two, and a receiver
with a 2:1 input multiplexer.
The drivers provide four selectable levels of preemphasis to compensate for transmission line losses. The
receivers incorporates receive equalization and compensates for input transmission line loss. This minimizes
deterministic jitter in the link. The equalization is optimized to compensate for a FR-4 backplane trace with 5-dB,
high-frequency loss between 375 MHz and 1.875 GHz. This corresponds to a 24-inch long FR-4 trace with 6-mil
trace width.
This device operates from a single 3.3-V supply. The device has integrated 100-Ω line termination and provides
self-biasing. The input tolerates most differential signaling levels such as LVDS, LVPECL or CML. The output
impedance matches 100-Ω line impedance. The inputs and outputs may be ac coupled for best interconnectivity
with other devices such as SERDES I/O or additional XAUI multiplexer buffer. With ac coupling, jitter is the
lowest.
Programmable
Preemphasis
FUNCTIONAL DIAGRAM
Input Equalization
Opens up Data Eye
out
SN65LVCP40
EQ
Input Data After Long Backplane Trace
Output Data
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The SN65LVCP40 is packaged in a 7 mm × 7 mm × 1 mm QFN (quad flatpack no-lead) lead-free package, and
is characterized for operation from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICE(1)
TA
DESCRIPTION
RGZ (48 pin)
-40°C to 85°C
Serial multiplexer
SN65LVCP40
(1) The package is available taped and reeled. Add an R suffix to device types (e.g., SN65LVCP40RGZR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
–0.5 V to 6 V
–0.5 V to (VCC + 0.5 V)
–0.5 V to 4 V
4 kV
VCC
Supply voltage range(2)
Voltage range
Control inputs, all outputs
Receiver inputs
All pins
Human Body Model(3)
Charged-Device Model(4)
ESD
All pins
500 V
See Package Thermal Characteristics
Table
TJ
Maximum junction temperature
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
PACKAGE THERMAL CHARACTERISTICS
PACKAGE THERMAL CHARACTERISTICS(1)
NOM
33
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJA (junction-to-ambient)
θJB (junction-to-board)
20
4-layer JEDEC Board (JESD51-7) using eight GND-vias Ø-0.2 on the
center pad as shown in the section: Recommended pcb footprint with
boundary and environment conditions of JEDEC Board (JESD51-2)
θJC (junction-to-case)
23.6
0.6
PSI-jt (junction-to-top pseudo)
PSI-jb (junction-to-board pseudo)
θJP (junction-to-pad)
19.4
5.4
(1) See application note SPRA953 for a detailed explanation of thermal parameters (http://www-s.ti.com/sc/psheets/spra953/spra953.pdf).
2
Submit Documentation Feedback
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
4
UNIT
Gbps
V
dR
Operating data rate
VCC
VCC(N)
TJ
Supply voltage
3.135
3.3
3.465
20
Supply voltage noise amplitude
Junction temperature
10 Hz to 2 GHz
mV
°C
125
85
TA
Operating free-air temperature(1)
-40
°C
DIFFERENTIAL INPUTS
dR(in) ≤ 1.25 Gbps
100
100
100
1750
1560
1000
mVpp
mVpp
mVpp
Receiver peak-to-peak differential input
VID
1.25 Gbps < dR(in) ≤ 3.125 Gbps
dR(in) > 3.125 Gbps
voltage(2)
|V
*
|
ID
Receiver common-mode
input voltage
Note: for best jitter performance ac
coupling is recommended.
V
CC
VICM
1.5
1.6
V
2
CONTROL INPUTS
VIH
VIL
High-level input voltage
Low-level input voltage
2
VCC + 0.3
0.8
V
V
–0.3
DIFFERENTIAL OUTPUTS
RL Differential load resistance
80
100
120
Ω
(1) Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
(2) Differential input voltage VID is defined as | IN+ – IN– |.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
DIFFERENTIAL INPUTS
Positive going differential
input high threshold
VIT+
50
mV
Negative going differential
input low threshold
VIT–
–50
80
mV
dB
Ω
A(EQ)
RT(D)
Equalizer gain
From 375 MHz to 1.875 GHz
5
Termination resistance,
differential
100
120
Open-circuit Input voltage
(input self-bias voltage)
VBB
AC-coupled inputs
1.6
30
V
Biasing network dc
impedance
R(BBDC)
kΩ
375 MHz
42
Biasing network ac
impedance
R(BBAC)
Ω
1.875 GHz
8.4
DIFFERENTIAL OUTPUTS
VOH
VOL
High-level output voltage
RL = 100 Ω±1%,
650
mVpp
mVpp
PRES_1 = PRES_0=0;
PREL_1 = PREL_0=0; 4 Gbps alternating
1010-pattern;
Low-level output voltage
–650
Output differential voltage
without preemphasis(2)
VODB(PP)
VOCM
1000
1300
1.65
1500
mVpp
V
Figure 1
Output common mode voltage
Change in steady-state
See Figure 6
∆VOC(SS) common-mode output voltage
1
mV
between logic states
(1) All typical values are at TA = 25°C and VCC = 3.3 V supply unless otherwise noted. They are for reference purposes and are not
production tested.
(2) Differential output voltage V(ODB) is defined as | OUT+ – OUT– |.
3
Submit Documentation Feedback
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Output preemphasis voltage
ratio,
PREx_1:PREx_0 = 00
PREx_1:PREx_0 = 01
PREx_1:PREx_0 = 10
0
3
6
RL = 100 Ω ±1%;
x = L or S;
See Figure 1
V(PE)
dB
V
ODB(PP)
V
PREx_1:PREx_0 = 11
9
175
100
ODPE(PP)
Output preemphasis is set to 9 dB during test
PREx_x = 1;
Measured with a 100-MHz clock signal;
RL = 100 Ω, ±1%, See Figure 2
Preemphasis duration
measurement
t(PRE)
ps
Differential on-chip termination between OUT+ and
OUT–
ro
Output resistance
Ω
CONTROL INPUTS
IIH
High-level Input current
VIN = VCC
VIN = GND
5
µA
µA
kΩ
IIL
Low-level Input currentn
Pullup resistance
90
35
125
R(PU)
POWER CONSUMPTION
PD
Device power dissipation
All outputs terminated 100 Ω
650
880
254
mW
mA
All outputs
ICC
Device current consumption
PRBS 27-1 pattern at 4 Gbps
terminated 100 Ω
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MULTIPLEXER
t(SM) Multiplexer switch time
DIFFERENTIAL OUTPUTS
Low-to-high propagation
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
Multiplexer or loopback control to valid output
3
6
ns
tPLH
0.5
0.5
1
1
ns
ns
delay
Propagation delay input to output
See Figure 4
High-to-low propagation
delay
tPHL
tr
Rise time
80
80
ps
ps
ps
ps
ps
20% to 80% of VO(DB); Test Pattern: 100-MHz clock signal;
See Figure 3 and Figure 7
tf
Fall time
(2)
tsk(p)
tsk(o)
tsk(pp)
Pulse skew, | tPHL– tPLH
Output skew(3)
Part-to-part skew(4)
|
20
200
500
All outputs terminated with 100 Ω
25
See Figure 7for test circuit.
BERT setting 10–15
RJ
Device random jitter, rms
0.8
2
ps-rms
Alternating 10-pattern.
(1) All typical values are at 25°C and with 3.3 V supply unless otherwise noted.
(2) tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.
(3) tsk(o) is the magnitude of the time difference between the tPLH and tPHL of any two outputs of a single device.
(4) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4
Submit Documentation Feedback
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
SWITCHING CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
0 dB preemphasis
Intrinsic deterministic device (PREx_x = 0);
PRBS 27-1
pattern
4 Gbps
30
ps
jitter (5)(6), peak-to-peak
See Figure 7 for the test
circuit.
1.25 Gbps
Over 20-inch
FR4 trace
7
DJ
0 dB preemphasis
(PREx_x = 0);
Absolute deterministic
PRBS 27-1
pattern
4 Gbps
ps
output jitter(7), peak-to-peak See Figure 7 for the test
circuit.
Over FR4
trace 2-inch
to 20 inches
long
20
(5) Intrinsic deterministic device jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation
(DJ(OUT)– DJ(IN) ), where DJ(OUT) is the total peak-to-peak deterministic jitter measured at the output of the device in pspp. DJ(IN) is the
peak-to-peak deterministic jitter of the pattern generator driving the device.
(6) The SN65LVCP40 built-in passive input equalizer compensates for ISI. For a 20-inch FR4 transmission line with 8-mil trace width, the
LVCP40 typically reduces jitter by 60 ps from the device input to the device output.
(7) Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP40 output. The value is a real measured
value with a Bit error tester as described in Figure 7. The absolute DJ reflects the sum of all deterministic jitter components accumulated
over the link: DJ(absolute) = DJ(Signal generator) + DJ(transmission line) + DJ(intrinsic(LVCP40))
.
PIN ASSIGNMENTS
1
36
35
34
33
PRES_0
VCC
PREL_1
2
3
4
5
6
7
8
VCC
SOB_0N
SOB_0P
GND
LO_0N
−
+
−
+
−
+
−
+
−
+
−
+
LO_0P
GND
32
31
30
29
28
27
LI_1N
LI_1P
LI_0P
LI_0N
VCC
VCC
SOB_1P
SOB_1N
9
+
LO_1P
LO_1N
GND
−
+
−
+
−
+
−
+
−
+
−
10
11
12
26
25
REXT
PRES_1
PREL_0
5
Submit Documentation Feedback
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
Table 1. Signal Descriptions
SIGNAL
PIN(S)
TYPE
SIGNAL TYPE
DESCRIPTION
LINE SIDE HIGH-SPEED I/O
LI_0P
LI_0N
6
7
I (w/ 50-Ω termination PECL/CML
to VBB) compatible
Differential input, port_0 line side
LI_1P
LI_1N
30
31
I (w/ 50-Ω termination PECL/CML
Differential input, port_1 line side
Differential output, port_0 line side
Differential output, port_1 line side
to VBB)
compatible
LO_0P
LO_0N
33
34
O
VML(1)
LO_1P
LO_1N
9
10
O
VML(1)
SWITCH SIDE HIGH-SPEED I/O
SIA_0P
SIA_0N
40
39
I (w/ 50-Ω termination CML/PECL
to VBB) compatible
Differential input, mux_0 switch_A_side
Differential input, mux_0 switch_B_side
Differential input, mux_1 switch_A_side
Differential input, mux_1 switch_B_side
Differential output, mux_0 switch_A_side
Differential output, mux_0 switch_B_side
Differential output, mux_1 switch_A_side
Differential output, mux_1 switch_B_side
SIB_0P
SIB_0N
43
42
I (w/ 50-Ω termination CML/PECL
to VBB) compatible
SIA_1P
SIA_1N
16
15
I (w/ 50-Ω termination CML/PECL
to VBB) compatible
SIB_1P
SIB_1N
19
18
I (w/ 50-Ω termination CML/PECL
to VBB)
compatible
SOA_0P
SOA_0N
46
45
O
VML(1)
SOB_0P
SOB_0N
4
3
O
O
O
VML(1)
VML(1)
VML(1)
SOA_1P
SOA_1N
22
21
SOB_1P
SOB_1N
28
27
CONTROL SIGNALS
Output preemphasis control, line side port_0 and port_1. Has internal
pull-up. See Preemphasis Controls PREL_0, PREL_1, PRES_0 and
PRES for function definition.
PREL_0
PREL_1
12
1
I (w/ 35-kΩ pullup)
I (w/ 35-kΩ pullup)
LVTTL
LVTTL
Output preemphasis control, switch side port_0 and port_1. See
Preemphasis Controls PREL_0, PREL_1, PRES_0 and PRES for
function definition.
PRES_0
PRES_1
36
25
LB0A
LB0B
47
48
Loopback control for mux_0 switch side. See Loopback Controls LB0A,
LB0B, LB1A and LB1B for function definition.n
I (w/ 35-kΩ pullup)
I (w/ 35-kΩ pullup)
I (w/ 35-kΩ pullup)
LVTTL
LVTTL
LVTTL
N/A
LB1A
LB1B
23
24
Loopback control for mux_1 switch side. See Loopback Controls LB0A,
LB0B, LB1A and LB1B for function definition.n
MUX_S0
MUX_S1
37
13
Port A and B multiplex control of mux_0 and mux_1. See Multiplex
Controls MUX_S0 and MUX_S1 for function definition.
No connect. This pin is unused and can be left open or tied to GND with
any resistor.
REXT
26
POWER SUPPLY
2, 8, 14,
20, 29,
35, 38,
44
VCC
PWR
PWR
PWR
Power supply 3.3 V ±5%
Power supply return
5, 11, 17,
32, 41
GND
The ground center pad is the metal contact at the bottom of the 48-pin
package. It must be connected to the GND plane. At least 4 vias are
recommended to minimize inductance and provide a solid ground. See
the package drawing for the via placement.
GND
Center Pad
(1) VML stands for Voltage Mode logic; VML provides a differential output impedance of 100-Ω. VML offers the benefits of CML and
consumes less power.
6
Submit Documentation Feedback
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
FUNCTIONAL BLOCK DIAGRAM
V
BB
R
R
T
SIA_0P
SIA_0N
T
EQ
EQ
LO_0P
+
−
R
R
T
+
−
+
−
LO_0N
SIB_0P
SIB_0N
T
MUX_S0
SOA_0P
+
−
V
BB
+
−
R
R
T
+
−
SOA_0N
LI_0P
LI_0N
T
EQ
SOB_0P
SOB_0N
+
−
+
−
+
−
LB0A
LB0B
PREL_0
PREL_1
Line Side Outputs
V
BB
Preemphasis Control
R
R
T
SIA_1P
SIA_1N
T
EQ
EQ
LO_1P
LO_1N
+
−
R
R
T
+
−
+
−
SIB_1P
SIB_1N
T
MUX_S1
SOA_1P
SOA_1N
+
−
V
BB
R
+
−
T
T
+
−
LI_1P
LI_1N
R
EQ
SOB_1P
SOB_1N
+
−
+
−
+
−
LB1A
LB1B
PRES_0
PRES_1
Switch Side Outputs
Preemphasis Control
Note:
Receiver input internal biasing voltage (allows ac coupling)
:
V
BB
30 K
V
BB
EQ: Input Equalizer (compensates for frequency dependent
transmission line loss of backplanes)
1.6 V
Internal 50−Ohm receiver termination (100−Ohm differential)
Output precompensation for transmission line losses
R :
T
Preemphasis:
7
Submit Documentation Feedback
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
FUNCTIONAL DEFINITIONS
Table 2. Multiplex Controls MUX_S0 and MUX_S1
MUX_Sn(1)
MUX FUNCTION
MUX_n select input B
MUX_n select input A
0
1
(1) n = 0 or 1
Table 3. Loopback Controls LB0A, LB0B, LB1A and
LB1B
LBnx(1)
LOOPBACK FUNCTION
0
1
Enable loopback of SIx input to SOx output
Disable loopback of SIx input to SOx output
(1) n = 0 or 1, x = A or B
Table 4. Multiplexer and Loopback Controls
INPUTS / OUTPUTS
SOA_0
SOB_0
SOA_1
SOB_1
LO_0
LO_1
SIA_0
SIB_0
SIA_1
SIB_1
LI_0
LB0A = 0
x
x
x
MUX_S0 = 1
x
x
LB0B = 0
x
x
MUX_S0 = 0
x
x
x
LB1A = 0
x
x
x
x
x
MUX_S1 = 1
x
LB0A = 1
x
x
LB0B = 1
x
x
x
LB1B =0
x
MUX_S1 = 0
x
x
LI_1
LB1A = 1
LB1B = 1
Table 5. Preemphasis Controls PREL_0, PREL_1, PRES_0, and PRES_1
OUTPUT
PREEMPHASIS
LEVEL IN dB
OUTPUT LEVEL IN mVpp
TYPICAL FR4
TRACE LENGTH
PREx_1(1) PREx_0(1)
DEEMPHASIZED
PREEMPHASIZED
0
0
1
1
0
1
0
1
0 dB
3 dB
6 dB
9 dB
1200
850
600
425
1200
1200
1200
1200
10 inches of FR4 trace
20 inches of FR4 trace
30 inches of FR4 trace
40 inches of FR4 trace
(1) x = L or S
Preemphasis is the primary signal conditioning mechanism. See Figure 1 and Figure 2 for further definition.
Equalization is secondary signal conditioning mechanism. The input stage provides 5-dB of fixed equalization
gain from 375 MHz to 1.875 GHz (optimized for 3.75-Gbps 8B10B coded data).
8
Submit Documentation Feedback
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
PARAMETER MEASUREMENT INFORMATION
1−bit
1 to N bit
0−dB Preemphasis
3−dB Preemphasis
6−dB Preemphasis
V
V
OH
9−dB Preemphasis
V
OCM
OL
V
ODB(PP)
Figure 1. Preemphasis and Output Voltage Waveforms and Definitions
1−bit
1 to N bit
9−dB Preemphasis
V
ODB(PP)
80%
20%
tPRE
Figure 2. t(PRE) Preemphasis Duration Measurement
9
Submit Documentation Feedback
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
80%
80%
V
ODB
20%
20%
t
t
f
r
Figure 3. Driver Output Transition Time
V
ID
= 0 V
IN
t
t
PLHD
PHLD
V
OD
= 0 V
OUT
Figure 4. Propagation Delay Input to Output
CIRCUIT DIAGRAMS
VCC
49.9 W
OUT+
OUT−
V
IN+
OCM
49.9 W
R
T(SE)
1 pF
= 50 W
Gain
Stage
+ EQ
VCC
RBBDC
VBB
R
T(SE)
= 50 W
Figure 6. Common-Mode Output Voltage Test
Circuit
IN−
LineEndTermination
ESD Self−Biasing Network
Figure 5. Equivalent Input Circuit Design
10
Submit Documentation Feedback
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
JITTER TEST CIRCUIT
DC
DC
Block
Pre-amp
Block
Pattern
Generator
SMA
Coax
Coax
Coax
D+
D−
<2” 50 Ω TL
SMA
SMA
RX
+
EQ
M
U
X
OUT
0 dB
DC
Block
DC
Block
20−inch FR4
SMA
Coax
Coupled
Transmission line
<2” 50 Ω TL
400 mV
PP
Differential
SN65LVCP40
Characterization Test Board
Jitter Test
Instrument
NOTE: For the Jitter Test, the preemphasis level of the output is set to 0 dB (PREx_x=0)
Figure 7. AC Test Circuit – Jitter and Output Rise Time Test Circuit
The SN65LVCP40 input equalizer provides 5-dB frequency gain to compensate for frequency loss of a shorter
backplane transmission line. For characterization purposes, a 24-inch FR-4 coupled transmission line is used in
place of the backplane trace. The 24-inch trace provides roughly 5 dB of attenuation between 375 MHz and
1.875 GHz, representing closely the characteristics of a short backplane trace. The loss tangent of the FR4 in the
test board is 0.018 with an effective ε(r) of 3.1.
TYPICAL DEVICE BEHAVIOR
Data Eye Input After 30-inch of FR4
0
0
1
1
0
1
0
1
0dB
3dB
6dB
9dB
Data Eye Output After SN65LVCP40
80 ps/ div
Figure 9. Preemphasis Signal Shape
40 ps/ div
1
NOTE: 30 Inch Input Trace, dR = 4 Gbps; 27-
PRBS
Figure 8. Data Input and Output Pattern
11
Submit Documentation Feedback
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
LVCP40
Output
with 9-dB
Preemp
4-Gbps
Signal
30-inch FR4
30-inch FR4
Generator
30−inch FR4
IN
7−1
PRBS 2
Output
with 0-dB
Preemp
Figure 10. Data Output Pattern
12
Submit Documentation Feedback
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS
DETERMINISTIC OUTPUT JITTER
DETERMINISTIC OUTPUT JITTER
vs
DIFFERENTIAL INPUT AMPLITUDE
DETERMINISTIC OUTPUT JITTER
vs
DIFFERENTIAL INPUT AMPLITUDE
vs
DATA RATE
100
90
80
70
60
50
40
30
20
10
0
70
40
35
30
25
20
15
10
5
7 − 1
2
PRBS pattern,
7−1
A 20 inch FR−4 Trace 8−mil Wide is
Driving the LVCO40.
The DJ is Measured on the Output of the
LVCP40
PRBS 2
+ 100 CIDs
Jitter @ 2.5 Gbps
60
50
40
30
20
10
0
DJ @ T = 85°C
Jitter @ 3.75 Gbps
DJ @ T = 25°C
7−1
2
PRBS
K 28.5
Jitter @ 1.25 Gbps
DJ @ T = 0°C
CJTPAT
Jitter @ 3.125 Gbps
0
0
200 400 600 800 1000 1200 140016001800
0
200 400 600 800 1000 1200 140016001800
1
1.5
2
2.5
3
3.5
4
V
− Differential Input Amplitude − mV
V
− Differential Input Swing − mV
ID
ID
DR − Data Rate − Gbps
Figure 11.
Figure 12.
Figure 13.
DETERMINISTIC OUTPUT JITTER
RANDOM OUTPUT JITTER
RANDOM OUTPUT JITTER
vs
DIFFERENTIAL INPUT SWING
vs
vs
INPUT TRACE LENGTH
DATA RATE
1.4
1.2
1
1.4
1.2
1
140
120
100
80
RJ @ 2.5 Gbps
T
= 85°C − K28.7 Pattern
A
DJ @ 3.75Gpbs
[ps] 600mV
DJ @ 3.75Gpbs
[ps] 200mV
0.8
0.6
0.4
0.8
0.6
T
A
= 0°C − 1010 Pattern
DJ @ 3.125Gbps
[ps] 200mV
RJ @ 3.125 Gbps
RJ @ 3.75 Gbps
60
T
A
= 85°C − 1010 Pattern
T
A
= 25°C − 1010 Pattern
40
20
0
0.4
DJ @ 3.125Gbps
[ps] 600mV
0.2
0
0.2
0
0
10
20
30
40
50
60
70
0
200 400 600 800 1000 1200 1400 1600
2.5 2.7 2.9
3.1 3.3 3.5 3.7 3.9 4
Input Trace Length − inch
V
− Differential Input Swing − mV
DR − Data Rate − Gbps
ID
Figure 14.
Figure 15.
Figure 16.
RANDOM OUTPUT JITTER
vs
INPUT TRACE LENGTH
TOTAL OUTPUT JITTER
vs
POWER SUPPLY NOISE
DJ/RJ OUTPUT JITTER
vs
COMMON-MODE INPUT VOLTAGE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
60
40
35
RJ @ 3.125Gbps
Vin=200mVpp;
[ps−rms]
4
Jitter @ 800 mV
50
Jitter @ 400 mV
3.5
3
30
40
25
20
2.5
30
2
DJ @ 3.75 Gbps
Jitter @ 100 mV
15
10
1.5
1.0
20
Jitter Without
RJ @ 3.75Gpbs
Vin=200mVpp;
[ps_rms]
V
Noise
CC
RJ @ 3.75Gbps
Vin=800mVpp;
[ps−rms]
10
5
0
0.5
RJ @ 3.75 Gbps
0
0
1000
1200 1400 1600 1800 2000 2200 2400
0.1
1
10
100
0
10
20
30
40
50
V
− Common Mode Input Voltage − mV
ICM
Input Trace Length − inch
Noise Frequency - MHz
Figure 17.
Figure 18.
Figure 19.
13
Submit Documentation Feedback
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS (continued)
TOTAL OUTPUT JITTER
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
DIFFERENTIAL OUTPUT SWING
vs
INPUT SIGNAL FREQUENCY
182
181
180
179
178
177
176
175
174
173
1.4
1.2
1
38
37
TJ @ 200 mV Input Swing
0−dB Preemphasis
VODB @ 0 dC
36
35
34
33
0.8
0.6
0.4
0.2
0
VODB @ 25 dC
9−dB Preemphasis
32
31
30
VODB @ 85 dC
TJ @ 600 mV Input Swing
0
10 20 30 40 50 60 70 80 85
0
500 1 k 1.5 k 2 k 2.5 k 3 k 3.5 k 4 k
0
20
40
60
80
100
T
A
− Free −Air Temperature − 5C
Input Signal Frequency − MHz
T
A
− Free −Air Temperature − 5C
Figure 20.
Figure 21.
Figure 22.
RECEIVER INPUT RETURN LOSS
vs
FREQUENCY
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
−50
10
100
1000
10000
f − Frequency − MHz
Figure 23.
14
Submit Documentation Feedback
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
APPLICATION INFORMATION
BANDWIDTH REQUIREMENTS
Error free transmission of data over a transmission line has specific bandwidth demands. It is helpful to analyze
the frequency spectrum of the transmit data first. For an 8B10B coded data stream at 3.75 Gbps of random data,
the highest bit transition density occurs with a 1010 pattern (1.875 GHz). The least transition density in 8B10B
allows for five consecutive ones or zeros. Hence, the lowest frequency of interest is 1.875 GHz/5 = 375 MHz.
Real data signals consist of higher frequency components than sine waves due to the fast rise time. The faster
the rise time, the more bandwidth becomes required. For 80-ps rise time, the highest important frequency
component is at least 0.6/(π × 80 ps) = 2.4 GHz. Figure 24shows the Fourier transformation of the 375-MHz and
1.875-GHz trapezoidal signal.
0
20 dB/dec
1875 MHz With
−5
−10
−15
−20
−25
80 ps Rise Time
20 dB/dec
375 MHz With
80 ps Rise Time
40 dB/dec
80%
40 dB/dec
20%
t
r
t
= 1/f
Period
100
1000
f − Frequency − MHz
10000
1/(pi x 100/60 t ) = 2.4 GHz
r
Figure 24. Approximate Frequency Spectrum of the Transmit Output Signal With 80 ps Rise Time
The spectrum analysis of the data signal suggests building a backplane with little frequency attenuation up to
2 GHz. Practically, this is achievable only with expensive, specialized PCB material. To support material like
FR4, a compensation technique is necessary to compensate for backplane imperfections.
EXPLANATION OF EQUALIZATION
Backplane designs differ widely in size, layer stack-up, and connector placement. In addition, the performance is
impacted by trace architecture (trace width, coupling method) and isolation from adjacent signals. Common to
most commercial backplanes is the use of FR4 as board material and its related high-frequency signal
attenuation. Within a backplane, the shortest to longest trace lengths differ substantially – often ranging from
8 inches up to 40 inches. Increased loss is associated with longer signal traces. In addition, the backplane
connector often contributes a good amount of signal attenuation. As a result, the frequency signal attenuation for
a 300-MHz signal might range from 1 dB to 4 dB while the corresponding attenuation for a 2-GHz signal might
span 6 dB to 24 dB. This frequency dependent loss causes distortion jitter on the transmitted signal. Each
'LVCP40 receiver input incorporates an equalizer and compensates for such frequency loss. The SN65LVCP40
equalizer provides 5 dB of frequency gain between 375 MHz and 1.875 GHz, compensating roughly for 20
inches of FR4 material with 8-mil trace width. Distortion jitter improvement is substantial, often providing more
than 30-ps jitter reduction. The 5-dB compensation is sufficient for most short backplane traces. For longer trace
lengths, it is recommended to enable transmit preemphasis in addition.
SETTING THE PREEMPHASIS LEVEL
The receive equalization compensates for ISI. This reduces jitter and opens the data eye. In order to find the
best preemphasis setting for each link, calibration of every link is recommended. Assuming each link consists of
a transmitter (with adjustable pre-emphasis such as 'LVCP40) and the 'LVCP40 receiver, the following steps are
necessary:
1. Set the transmitter and receiver to 0-dB preemphasis; record the data eye on the LVCP40 receiver output.
2. Increase the transmitter preemphasis until the data eye on the LVCP40 receiver output looks the cleanest.
15
Submit Documentation Feedback
SN65LVCP40
www.ti.com
SLLS623D–SEPTEMBER 2004–REVISED FEBRUARY 2006
APPLICATION INFORMATION (continued)
RECEIVER FAIL-SAFE RESPONSE
If the input is removed from a powered receiver of the 'LVCP40, there are no internal fail-safe provisions to
prevent noise from switching the output. Figure 25 shows one remedy using 1.6 kΩ resistors to pull up on one
input to the SN65LVCP40 supply, and pull down the other input to its ground. Assuming the differential noise in
the system is less than 25 mV, this maintains a valid output with no input. If the noise is greater than 25 mV,
lower fail-safe resistance is required.
VCC
1.6 kW
100
1.6 kW
Figure 25. Fail-Safe Bias Resistors
If the driver is another SN65LVCP40, attenuation from the driver to receiver must be less than 250 mV or 6 dB.
This value comes from the minimum output of 500 mV into 100 Ω less the minimum recommended input voltage
of 100 mV, 25 mV for noise, and 125 mV for the maximum fail-safe bias.
The fail-safe bias also introduces additional eye-pattern jitter depending upon the input voltage transition time,
but is designed to be less than 10% of the unit interval.
The only other options are to have a hardware interlock that removed power to the receiver, or switched in a
fail-safe bias, or rely on error detection to ignore random inputs.
16
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2007
PACKAGING INFORMATION
Orderable Device
SN65LVCP40RGZ
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RGZ
48
48
48
48
48
48
52 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
SN65LVCP40RGZG4
SN65LVCP40RGZR
SN65LVCP40RGZRG4
SN65LVCP40RGZT
SN65LVCP40RGZTG4
QFN
QFN
QFN
QFN
QFN
RGZ
RGZ
RGZ
RGZ
RGZ
52 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
16
SN65LVCP40RGZR
SN65LVCP40RGZT
RGZ
RGZ
48
48
TAI
TAI
7.3
7.3
7.3
7.3
1.5
1.5
12
12
16
16
Q2
Q2
330
16
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN65LVCP40RGZR
SN65LVCP40RGZT
RGZ
RGZ
48
48
TAI
TAI
407.0
342.9
336.6
336.6
97.0
28.58
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties
may be subject to additional restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明