SN65LVDS048A [TI]
LVDS QUAD DIFFERENTIAL LINE RECEIVER; LVDS四路差动线路接收器
| 型号： | SN65LVDS048A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LVDS QUAD DIFFERENTIAL LINE RECEIVER |
| 文件： | 总15页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B– SEPTEMBER 2000 – REVISED SEPTEMBER 2002
SN65LVDS048AD (Marked as LVDS048A)
SN65LVDS048APW (Marked as DL048A)
(TOP VIEW)
D
D
>400 Mbps (200 MHz) Signaling Rates
Flow-Through Pinout Simplifies PCB
Layout
R
R
R
R
R
R
R
R
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1–
IN1+
IN2+
IN2–
IN3–
IN3+
IN4+
IN4–
EN
R
D
D
D
D
D
D
D
D
D
50 ps Channel-to-Channel Skew (Typ)
200 ps Differential Skew (Typ)
OUT1
R
V
OUT2
Propagation Delay Times 2.7 ns (Typ)
3.3-V Power Supply Design
CC
GND
R
High Impedance LVDS Inputs on Power
Down
OUT3
R
OUT4
EN
Low-Power Dissipation (40 mW at 3.3 V
Static)
Accepts Small Swing (350 mV) Differential
Signal Levels
functional diagram
EN
EN
Supports Open, Short, and Terminated
Input Fail-Safe
Industrial Operating Temperature Range
(–40°C to 85°C)
R
R
IN1+
R1
R
OUT1
IN1–
D
D
D
Conforms to TIA/EIA-644 LVDS Standard
Available in SOIC and TSSOP Packages
R
R
IN2+
IN2–
R2
R3
R4
R
R
Pin-Compatible With DS90LV048A From
National
OUT2
OUT3
R
R
IN3+
description
IN3–
The SN65LVDS048A is a quad differential line receiver
R
R
IN4+
IN4–
that implements the electrical characteristics of
low-voltage differential signaling (LVDS). This signaling
technique lowers the output voltage levels of 5-V
differential standard levels (such as EIA/TIA-422B) to
reduce the power, increase the switching speeds, and
allow operation with a 3.3-V supply rail. Any of the quad
R
OUT4
differential receivers will provide a valid logical output state with a ±100-mV differential input voltage within the
input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential
difference between two LVDS nodes.
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to the environment, and other system characteristics.
The SN65LVDS048A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B– SEPTEMBER 2000 – REVISED SEPTEMBER 2002
TRUTH TABLE
DIFFERENTIAL INPUT ENABLES
– R EN
OUTPUT
R
EN
R
OUT
IN+
IN–
V
ID
≥ 100 mV
H
V
≤ –100 mV
L
H
Z
H
L or OPEN
ID
Open/short or terminated
X
All other conditions
H = high level, L = low level, X = irrelevant, Z = high impedance (off)
equivalent input and output schematic diagrams
V
CC
V
CC
V
CC
50 Ω
5 Ω
300 kΩ
300 kΩ
EN,EN
Output
7 V
7 V
Input
Input
300 kΩ
7 V
7 V
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range (V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
CC)
Input voltage range, V (R , R ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
I
IN+ IN–
Enable input voltage (EN, EN ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V
+0.3 V)
+0.3 V)
CC
CC
Output voltage, V (R
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V
O
OUT
Bus-pin (R , R ) Electrostatic discharge (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 10 kV
IN+ IN–
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
‡
T
≤ 25°C
OPERATING FACTOR
T = 85°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
D
950 mW
7.6 mW/°C
6.2 mW/°C
494 mW
PW
774 mW
402 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B– SEPTEMBER 2000 – REVISED SEPTEMBER 2002
recommended operating conditions
MIN
3
NOM
MAX
3.6
3
UNIT
V
Supply voltage, V
CC
3.3
Receiver input voltage
GND
V
|V
|
|V
|
ID
ID
Common–mode input voltage, V
IC
2.4 *
2
V
2
V
CC
– 0.8
Operating free-air temperature, T
–40
25
85
°C
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Note 3)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
Differential input high threshold voltage
Differential input low threshold voltage
Common mode voltage range
100
IT+
V
= 1.2 V, 0.05 V, 2.35 V
CM
mV
(see Note 4)
–100
IT–
V
V
V
V
= 200 mV pk to pk (see Note 5)
= 2.8 V
0.1
2.3
20
20
20
V
µA
µA
µA
V
(CMR)
ID
–20
–20
–20
2.7
2.7
2.7
±1
±1
IN
V
CC
= 3.6 V or 0 V
= 0 V
I
IN
Input current
IN
= 3.6 V
V
CC
= 0 V
±1
IN
I
I
I
I
= –0.4 mA, V = 200 mV
3.2
3.2
3.2
0.05
–65
OH
OH
OH
OL
ID
= –0.4 mA, input terminated
= –0.4 mA, input shorted
V
V
V
Output high voltage
OH
V
Output low voltage
Output short circuit current
Output 3-state current
Input high voltage
= 2 mA, V = –200 mV
ID
0.25
–100
1
V
OL
I
I
Enabled, V
OUT
= 0 V (see Note 6)
= 0 V or V
mA
µA
V
OS
Disabled, V
–1
2.0
O(Z)
OUT
CC
V
V
CC
0.8
IH
IL
V
Input low voltage
GND
V
V
= 0 V or V
,
IN
CC
I
I
Input current (enables)
–10
10
µA
Other input = V
or GND
CC
V
Input clamp voltage
I
= –18 mA
–1.5
–0.8
8
V
IK
CL
I
I
No load supply current, receivers enabled
No load supply current, receivers disabled
EN = V , Inputs open
CC
15
mA
mA
CC
EN = GND, Inputs open
0.6
1.5
CC(Z)
†
All typical values are at 25°C and with a 3.3-V supply.
NOTES: 3. Current into device pin is defined as positive. Current out of the device is defined as negative. All voltages are referenced to ground,
unless otherwise specified.
4.
V
isalwayshigherthanR
andR
voltage,R
andR
haveavoltagerangeof–0.2VtoV –V /2.Tobecompliantwith
CC ID
CC
IN+
IN–
IN–
IN+
ac specifications the common voltage range is 0.1 V to 2.3 V.
5. The VCMR range is reduced for larger V , Example: If V = 400 mV, the VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs
ID ID
shorted is not supported over the common-mode range of 0 V to 2.4 V, but is supported only with inputs shorted and no external
common-mode voltage applied. A V up to V –0 V may be applied to the R and R inputs with the common-mode voltage
ID CC IN+ IN–
set to V /2. Propagation delay and differential pulse skew decrease when V is increased from 200 mV to 400 mV. Skew
CC ID
specifications apply for 200 mV < V < 800 mV over the common-mode range.
ID
6. Output short circuit current (I ) is specified as magnitude only, minus sign indicates direction only. Only one output should be
OS
shorted at a time. Do not exceed maximum junction temperature specification.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B– SEPTEMBER 2000 – REVISED SEPTEMBER 2002
switching characteristics over recommended operating conditions (unless otherwise noted) (see
Notes 7)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
3.7
3.7
450
500
1
UNIT
ns
t
t
t
t
t
t
t
t
t
Differential propagation delay, high-to-low
Differential propagation delay, low-to-high
1.9
1.9
2.7
2.9
200
50
PHL
PLH
SK(p)
SK(o)
SK(pp)
SK(lim)
r
ns
Differential pulse skew (t
t
) (see Note 8)
ps
PHLD – PLHD
C
V
= 15 pF
L
Differential channel-to-channel skew; same device (see Note 8)
Differential part-to-part skew (see Note 10)
Differential part-to-part skew (see Note11)
Rise time
ps
= 200 mV
ID
ns
(see Figure 1 and 2 )
1.5
1
ns
0.5
0.5
8
ns
Fall time
1
ns
f
Disable time high to Z
9
ns
PHZ
R
C
= 2 K Ω
= 15 pF
L
L
t
t
t
Disable time low to Z
Enable time Z to high
Enable time Z to low
6
8
7
8
10
8
ns
ns
ns
PLZ
PZH
PZL
(see Figure 3 and 4 )
f
Maximum operating frequency (see Note 12)
All channels switching
200
250
MHz
(MAX)
†
All typical values are at 25°C and with a 3.3-V supply.
NOTES: 7. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z = 50 Ω, tr and tf (0% – 100%) ≤ 3 ns for R
.
IN
O
8.
t
|t
– t
| is the magnitude difference in differential propagation delay time between the positive going edge and
SK(p) PLH
PHL
the negative going edge of the same channel.
9.
10.
t
is the differential channel-to-channel skew of any event on the same device.
SK(o)
t
is the differential part-to-part skew, and is defined as the difference between the minimum and the maximum specified
SK(pp)
differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the
operating temperature range.
11.
12.
t
part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to
sk(lim)
devices over recommended operating temperature and voltage ranges, and across process distribution. t
– Max| differential propagation delay.
is defined as |Min
sk(lim)
f
V
generator input conditions: t = t < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%,
(MAX)
r
f
> 250 mV, all channels switching
OD
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B– SEPTEMBER 2000 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
R
R
IN+
R
Generator
R
OUT
IN–
C
L
50 Ω
50 Ω
Receiver Enabled
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
R
R
1.3 V
1.1 V
IN–
OV Differential
V
= 200 mV
1.2 V
ID
IN+
t
t
PLH
PHL
80%
V
V
OH
80%
R
OUT
1.5 V
20%
1.5 V
20%
OL
t
t
f
r
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B– SEPTEMBER 2000 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
V
CC
S
1
R
L
R
R
IN+
Device
Under
Test
R
OUT
IN–
Generator
EN
EN
C
L
50 Ω
1/4 65LVDS048A
C
S
S
Includes Load and Test Jig Capacitance.
L
1
1
= V
for t
and t
PLZ
and t
Measurements.
Measurements.
CC
PZL
PZH
= GND for t
PHZ
Figure 3. Receiver 3-State Delay Test Circuit
1.5 V
1.5 V
3 V
EN When EN = GND or Open
0 V
3 V
EN When EN = V
CC
0 V
t
t
PZL
PLZ
V
V
CC
50%
50%
Output When
0.5 V
0.5 V
OL
V
ID
= –100 mV
t
t
PZH
PHZ
V
OH
Output When
V
ID
= 100 mV
GND
Figure 4. Receiver 3-State Delay Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B– SEPTEMBER 2000 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
OUTPUT HIGH VOLTAGE
vs
POWER SUPPLY VOLTAGE
OUTPUT LOW VOLTAGE
vs
POWER SUPPLY VOLTAGE
3.6
3.4
57
56
T
V
= 25°C
T
V
= 25°C
A
A
= 200 mV
= 200 mV
ID
ID
55
54
3.2
3
53
52
2.8
3
3.3
3.6
3
3.3
3.6
V
CC
– Power Supply Voltage – V
V
CC
– Power Supply Voltage – V
Figure 5
Figure 6
OUTPUT SHORT CIRCUIT CURRENT
DIFFERENTIAL TRANSITION VOLTAGE
vs
vs
POWER SUPPLY VOLTAGE
POWER SUPPLY VOLTAGE
–80
–76
–72
50
40
T
V
= 25°C
= 0 V
T
A
= 25°C
A
O
30
20
–68
–64
10
0
–60
–56
3
3.3
3.6
3
3.3
3.6
V
CC
– Power Supply Voltage – V
V
CC
– Power Supply Voltage – V
Figure 7
Figure 8
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B– SEPTEMBER 2000 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
DIFFERENTIAL PROPAGATION DELAY
vs
DIFFERENTIAL PROPAGATION DELAY
vs
DIFFERENTIAL INPUT VOLTAGE
COMMON-MODE VOLTAGE
4
3
4
3
2
1
t
t
PLH
PLH
t
PHL
t
PHL
2
1
0
T
= 25°C
T
A
= 25°C
A
f = 20 MHz
f = 20 MHz
= 1.2 V
V
= 1.2 V
V
CM
C = 15 pF
CM
C = 15 pF
I
I
V
= 3.3 V
V
= 3.3 V
CC
CC
0
–0.5
0
500
1000
1500
2000
2500
3000
0
0.5
1
1.5
2
2.5
Differential Input Voltage – mV
Common-Mode Voltage – V
Figure 9
Figure 10
DATA TRANSFER RATE
vs
FREE-AIR TEMPERATURE
800
750
700
650
600
550
500
450
400
15
2
–1 prbs NRZ
= 3.3 V
V
V
V
CC
= 0.4 V
= 1.2 V
= 5.5 pF
ID
IC
C
L
40% Open Eye
4 Receivers Switching
Input Jitter < 45 ps
–40
–20
0
20
40
60
80
T
A
– Free-Air Temperature – °C
Figure 11
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B– SEPTEMBER 2000 – REVISED SEPTEMBER 2002
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100
mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it
handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
will pull each line of the signal pair to near V
through 300-kΩ resistors as shown in Figure 10. The fail-safe
CC
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
V
CC
300 kΩ
300 kΩ
A
Rt = 100 Ω (Typ)
Y
B
V
IT
≈ 2.3 V
Figure 12. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B– SEPTEMBER 2000 – REVISED SEPTEMBER 2002
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–ā8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS048A
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS451B– SEPTEMBER 2000 – REVISED SEPTEMBER 2002
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–ā8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2005
PACKAGING INFORMATION
Orderable Device
SN65LVDS048AD
SN65LVDS048ADR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN65LVDS048APW
SN65LVDS048APWR
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
16
16
90
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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