SN65LVDS104PW [TI]
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS; 4端口LVDS和4端口TTL - TO- LVDS转发器
| 型号： | SN65LVDS104PW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS |
| 文件： | 总20页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
Receiver and Drivers Meet or Exceed the
Requirements of ANSI EIA/TIA-644
Standard
SN65LVDS104
D OR PW PACKAGE
(TOP VIEW)
SN65LVDS105
D OR PW PACKAGE
(TOP VIEW)
– SN65LVDS105 Receives Low-Voltage TTL
(LVTTL) Levels
– SN65LVDS104 Receives Differential Input
Levels, ±100 mV
EN1
EN2
EN3
1Y
1Z
2Y
2Z
3Y
3Z
EN1
EN2
EN3
1Y
1Z
2Y
2Z
3Y
3Z
1
2
3
4
5
6
7
8
16
15
14
13
12
11
1
2
3
4
5
6
7
8
16
15
14
13
12
11
V
V
CC
CC
Designed for Signaling Rates up to
630 Mbps
GND
A
GND
A
Operates From a Single 3.3-V Supply
B
10 4Y
4Z
NC
EN4
10 4Y
4Z
EN4
9
9
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100-Ω Load
Propagation Delay Time
logic diagram (positive logic)
– SN65LVDS105 . . . 2.2 ns (Typ)
– SN65LVDS104 . . . 3.1 ns (Typ)
’LVDS104
1Y
Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Networks
1Z
EN1
EN2
2Y
2Z
EN3
Driver Outputs Are High Impedance When
3Y
3Z
Disabled or With V
<1.5 V
CC
A
B
Bus-Pin ESD Protection Exceeds 16 kV
SOIC and TSSOP Packaging
4Y
4Z
EN4
description
’LVDS105
The SN65LVDS104 and SN65LVDS105 are a
differential line receiver and a LVTTL input
(respectively) connected to four differential line
drivers that implement the electrical characteris-
tics of low-voltage differential signaling (LVDS).
LVDS, as specified in EIA/TIA-644 is a data
signaling technique that offers low-power, low-
noise coupling, and switching speeds to transmit
data at speeds up to 655 Mbps at relatively long
distances. (Note: The ultimate rate and distance
of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to
the environment, and other system characteris-
tics.)
1Y
1Z
EN1
EN2
2Y
2Z
EN3
A
3Y
3Z
4Y
4Z
EN4
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse
skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input.
This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.
The SN65LVDS104 and SN65LVDS105 are characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
description (continued)
The SN65LVDS104 and SN65LVDS105 are members of a family of LVDS repeaters. A brief overview of the
family is provided in the table below.
Selection Guide to LVDS Repeaters
DEVICE
NO. INPUTS
2 LVDS
NO. OUTPUTS
2 LVDS
PACKAGE
16-pin D
COMMENT
Dual multiplexed LVDS repeater
4-Port LVDS repeater
SN65LVDS22
SN65LVDS104
SN65LVDS105
SN65LVDS108
SN65LVDS109
SN65LVDS116
SN65LVDS117
1 LVDS
4 LVDS
16-pin D
1 LVTTL
1 LVDS
4 LVDS
16-pin D
4-Port TTL-to-LVDS repeater
8-Port LVDS repeater
8 LVDS
38-pin DBT
38-pin DBT
64-pin DGG
64-pin DGG
2 LVDS
8 LVDS
Dual 4-port LVDS repeater
16-Port LVDS repeater
1 LVDS
16 LVDS
16 LVDS
2 LVDS
Dual 8-port LVDS repeater
Function Tables
SN65LVDS104
SN65LVDS105
INPUT
= V - V
OUTPUT
INPUT
#EN
OUTPUT
V
#EN
X
#Y
Z
#Z
Z
A
L
#Y
#Z
H
L
ID
A
B
X
H
H
H
L
L
H
L
X
L
Z
Z
H
V
≥ 100 mV
H
H
?
L
Open
X
H
Z
ID
–100 mV < V < 100 mV
H
?
Z
Z
ID
≤ –100 mV
V
ID
H
L
H
X
X
Z
H = high level, L = low level, Z = high impedance, ? = indeterminate, X = don’t care
equivalent input and output schematic diagrams
V
CC
V
CC
V
CC
300 kΩ
300 kΩ
EN and
A (’LVDS105)
Input
50 Ω
10 kΩ
5 Ω
Y or Z
Output
A
Input
B
Input
7 V
7 V
300 kΩ
7 V
7 V
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to 4 V
CC
Voltage range,
Enable inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to 6 V
A, B, Y or Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to 4 V
Electrostatic discharge (see Note 2); Y, Z, and GND . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:16 kV, B: 600 V
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:7 kV, B: 500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7
DISSIPATION RATING TABLE
T
≤ 25°C
OPERATING FACTOR‡
T = 85°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
D
950 mW
7.6 mW/°C
6.2 mW/°C
494 mW
PW
774 mW
402 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k)
and with no air flow.
recommended operating conditions
MIN NOM
MAX
UNIT
Supply voltage, V
CC
3
2
3.3
3.6
V
V
V
V
High-level input voltage, V
IH
Low-level input voltage, V
IL
Magnitude of differential input voltage, V
0.8
3.6
0.1
ID
ID
V
V
V
ID
2
2.4 –
Common-mode input voltage, V
IC
2
V
CC
–0.8
V
Operating free-air temperature, T
–40
85
°C
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
SN65LVDS104 electrical characteristics over recommended operating conditions (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
Differential output voltage magnitude
100
ITH+
See Figure 1 and Table 1
mV
–100
ITH–
V
247
340
454
50
OD
R = 100Ω,
L
V
= ± 100 mV,
mV
Change in differential output voltage magnitude between
logic states
ID
∆ V
–50
OD
See Figure 1 and Figure 2
V
Steady-state common-mode output voltage
1.125
–50
1.375
50
V
OC(SS)
Change in steady-state common-mode output voltage
between logic states
∆V
mV
See Figure 3
OC(SS)
OC(PP)
V
Peak-to-peak common-mode output voltage
25
23
3
150
35
mV
mA
mA
Enabled, R = 100Ω
L
I
Supply current
CC
Disabled
8
V = 0 V
–2
–11
–3
–20
I
I
I
Input current (A or B inputs)
µA
V = 2.4 V
I
–1.2
I
I
I
Power-off Input current
V
V
V
V
V
V
V
= 1.5 V,
V = 2.4 V
20
20
µA
µA
µA
mA
mA
µA
µA
pF
I(OFF)
CC
I
High-level input current (enables)
Low-level input current (enables)
= 2 V
IH
IH
= 0.8 V
10
IL
IL
or V
OZ
= 0 V
= 0 V
±10
±10
±1
OY
OD
I
Short-circuit output current
OS
I
I
High-impedance output current
Power-off output current
= 0 V or 2.4 V
OZ
O
= 1.5 V,
V = 2.4 V
O
±1
O(OFF)
CC
C
Input capacitance (A or B inputs)
V = 0.4 sin (4E6πt) + 0.5 V
I
3
IN
V = 0.4 sin (4E6πt) + 0.5 V,
Disabled
I
C
Output capacitance (Y or Z outputs)
9.4
pF
O
†
All typical values are at 25°C and with a 3.3 V supply.
SN65LVDS104 switching characteristics over recommended operating conditions (unless
otherwise noted)
†
PARAMETER
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
TEST CONDITIONS
MIN TYP
MAX
4.2
4.2
1.2
1.2
500
100
1.5
15
UNIT
ns
t
t
t
t
t
t
t
t
t
t
t
2.4
2.2
0.3
0.3
3.2
3.1
0.8
0.8
150
20
PLH
PHL
r
ns
R
C
= 100Ω,
= 10 pF,
L
L
ns
Differential output signal fall time
ns
f
See Figure 4
Pulse skew (|t
– t
|)
ps
sk(p)
sk(o)
sk(pp)
PZH
PZL
PHZ
PLZ
PHL PLH
‡
Channel-to-channel output skew
ps
§
Part-to-part skew
ns
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
7.2
8.4
3.6
6
ns
15
ns
See Figure 5
15
ns
15
ns
†
All typical values are at 25°C and with a 3.3 V supply.
‡
§
t
t
is the magnitude of the time difference between the t
PLH
sk(pp)
or t
of all drivers of a single device with all of their inputs connected together.
sk(o)
PHL
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
SN65LVDS105 electrical characteristics over recommended operating conditions (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
Differential output voltage magnitude
247
340
454
OD
R = 100Ω,
L
V
= ± 100 mV,
mV
Change in differential output voltage magnitude between
logic states
ID
∆ V
–50
50
1.375
50
OD
See Figure 6 and Figure 7
V
Steady-state common-mode output voltage
1.125
–50
V
OC(SS)
Change in steady-state common-mode output voltage be-
tween logic states
∆V
mV
See Figure 8
OC(SS)
OC(PP)
V
Peak-to-peak common-mode output voltage
25
23
150
35
mV
mA
mA
µA
µA
mA
mA
µA
µA
pF
Enabled, R = 100Ω
L
I
Supply current
CC
Disabled
0.7
6.4
20
I
I
High-level input current
Low-level input current
V
V
V
V
V
V
= 2 V
IH
IH
= 0.8 V
10
IL
IL
or V
OZ
= 0 V
= 0 V
±10
±10
±1
OY
OD
I
Short-circuit output current
OS
I
I
High-impedance output current
Power-off output current
Input capacitance
= 0 V or 2.4 V
OZ
O
= 1.5 V,
V = 2.4 V
O
0.3
5
±1
O(OFF)
CC
C
V = 0.4 sin (4E6πt) + 0.5 V
I
IN
V = 0.4 sin (4E6πt) + 0.5 V,
Disabled
I
C
Output capacitance (Y or Z outputs)
9.4
pF
O
†
All typical values are at 25°C and with a 3.3 V supply.
SN65LVDS105 switching characteristics over recommended operating conditions (unless
otherwise noted)
†
PARAMETER
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
TEST CONDITIONS
MIN TYP
MAX
3
UNIT
ns
t
t
t
t
t
t
t
t
t
t
t
1.7
1.4
0.3
0.3
2.2
2.3
0.8
0.8
150
20
PLH
PHL
r
3.5
1.2
1.2
500
100
1.5
15
ns
R
C
= 100Ω,
= 10 pF,
L
L
ns
Differential output signal fall time
ns
f
See Figure 9
Pulse skew (|t
– t
|)
ps
sk(p)
sk(o)
sk(pp)
PZH
PZL
PHZ
PLZ
PHL PLH
‡
Channel-to-channel output skew
ps
§
Part-to-part skew
ns
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
7.2
8.4
3.6
6
ns
15
ns
See Figure 10
15
ns
15
ns
†
All typical values are at 25°C and with a 3.3 V supply.
‡
§
t
t
is the magnitude of the time difference between the t
PLH
sk(pp)
or t
of all drivers of a single device with all of their inputs connected together.
sk(o)
PHL
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
I
I
I
OY
A
Y
Z
V
V
OD
ID
V
V
OY
OZ
I
I
OZ
IB
V
OY
2
V
IA
B
V
OC
V
V
IB
OZ
Figure 1. ’LVDS104 Voltage and Current Definitions
Table 1. SN65LVDS104 Minimum and Maximum Input Threshold Test Voltages
RESULTING
DIFFERENTIAL
INPUT VOLTAGE
RESULTING
COMMON-MODE
INPUT VOLTAGE
APPLIED
VOLTAGES
V
IA
V
IB
V
ID
V
IC
1.25 V
1.15 V
2.4 V
2.3 V
0.1 V
0 V
1.15 V
1.25 V
2.3 V
2.4 V
0 V
100 mV
–100 mV
100 mV
–100 mV
100 mV
–100 mV
600 mV
–600 mV
600 mV
–600 mV
600 mV
–600 mV
1.2 V
1.2 V
2.35 V
2.35 V
0.05 V
0.05 V
1.2 V
1.2 V
2.1 V
2.1 V
0.3 V
0.3 V
0.1 V
0.9 V
1.5 V
1.8 V
2.4 V
0 V
1.5 V
0.9 V
2.4 V
1.8 V
0.6 V
0 V
0.6 V
3.75 kΩ
Y
Z
V
OD
Input
100 Ω
3.75 kΩ
0 V ≤ V
TEST
≤ 2.4 V
±
Figure 2. ’LVDS104 VOD Test Circuit
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
49.9 Ω ± 1% (2 Places)
V
I
I
1.4 V
1 V
Y
Z
V
Input
V
OC(PP)
V
V
OC
OC(SS)
C
= 10 pF
L
(2 Places)
V
O
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulsewidth = 500 ± 10 ns . C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of V
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
L
OC(PP)
Figure 3. ’LVDS104 Test Circuit and Definitions for the Driver Common-Mode Output Voltage
1.4 V
1.2 V
V
IB
Input
1 V
V
t
IA
PLH
t
PHL
Y
Z
A
B
Input
100%
80%
V
OD
100 Ω ± 1 %
Output
V
OD(H)
C
= 10 pF
L
0 V
(2 Places)
V
OD(L)
20%
0%
t
t
r
f
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
r
f
pulsewidth = 10 ± 0.2 ns . C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
Figure 4. ’LVDS104 Test Circuit, Timing, and Voltage Definitions for the Differential output Signal
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
49.9 Ω ± 1% (2 Places)
Y
Z
1 V or 1.4 V
1.2 V
EN
1.2 V
C
= 10 pF
V
OY
V
OZ
L
(2 Places)
(see Note B)
3 V
1.5 V
EN
0 V
t
t
t
PZH
PHZ
PLZ
V
OY
or
1.4 V
1.25 V
V
OZ
1.2 V
t
PZL
1.2 V
1.15 V
1 V
V
OZ
or
V
OY
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulsewidth = 500 ± 10 ns . C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
Figure 5. ’LVDS104 Enable and Disable Time Circuit and Definitions
I
OY
Y
Z
I
I
A
V
OD
V
V
OY
OZ
I
OZ
V
OY
2
V
OC
V
IA
V
OZ
Figure 6. ’LVDS105 Voltage and Current Definitions
3.75 kΩ
Y
V
OD
Input
100 Ω
3.75 kΩ
Z
0 V ≤ V
≤ 2.4 V
±
TEST
Figure 7. ’LVDS105 VOD Test Circuit
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
49.9 Ω ± 1% (2 Places)
3 V
0 V
Y
Z
A
O
Input
V
OC(PP)
V
V
OC
OC(SS)
C
= 10 pF
L
(2 Places)
V
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulsewidth = 500 ± 10 ns . C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of V
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
L
OC(PP)
Figure 8. ’LVDS105 Test Circuit and Definitions for the Driver Common-Mode Output Voltage
3 V
Input
1.5 V
0 V
V
t
IA
PLH
t
PHL
Y
Z
Input
100%
80%
V
OD
100 Ω ± 1 %
Output
V
OD(H)
C
= 10 pF
L
0 V
(2 Places)
V
OD(L)
20%
0%
t
t
r
f
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
r
f
pulsewidth = 10 ± 0.2 ns . C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
Figure 9. ’LVDS105 Test Circuit, Timing, and Voltage Definitions for the Differential output Signal
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
49.9 Ω ± 1% (2 Places)
Y
Z
0.8 V or 2 V
EN
1.2 V
C
= 10 pF
V
OY
V
OZ
L
(2 Places)
(see Note B)
3 V
1.5 V
EN
0 V
t
t
t
PZH
PHZ
PLZ
V
OY
or
1.4 V
1.25 V
V
OZ
1.2 V
t
PZL
1.2 V
1.15 V
1 V
V
OZ
or
V
OY
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulsewidth = 500 ± 10 ns . C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
Figure 10. ’LVDS105 Enable and Disable Time Circuit and Definitions
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTIC
SN65LVDS104
SUPPLY CURRENT
vs
SN65LVDS105
SUPPLY CURRENT
vs
SWITCHING FREQUENCY
SWITCHING FREQUENCY
60
55
50
45
40
35
30
25
50
45
40
35
30
25
20
V
CC
= 3.6 V
V
CC
= 3.6 V
V
= 3 V
CC
V
= 3 V
CC
V
CC
= 3.3 V
V
CC
= 3.3 V
All Outputs Loaded
and Enabled
All Outputs Loaded
and Enabled
50
100
150
200
250
300
350
50
100
150
200
250
300
350
f – Frequency – MHz
f – Frequency – MHz
Figure 11
Figure 12
DRIVER
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
4
3.5
3
V
T
A
= 3.3 V
= 25°C
CC
V
T
A
= 3.3 V
= 25°C
CC
3
2.5
2
2
1
1.5
1
0.5
0
0
0
2
4
6
–1
–4
–3
–2
0
I
– Low-Level Output Current – mA
I
– High-Level Output Current – mA
OL
OH
Figure 13
Figure 14
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTIC
SN65LVDS104
SN65LVDS104
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
3.6
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
3.6
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
V
= 3.3 V
CC
V
CC
= 3 V
V
= 3.3 V
CC
V
CC
= 3 V
V
= 3.6 V
V
CC
= 3.6 V
CC
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
T
A
– Free–Air Temperature – °C
T
A
– Free–Air Temperature – °C
Figure 15
Figure 16
SN65LVDS105
SN65LVDS105
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
2.7
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
2.6
2.5
2.4
2.3
2.2
2.1
2
V
CC
= 3 V
V
= 3 V
CC
V
CC
= 3.3 V
V
= 3.3 V
CC
V
CC
= 3.6 V
V
= 3.6 V
25
CC
–50
–25
0
50
75
100
–50
–25
0
25
50
75
100
T
A
– Free–Air Temperature – °C
T
A
– Free–Air Temperature – °C
Figure 17
Figure 18
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
APPLICATION INFORMATION
A LVDS receiver can be used to receive various other types of logic signals. Figure 19 through Figure 28 show
the termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.
V
DD
50 Ω
25 Ω
A
B
50
Ω
1/2 V
DD
LVDS Receiver
0.1 µF
Figure 19. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL)
V
DD
50 Ω
A
B
50 Ω
1.35 V < V < 1.65 V
TT
LVDS Receiver
0.1 µF
Figure 20. Center-Tap Termination (CTT)
1.14 V < V < 1.26 V
TT
V
DD
1 kΩ
50 Ω
50 Ω
A
B
2 kΩ
0.1 µF
LVDS Receiver
Figure 21. Gunning Transceiver Logic (GTL)
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
APPLICATION INFORMATION
Z
0
Z
0
A
B
1.47 V < V < 1.62 V
TT
LVDS Receiver
0.1 µF
Figure 22. Backplane Transceiver Logic (BTL)
3.3 V
3.3 V
ECL
120 Ω
33 Ω
120 Ω
50 Ω
50 Ω
33 Ω
A
B
51 Ω
51 Ω
LVDS Receiver
Figure 23. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
APPLICATION INFORMATION
5 V
5 V
82 Ω
82 Ω
50 Ω
50 Ω
ECL
100 Ω
100 Ω
A
B
33 Ω
33 Ω
LVDS Receiver
Figure 24. Postive Emitter-Coupled Logic (PECL)
3.3 V
3.3 V
7.5 kΩ
A
B
7.5 kΩ
0.1 µF
LVDS Receiver
Figure 25. 3.3-V CMOS
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
APPLICATION INFORMATION
5 V
5 V
10 kΩ
560 Ω
A
B
560 Ω
3.32 kΩ
0.1 µF
LVDS Receiver
LVDS Receiver
LVDS Receiver
Figure 26. 5-V CMOS
5 V
5 V
10 kΩ
470 Ω
A
B
3.3 V
4.02 kΩ
0.1 µF
Figure 27. 5-V TTL
3.3 V
3.3 V
4.02 kΩ
560 Ω
A
B
3.01 kΩ
0.1 µF
Figure 28. LVTTL
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100
mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it
handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
will pull each line of the signal pair to near V
through 300-kΩ resistors as shown in Figure 10. The fail-safe
CC
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
V
CC
300 kΩ
300 kΩ
A
Rt = 100 Ω (Typ)
Y
B
V
IT
≈ 2.3 V
Figure 29. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999
MECHANICAL INFORMATION
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
M
0,10
0,65
0,19
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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