SN65LVDS108DBTG4 [TI]
1:8 LVDS 时钟扇出缓冲器 | DBT | 38 | -40 to 85;
| 型号： | SN65LVDS108DBTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1:8 LVDS 时钟扇出缓冲器 | DBT | 38 | -40 to 85 时钟 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总16页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
DBT PACKAGE
(TOP VIEW)
One Line Receiver and Eight Line Drivers
Configured as an 8-Port LVDS Repeater
Line Receiver and Line Drivers Meet or
Exceed the Requirements of ANSI
EIA/TIA-644 Standard
GND
ANC
AY
AZ
BY
BZ
CY
CZ
DY
DZ
EY
EZ
FY
FZ
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
V
2
CC
GND
NC
3
Designed for Signaling Rates up to
622 Mbps
4
ENM
ENA
ENB
ENC
END
A
5
Enabling Logic Allows Individual Control of
Each Driver Output, Plus all Outputs
6
7
8
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100Ω Load
9
10
11
12
13
14
15
16
B
Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Termination Networks
ENE
ENF
ENG
ENH
NC
GY
GZ
HY
HZ
NC
NC
Propagation Delay Times < 4.7 ns
Output Skew Less Than 300 ps and
Part-to-Part Skew Less Than 1.5 ns
GND 17
18
GND 19
V
CC
Total Power Dissipation at 200 MHz
Typically Less Than 330 mW With 8
Channels Enabled
Driver Outputs or Receiver Input Equals
High Impedance When Disabled or With
V
< 1.5 V
CC
Bus-Pin ESD Protection Exceeds 12 kV
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
description
The SN65LVDS108 is configured as one differential line receiver connected to eight differential line drivers.
Individual output enables are provided for each output and an additional enable is provided for all outputs.
The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling
(LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise
emission, high noise immunity, and high switching speeds. It can be used to transmit data at speeds up to at
least 622 Mbps and over relatively long distances. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)
The intended application of this device, and the LVDS signaling technique, is for point-to-point or
point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of
approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The
large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced
signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is
particularly advantageous for implementing system clock or data distribution trees.
The SN65LVDS108 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
logic diagram (positive logic)
AY
AZ
ENA
ENM
BY
BZ
ENB
CY
CZ
ENC
END
DY
DZ
A
B
EY
EZ
ENE
FY
FZ
ENF
ENG
ENH
GY
GZ
HY
HZ
selection guide to LVDS splitter
The SN65LVDS108 is one member of a family of LVDS splitters and repeaters. A brief overview of the family
is provided in the following table.
LVDS SPLITTER AND REPEATER FAMILY
NUMBER
OF INPUTS
NUMBER OF
OUTPUTS
DEVICE
PACKAGE
COMMENTS
SN65LVDS104
SN65LVDS105
SN65LVDS108
SN65LVDS109
SN65LVDS116
SN65LVDS117
1 LVDS
1 LVTTL
1 LVDS
2 LVDS
1 LVDS
2 LVDS
4 LVDS
4 LVDS
8 LVDS
8 LVDS
16 LVDS
16 LVDS
16-pin D
4-Port LVDS Repeater
16-pin D
4-Port TTL-to-LVDS Repeater
8-Port LVDS Repeater
38-pin DBT
38-pin DBT
64-pin DGG
64-pin DGG
Dual 4-Port LVDS Repeater
16-Port LVDS Repeater
Dual 8-Port LVDS Repeater
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
FUNCTION TABLE
INPUTS
OUTPUTS
V
= V – V
A
ENM ENx
xY
Z
xZ
Z
ID
B
X
X
L
X
H
H
H
X
L
Z
Z
V
≥ 100 mV
H
H
H
H
?
L
ID
–100 mV < V < 100 mV
?
ID
≤–100 mV
V
L
H
ID
H = high level, L = low level, Z = high impedance, X = don’t care,
? = indeterminate
equivalent input and output schematic diagrams
V
CC
V
CC
V
CC
300 kΩ
(ENM Only)
300 kΩ
300 kΩ
50 Ω
Enable
Inputs
10 kΩ
5 Ω
Y or Z
Output
7 V
A Input
B Input
7 V
300 kΩ
7 V
7 V
(ENx Only)
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
CC
Input voltage range, Enable inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
A, B, Y or Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Electrostatic discharge, Y, Z, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:12 kV, B: 500 V
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 4 kV, B: 400 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
‡
T
≤ 25°C
DERATING FACTOR
T = 85°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
DBT
1277 mW
10.2 mW/°C
644 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k)
with no air flow.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
recommended operating conditions
MIN NOM
MAX
UNIT
Supply voltage, V
CC
3
2
3.3
3.6
V
V
V
V
High-level input voltage, V
IH
Low-level input voltage, V
IL
Magnitude of differential input voltage, V
0.8
3.6
0.1
ID
V
V
ID
V
ID
2.4 –
Common-mode input voltage, V
IC
2
2
V
CC
– 0.8
V
Operating free-air temperature, T
–40
85
°C
A
electrical characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
Differential output voltage magnitude
100
ITH+
See Figure 1 and Table 1
mV
–100
ITH–
V
247
340
454
50
OD
R = 100 Ω,
See Figure 1 and Figure 2
V = ±100 mV,
ID
L
mV
V
Change in differential output voltage magnitude
between logic states
∆ V
–50
OD
V
Steady-state common-mode output voltage
1.125
–50
1.375
50
OC(SS)
Change in steady-state common-mode output
voltage between logic states
∆V
See Figure 3
OC(SS)
mV
V
Peak-to-peak common-mode output voltage
50
62
8
150
85
OC(PP)
Enabled,
Disabled
R = 100 Ω
L
I
Supply current
mA
CC
12
V = 0 V
–2
–20
I
I
I
Input current (A or B inputs)
µA
V = 2.4 V
I
–1.2
I
I
I
Power-off input current (A or B inputs)
High-level input current (enables)
Low-level input current (enables)
V
V
V
V
V
V
V
= 1.5 V,
V = 2.4 V
20
±20
±10
±24
±12
±1
µA
µA
µA
I(OFF)
CC
I
= 2 V
IH
IH
= 0.8 V
IL
IL
or V
OZ
= 0 V
= 0 V
OY
OD
I
Short-circuit output current
mA
OS
I
I
High-impedance output current
Power-off output current
= 0 V or V
CC
µA
µA
OZ
O
= 1.5 V,
V = 3.6 V
O
±1
O(OFF)
CC
C
Input capacitance (A or B inputs)
V = 0.4 sin (4E6πt) + 0.5 V
I
5
IN
pF
V = 0.4 sin (4E6πt) + 0.5 V,
Disabled
I
C
Output capacitance (Y or Z outputs)
9.4
O
†
All typical values are at 25°C and with a 3.3 V supply.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
switching characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
TEST CONDITIONS
MIN TYP
MAX
4.5
4.5
1.2
1.2
500
300
1.5
15
UNIT
t
t
t
t
t
t
t
t
t
t
t
1.6
1.6
0.3
0.3
2.8
2.8
0.8
0.8
150
PLH
PHL
r
ns
R
C
= 100 Ω,
= 10 pF,
L
L
ns
Differential output signal fall time
f
See Figure 4
‡
- t |)
PHL PLH
Pulse skew (|t
sk(p)
sk(o)
sk(pp)
PZH
PZL
PHZ
PLZ
ps
ns
§
Output skew
Part-to-part skew
#
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
5.7
7.7
3.2
3.2
15
ns
ns
See Figure 5
15
15
†
All typical values are at 25°C and with a 3.3 V supply.
‡
§
#
t
t
t
is the magnitude of the time difference between the t
is the magnitude of the time difference between the t
is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
and t of any output of a single device.
PHL
sk(p)
sk(o)
sk(pp)
PLH
PLH
or t
measured at any two outputs.
PHL
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
PARAMETER MEASUREMENT INFORMATION
I
I
IA
OY
A
B
Y
Z
V
V
OD
V
ID
I
IB
I
OZ
V
OY
V
OC
V
IA
(V
OY
+ V )/2
OZ
OZ
V
IB
Figure 1. Voltage and Current Definitions
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
V
IA
V
IB
V
ID
V
IC
1.25 V
1.15 V
2.4 V
2.3 V
0.1 V
0 V
1.15 V
1.25 V
2.3 V
2.4 V
0 V
100 mV
-100 mV
100 mV
-100 mV
100 mV
-100 mV
600 mV
-600 mV
600 mV
-600 mV
600 mV
-600 mV
1.2 V
1.2 V
2.35 V
2.35 V
0.05 V
0.05 V
1.2 V
1.2 V
2.1 V
2.1 V
0.3 V
0.3 V
0.1 V
0.9 V
1.5 V
1.8 V
2.4 V
0 V
1.5 V
0.9 V
2.4 V
1.8 V
0.6 V
0 V
0.6 V
3.75 kΩ
Y
Z
V
OD
Input
100 Ω
3.75 kΩ
0 V ≤ V
≤ 2.4 V
±
TEST
Figure 2. VOD Test Circuit
49.9 Ω ± 1% (2 Places)
V
I
I
1.4 V
1 V
Y
V
Input
Z
V
OC(PP)
50 pF
V
V
OC
OC(SS)
V
O
NOTE A: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulsewidth=500±10ns.C includesinstrumentationandfixturecapacitancewithin0,06mmoftheD.U.T.ThemeasurementofV
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
L
OC(PP)
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
1.4 V
1.2 V
V
IB
Input
1 V
V
t
IA
PLH
t
PHL
Y
Z
A
B
Input
100%
80%
V
OD
100 Ω ± 1 %
Output
V
OD(H)
C
= 10 pF
L
0 V
(2 Places)
V
OD(L)
20%
0%
t
t
r
f
NOTE A: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
r
f
pulsewidth = 10 ±0.2 ns . C includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
L
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
49.9 Ω ± 1% (2 Places)
Y
1 V or 1.4 V
Z
1.4 V or 1 V
1.2 V
C
= 10 pF
L
V
OY
V
OZ
(2 Places)
ENM
ENx
Inputs
2 V
1.4 V
Input
0.8 V
t
t
t
PZH
PHZ
PLZ
V
OY
or
100%, 1.4 V
50%
V
OZ
0%, 1.2 V
t
PZL
100%, 1.2 V
50%
0%, 1 V
V
OZ
or
V
OY
NOTE A: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulsewidth = 500 ±10 ns . C includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
L
Figure 5. Enable and Disable Time Circuit and Definitions
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
SWITCHING FREQUENCY
FREE-AIR TEMPERATURE
140
120
100
80
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
V
CC
= 3.6 V
V
CC
= 3 V
V
CC
= 3.3 V
V
CC
= 3.3 V
60
V
CC
= 3 V
V
CC
= 3.6 V
40
20
All Outputs Loaded
and Enabled
0
0
50
100
150
200
250
300
350
–50
–25
0
25
50
75
100
f – Frequency – MHz
T
A
– Free–Air Temperature – °C
Figure 6
Figure 7
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
2.9
V
CC
= 3.3 V
V
CC
= 3.6 V
V
CC
= 3 V
–50
–25
0
25
50
75
100
T
A
– Free–Air Temperature – °C
Figure 8
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
Figure 9. Typical Differential Eye Pattern at 400 Mbps
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
The SN65LVDS108 device solves several problems common to the distribution of timing critical clock and data
signals. These problems include:
Excessive skew between the signal paths
Noise pickup over long signaling paths
High power consumption
Control of which signal paths are enabled or disabled
Elimination of radiation from unterminated lines
Buffering and splitting the signal on the same silicon die minimizes corruption of the timing relation between the
copies of the signal. Buffering and splitting the signal in separate devices will introduce considerably higher
levels of uncontrolled timing skew between the signals. Higher speed operation and more timing tolerance for
other components of the system is enabled by the tighter system timing budgets provided by the single die
implementations of the SN65LVDS108.
The use of LVDS signaling technology for both the inputs and the outputs provides superior common-mode and
noise tolerance compared to single-ended I/O technologies. This is particularly important because the signals
that are being distributed must be transmitted over longer distances, and at higher rates, than can be
accommodated with single-ended I/Os. In addition, LVDS consumes considerably less power than other
high-performance differential signaling schemes.
The enable inputs provided for each output may be used to turn on or off any of the paths. This function is
required to prevent radiation of signals from the unterminated signal lines on open connectors when boards or
devices are being swapped in the end equipment. The individual channel enables are also required if redundant
paths are being utilized for reliability reasons.
The following diagram shows how an input signal is being identically repeated out two of the available outputs.
A third output is shown in the disabled state.
DESTINATION
EQUIPMENT/
BOARD #1
DESTINATION
EQUIPMENT/
BOARD #2
SOURCE
EQUIPMENT/
BOARD
Output Pair Disabled
DESTINATION
EQUIPMENT/
BOARD #n
Figure 10. LVDS Repeating Splitter Application Example Showing Individual Path Control
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
A LVDS receiver can be used to receive various other types of logic signals. Figure 12 through Figure 20 show the
termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.
V
DD
50 Ω
25 Ω
A
B
50
Ω
1/2 V
DD
LVDS Receiver
0.1 µF
Figure 11. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL)
V
DD
50 Ω
A
B
50 Ω
1.35 V < V < 1.65 V
TT
LVDS Receiver
0.1 µF
Figure 12. Center-Tap Termination (CTT)
1.14 V < V < 1.26 V
TT
V
DD
1 kΩ
50 Ω
50 Ω
A
B
2 kΩ
0.1 µF
LVDS Receiver
Figure 13. Gunning Transceiver Logic (GTL)
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
Z
0
Z
0
A
B
1.47 V < V < 1.62 V
TT
LVDS Receiver
0.1 µF
Figure 14. Backplane Transceiver Logic (BTL)
3.3 V
3.3 V
ECL
120 Ω
33 Ω
120 Ω
50 Ω
50 Ω
A
33 Ω
B
51 Ω
51 Ω
LVDS Receiver
Figure 15. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
5 V
5 V
82 Ω
82 Ω
50 Ω
50 Ω
ECL
100 Ω
A
100 Ω
B
33 Ω
33 Ω
LVDS Receiver
Figure 16. Positive Emitter-Coupled Logic (PECL)
3.3 V
3.3 V
7.5 kΩ
A
B
7.5 kΩ
0.1 µF
LVDS Receiver
Figure 17. 3.3-V CMOS
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
5 V
5 V
10 kΩ
560 Ω
A
B
560 Ω
3.32 kΩ
0.1 µF
LVDS Receiver
Figure 18. 5-V CMOS
5 V
5 V
10 kΩ
470 Ω
A
B
3.3 V
4.02 kΩ
0.1 µF
LVDS Receiver
Figure 19. TTL
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
MECHANICAL DATA
DBT (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,27
0,17
M
0,50
30
0,08
16
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
15
0°–8°
0,75
0,50
A
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
28
30
38
44
50
DIM
7,90
7,70
7,90
7,70
9,80
9,60
11,10
10,90
12,60
12,40
A MAX
A MIN
4073252/D 09/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-153
15
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