SN65LVDS122_14 [TI]
1.5-Gbps 2 ´ 2 LVDS CROSSPOINT SWITCH;
| 型号： | SN65LVDS122_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.5-Gbps 2 ´ 2 LVDS CROSSPOINT SWITCH |
| 文件： | 总18页 (文件大小：534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS122
SN65LVDT122
www.ti.com
SLLS525B–MAY 2002–REVISED JUNE 2004
1.5-Gbps 2 × 2 LVDS CROSSPOINT SWITCH
FEATURES
•
DESCRIPTION
Designed for Signaling Rates (1) Up To
1.5 Gbps
The SN65LVDS122 and SN65LVDT122 are
crosspoint switches that use low voltage differential
signaling (LVDS) to achieve signaling rates as high
as 1.5 Gbps. They are pin-compatible speed up-
grades to the SN65LVDS22 and SN65LVDM22. The
internal signal paths maintain differential signaling for
high speeds and low signal skews. These devices
have a 0-V to 4-V common-mode input range that
accepts LVDS, LVPECL, or CML inputs. Two logic
pins (S0 and S1) set the internal configuration be-
tween the differential inputs and outputs. This allows
the flexibility to perform the following configurations:
2 x 2 crosspoint switch, 2:1 input multiplexer, 1:2
splitter or dual repeater/translator within a single
device. Additionally, SN65LVDT122 incorporates a
110-Ω termination resistor for those applications
where board space is a premium. Although these
devices are designed for 1.5 Gbps, some applications
at a 2-Gbps data rate can be supported depending on
loading and signal quality.
•
•
Total Jitter < 65 ps
Pin-Compatible With SN65LVDS22 and
SN65LVDM22
•
•
25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Common-Mode Range
Inputs Electrically Compatible With CML,
LVPECL and LVDS Signal Levels
•
•
•
Propagation Delay Times, 900 ps Maximum
LVDT Integrates 110-Ω Terminating Resistor
Offered in SOIC and TSSOP
APPLICATIONS
•
•
•
•
•
10-G (OC-192) Optical Modules
622-MHz Central Office Clock Distribution
Wireless Basestations
Low Jitter Clock Repeater/Multiplexer
Protection Switching for Serial Backplanes
The intended application of this device is ideal for
loopback switching for diagnostic routines, fanout
buffering of clock/data distribution provide protection
in fault-tolerant systems, clock multiplexing in optical
modules, and for overall signal boosting over
extended distances.
(1) The signlaing rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
The SN65LVDS122 and SN65LVDT122 are
characterized for operation from –40°C to 85°C.
EYE PATTERNS OF OUTPUTS
OPERATING SIMULTANEOUSLY
FUNCTIONAL DIAGRAM
1DE
1A
1Y
1.5 Gbps
− 1 PRBS
110 Ω
23
V
1Z
2
OUTPUT 1
1B
S0
= 3.3 V
CC
V
ID
= 200 mV, V = 1.2 V
IC
MUX
S1
2A
Vertical Scale=200 mV/div
2Y
2Z
110 Ω
OUTPUT 2
2B
2DE
Integrated Termination on SN65LVDT122 Only
Horizontal Scale= 200 ps/div
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LVDS122
SN65LVDT122
www.ti.com
SLLS525B–MAY 2002–REVISED JUNE 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE
SOIC
TERMINATION RESISTOR
PART NUMBER(1)
SN65LVDS122D
SN65LVDT122D
SN65LVDS122PW
SN65LVDT122PW
SYMBOLIZATION
LVDS122
No
Yes
No
SOIC
LVDT122
TSSOP
TSSOP
LVDS122
Yes
LVDT122
(1) Add the suffix R for taped and reeled carrier
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
SN65LVDS122, SN65LVDT122
–0.5 V to 4 V
–0.7 V to 4.3 V
1 V
VCC
Supply voltage range(2)
Voltage range
(A, B)
|VA-VB| (LVDT only)
(DE, S0, S1)
(Y, Z)
–0.5 V to 4 V
–0.5 V to 4 V
±4 kV
A, B, Y, Z, and GND
Human Body Model(3)
ESD
All pins
All pins
±2 kV
Charged-Device Model(4)
±1500 V
Continuous power dissipation
Storage temperature range
See Dissipation Rating Table
–65°C to 150°C
260°C
Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.7.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX
3.6
4
UNIT
VCC Supply voltage
3
2
3.3
V
V
V
VIH
VIL
High-level input voltage
S0, S1, 1DE, 2DE
S0, S1, 1DE, 2DE
LVDS
Low-level input voltage
0
0.8
1
0.1
0.1
0
|VID
|
Magnitude of differential input voltage
V
LVDT
0.8
4
Input voltage (any combination of common-mode or input signals)
Operating free-air temperature
V
TA
–40
85
°C
PACKAGE DISSIPATION RATINGS
T
A ≤ 25°C
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
PW
D
712 mW
6.2 mW/°C
8.7 mW/°C
340 mW
1002 mW
480 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
2
SN65LVDS122
SN65LVDT122
www.ti.com
SLLS525B–MAY 2002–REVISED JUNE 2004
INPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 1 and Table 1
MIN TYP(1) MAX UNIT
VIT+
VIT-
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
100
mV
mV
mV
See Figure 1 and Table 1
–100(2)
VID(HYS) Differential input voltage hysteresis (VIT+– VIT-
)
25
DE
–10
0
0
20
0
IIH
High-level input current
Low-level input current
Supply current
VIH = 2
µA
µA
mA
µA
µA
S0, S1
DE
–10
IIL
VIL = 0.8 V
S0, S1
20
RL = 100 Ω
80 100
ICC
Disabled
35
45
20
33
40
66
VI = 0 V or 2.4 V, Other input at 1.2 V
VI = 4 V, Other input at 1.2 V
VI = 0 V or 2.4 V, Other input open
VI = 4 V, Other input open
–20
0
Input current (A or B inputs 'LVDS)
Input current (A or B inputs 'LVDT)
II
–40
0
VCC = 1.5 V, VI = 0 V or 2.4 V,
Other input at 1.2 V
–20
0
20
33
40
Input current (A or B inputs 'LVDS)
Input current (A or B inputs 'LVDT)
µA
VCC = 1.5 V, VI = 2.4 V or 4 V,
Other input at 1.2 V
II(OFF)
VCC = 1.5 V, VI = 0 V or 2.4 V,
Other input open
–40
µA
µA
Ω
VCC = 1.5 V, VI = 2.4 V or 4 V,
Other input open
0
–6
90
66
6
IIO
Input offset current (| IIA– IIB |) 'LVDS
Termination resistance ('LVDT)
VIA = VIB, 0 ≤ VIA ≤ 4 V
VID = 300 mV and 500 mV,
VIC = 0 V to 2.4 V
110 132
110 132
RT
VID = 300 mV and 500 mV,
VCC = 1.5 V, VIC = 0 V to 2.4 V
Termination resistance ('LVDT with power-off)
90
VI = 0.4 sin (4E6πt) + 0.5 V
3
3
Differential input capacitance ('LVDT with
power-off)
CI
pF
Powered down (VCC = 1.5 V)
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
OUTPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 2
MIN TYP(1)
MAX UNIT
|VOD
|
Differential output voltage magnitude
247
310
454
mV
50
Change in differential output voltage magnitude between logic
states
∆|VOD
|
–50
VOC(SS)
Steady-state common-mode output voltage
1.125
–50
1.375
50
V
Change in steady-state common-mode output voltage between
logic states
∆VOC(SS)
See Figure 3
mV
VOC(PP)
IOS
Peak-to-peak common-mode output voltage
Short-circuit output current
50
150
24
12
1
mV
mA
mA
VO(Y) or VO(Z) = 0 V
VOD = 0 V
–24
–12
–1
IOS(D)
Differential short-circuit output current
VOD = 600 mV
IOZ
Co
High-impedance output current
Differential output capacitance
µA
pF
VO = 0 V or VCC
VI = 0.4 sin (4E6πt) + 0.5 V
–1
1
3
(1) All typical values are at 25°C and with a 3.3-V supply.
3
SN65LVDS122
SN65LVDT122
www.ti.com
SLLS525B–MAY 2002–REVISED JUNE 2004
TIMING CHARACTERISTICS
PARAMETER
Input to select setup time
TEST CONDITIONS
MIN NOM MAX UNIT
tSET
0
0.5
1
ns
ns
ns
tHOLD
tSWITCH
Input to select hold time
Select to switch output
2
2.6
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN NOM(1) MAX UNIT
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time (20% - 80%)
Differential output signal fall time (20% - 80%)
Pulse skew (|tPHL - tPLH|)(2)
400
400
650
650
900
900
280
280
50
100
2.2
17
65
50
8
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ps
See Figure 4
tf
tsk(p)
10
tsk(pp) Part-to-part skew(3)
tjit(per) Period jitter, rms (1 standard deviation)(4)
VID = 0.2 V
750 MHz clock input(5)
1
10
33
17
6
Cycle-to-cycle jitter (peak)(4)
Peak-to-peak jitter(4)
750 MHz clock input
(6)
tjit(cc)
tjit(pp)
1.5 Gbps 223–1 PRBS input(7)
1.5 Gbps 27–1 PRBS input(8)
See Figure 5
tjit(det) Deterministic jitter, peak-to-peak(4)
tPHZ
tPLZ
tPZH
tPZL
tsk(o)
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Output skew(9)
See Figure 5
6
8
See Figure 5
4
6
See Figure 5
4
6
15
40
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(4) Jitter is specified by design and characterization. Stimulus jitter has been subtracted.
(5) Input voltage = VID = 200 mV, 50% duty cycle at 750 MHz, tr = tf = 50 ps (20% to 80%), measured over 1000 samples.
(6) Input voltage = VID = 200 mV, 50% duty cycle at 750 MHz, tr = tf = 50 ps (20% to 80%).
(7) Input voltage = VID = 200 mV, 223–1 PRBS pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%), measured over 200 k samples.
(8) Input voltage = VID = 200 mV, 27–1 PRBS pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%).
(9) Output skew is the magnitude of the time delay difference between the outputs of a single device with all inputs tied together.
4
SN65LVDS122
SN65LVDT122
www.ti.com
SLLS525B–MAY 2002–REVISED JUNE 2004
PIN ASSIGNMENT
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
S0
1DE
S1
2A
V
V
1Y
1Z
2DE
2Z
CC
CC
2B
GND
2Y
GND
Circuit Function Table
INPUTS(1)
OUTPUTS(1)
LOGIC DIAGRAM
1VID
2VID
X
S1
X
L
S0
X
L
1DE
2DE
L
1VOD
Z
2VOD
Z
X
L
H
H
H
H
L
> 100 mV
X
L
H
L
Z
< -100 mV
< -100 mV
> 100 mV
> 100 mV
< -100 mV
> 100 mV
< -100 mV
< -100 mV
< -100 mV
> 100 mV
> 100 mV
X
X
L
L
L
Z
1DE
1A / 1B
1Y / 1Z
X
L
L
H
H
H
H
L
L
L
X
L
L
H
Z
H
H
L
2A / 2B
2Y / 2Z
2DE
X
L
L
X
L
L
L
Z
X
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
L
H
L
Z
X
L
L
Z
< -100 mV
> 100 mV
< -100 mV
> 100 mV
> 100 mV
< -100 mV
> 100 mV
< -100 mV
< -100 mV
> 100 mV
> 100 mV
< -100 mV
> 100 mV
< -100 mV
< -100 mV
> 100 mV
< -100 mV
> 100 mV
X
L
H
H
H
H
H
H
L
L
L
1DE
1A / 1B
2A / 2B
1Y / 1Z
L
L
H
L
L
H
H
Z
2Y / 2Z
2DE
L
H
H
L
L
X
L
L
Z
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
Z
1DE
X
L
L
Z
1Y / 1Z
1A / 1B
2A / 2B
X
L
H
H
H
H
L
L
L
X
L
H
Z
H
H
L
2Y / 2Z
2DE
X
L
X
L
L
Z
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
Z
X
L
Z
1DE
< -100 mV
< -100 mV
> 100 mV
> 100 mV
> 100 mV
< -100 mV
H
H
H
H
H
H
L
L
1A / 1B
2A / 2B
1Y / 1Z
H
L
L
H
H
H
L
2Y / 2Z
2DE
H
Z
X
L
Z
(1) H = high level, L = low level, Z = high impedance, X = don't care
5
SN65LVDS122
SN65LVDT122
www.ti.com
SLLS525B–MAY 2002–REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION
I
IA
A
B
Y
Z
V
OD
V
ID
V
IA
V
OY
V
IC
(V +V )/2
IA IB
(V +V )/2
OY OZ
I
IB
V
IB
V
OZ
Figure 1. Voltage and Current Definitions
3.74 kΩ
Y
V
OD
100 Ω
0 V ≤ V
≤ 2.4 V
test
+
Z
_
3.74 kΩ
Figure 2. Differential Output Voltage (VOD) Test Circuit
A
≈ 1.4 V
≈ 1 V
49.9 Ω ±1%
A
B
Y
B
V
ID
V
V
OC(SS)
OC(PP)
V
OC
Z
1 pF
V
49.9 Ω ±1%
OC
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns; RL = 100 Ω; CL includes instrumentation and fixture capacitance within
0,06 mm of the D.U.T.; the measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least
300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
V
1.4 V
1 V
IA
IB
A
B
Y
Z
V
100 Ω
1 pF
V
OD
V
ID
V
IA
0.4 V
0 V
-0.4 V
V
ID
V
IB
t
t
PLH
PHL
80%
0 V
V
OD
20%
t
f
t
r
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 4. Timing Test Circuit and Waveforms
6
SN65LVDS122
SN65LVDT122
www.ti.com
SLLS525B–MAY 2002–REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION (continued)
3 V
1.5 V
49.9 Ω ±1%
Y
DE
A
1 V or 1.4 V
1 pF
0 V
1.4 V
1.25 V
1.2 V
1.2 V
49.9 Ω ±1%
V
or V
OY
OZ
OZ
B
Z
DE
1.2 V
t
t
PHZ
PZH
1.2 V
1.15 V
1 V
V
or V
OY
t
t
PLZ
PZL
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
A
B
C
INPUT 1
INPUT 2
D
SEL 0/1
t
t
(HOLD)
(SET)
A
B
C
D
OUTPUT1
t
(SWITCH)
Figure 6. Example Switch, Setup, and Hold Times
7
SN65LVDS122
SN65LVDT122
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SLLS525B–MAY 2002–REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION (continued)
t(SET) and t(HOLD) times specify that data must be in a stable state before and after multiplex control switches.
Table 1. Receiver Input Voltage Threshold Test
APPLIED
VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
OUTPUT(1)
VIA
VIB
VID
VIC
1.25 V
1.15 V
4.0 V
3.9 V
0.1 V
0.0 V
1.7 V
0.7 V
4.0 V
3.0 V
1.0 V
0.0 V
1.15 V
1.25 V
3.9 V
4. 0 V
0.0 V
0.1 V
0.7 V
1.7 V
3.0 V
4.0 V
0.0 V
1.0 V
100 mV
1.2 V
1.2 V
3.95 V
3.95 V
0.05 V
0.05 V
1.2 V
1.2 V
3.5 V
3.5 V
0.5 V
0.5 V
H
L
–100 mV
100 mV
H
L
–100 mV
100 mV
H
L
–100 mV
1000 mV
–1000 mV
1000 mV
–1000 mV
1000 mV
–1000 mV
H
L
H
L
H
L
(1) H = high level, L = low level
8
SN65LVDS122
SN65LVDT122
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SLLS525B–MAY 2002–REVISED JUNE 2004
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
INPUT LVDS122
V
CC
V
CC
A
B
7 V
7 V
V
CC
V
CC
300 kΩ
S0, S1
400 Ω
DE1, DE2
400 Ω
300 kΩ
7 V
7 V
OUTPUT LVDS122
V
CC
V
CC
V
CC
Y
Z
7 V
7 V
9
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SN65LVDT122
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SLLS525B–MAY 2002–REVISED JUNE 2004
TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT
VOLTAGE
DIFFERENTIAL PROPAGATION
DIFFERENTIAL PROPAGATION
DELAY
DELAY
vs
vs
vs
FREQUENCY
COMMON-MODE INPUT VOLTAGE
TEMPERATURE
350
1000
800
700
V
= 3.3 V
CC
= 25°C
T
A
300
250
t
900
V
= 200 mV
PHL
ID
f = 150 MHz
600
500
400
300
200
100
0
t
PLH
800
700
200
150
t
PHL
V
T
V
= 3.3 V
CC
= 25°C
100
50
A
t
PLH
= 1.2 V
= 200 mV
V
= 3.3 V
CC
IC
600
500
V
V
= 200 mV
ID
ID
Input = Clock
f = 150 MHz
0
0
1
2
3
4
5
1600
800
−40 −20
0
20 40
60
80 100
0
500
1000
1500
2000
V
− Common-Mode Input Voltage − V
IC
f − Frequency − MHz
T
A
− Free Air Temperature − °C
Figure 7.
Figure 8.
Figure 9.
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
vs
vs
vs
FREQUENCY
DATA RATE
FREQUENCY
30
60
30
V
T
= 3.3 V
V
T
= 3.3 V
= 25°C
V
T
V
= 3.3 V
= 25°C
= 400 mV
Input = Clock
CC
CC
CC
= 25°C
A
A
A
25
20
50
40
25
20
V
= 400 mV
V
= 1.2 V
IC
IC
IC
23
Input = PRBS 2 −1
Input = Clock
V
= 0.5 V
ID
V
= 0.5 V
V
= 0.8 V
ID
ID
15
30
15
V
= 0.8 V
ID
V
= 0.3 V
ID
V
= 0.5 V
ID
V
= 0.8 V
ID
10
5
20
10
0
10
5
V
= 0.3 V
1200
ID
V
= 0.3 V
200
ID
0
0
0
400
600
800
0
400
800
0
200
400
600
800
f − Frequency − MHz
Data Rate − Mbps
f − Frequency − MHz
Figure 10.
Figure 11.
Figure 12.
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
vs
vs
vs
DATA RATE
FREQUENCY
DATA RATE
60
30
60
V
T
= 3.3 V
= 25°C
V
= 3.3 V
= 25°C
= 2.8 V
CC
CC
V
= 0.3 V
ID
T
A
A
50
40
25
20
50
40
V
= 1.2 V
Input = PRBS 2 −1
V
IC
IC
23
V
= 0.8 V
Input = Clock
ID
V
= 0.3 V
ID
V
= 0.8 V
V
= 0.8 V
ID
ID
30
15
30
V
= 0.5 V
ID
V
= 0.5 V
ID
20
10
0
10
5
20
10
0
V
T
A
= 3.3 V
CC
= 25°C
V
= 0.3 V
V
= 2.8 V
ID
IC
Input = PRBS 2 −1
V
= 0.5 V
600
23
ID
0
0
400
800
1200
1600
0
200
400
0
400
800
1200
1600
Data Rate − Mbps
f − Frequency − MHz
Data Rate − Mbps
Figure 13.
Figure 14.
Figure 15.
10
SN65LVDS122
SN65LVDT122
www.ti.com
SLLS525B–MAY 2002–REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
PEAK-TO-PEAK JITTER
vs
PEAK-TO-PEAK JITTER
vs
TEMPERATURE
DATA RATE
50
100
90
V
T
= 3.3 V
V
T
= 3.3 V
CC
= 25°C
CC
= 25°C
A
A
V
= 1.2 V
40
V
V
= 1.2 V
IC
|V |= 200 m V
IC
80
70
= 200 mV
ID
ID
23
Input = PRBS 2 −1
23
Input = 1.5 Gpbs, PRBS 2 −1
30
20
60
50
40
30
20
10
0
10
0
0
500 1000 1500 2000 2500 3000 3500
−40 −20
0
20
40
60
80
100
Data Rate − Mbps
T
A
− Free Air Temperature − °C
Figure 16.
Figure 17.
LVDS122
LVDS122
622 Mbps, 223– 1 PRBS
1.5 Gbps, 223– 1 PRBS
V
T
A
= 3.3 V
V
= 3.3 V
CC
= 25°C
CC
T = 25°C
A
V
= 200 mV
V
= 200 mV
ID
ID
Horizontal Scale= 200 ps/div
LVPECL-to-LVDS
Horizontal Scale= 100 ps/div
LVPECL-to-LVDS
Figure 18.
Figure 19.
11
SN65LVDS122
SN65LVDT122
www.ti.com
SLLS525B–MAY 2002–REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
LVDS122
LVDS122
622 Mbps, 223– 1 PRBS
1.5 Gbps, 223– 1 PRBS
V
T
A
= 3.3 V
V
= 3.3 V
CC
= 25°C
CC
T = 25°C
A
V
= 200 mV
V
= 200 mV
ID
ID
Horizontal Scale= 200 ps/div
LVDS-to-LVDS
Horizontal Scale= 100 ps/div
LVDS-to-LVDS
Figure 20.
Figure 21.
Power Supply 1
+
3.3 V
−
+
Power Supply 2
1.22 V
−
J3
DUT
GND
J2
EVM
GND
J1
VCC
J4
J5
J6
J7
100 Ω
50 Ω
50 Ω
DUT
Matched
Cables
Matched
Cables
Pattern
Generator
SMA to SMA
SMA to SMA
EVM
Oscilloscope
Figure 22. Jitter Setup Connections for SN65LVDS122
12
SN65LVDS122
SN65LVDT122
www.ti.com
SLLS525B–MAY 2002–REVISED JUNE 2004
APPLICATION INFORMATION
TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.)
50 Ω
3.3 V or 5 V
3.3 V
SN65LVDS122
A
B
ECL
50 Ω
50 Ω
50 Ω
V
TT
= V −2 V
CC
V
TT
Figure 23. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
3.3 V
50 Ω
50 Ω
50 Ω
3.3 V
3.3 V
SN65LVDS122
A
B
CML
50 Ω
3.3 V
Figure 24. Current-Mode Logic (CML)
3.3 V
SN65LVDS122
3.3 V
50 Ω
A
ECL
B
50 Ω
1.1 kΩ
1.5 kΩ
V
TT
= V −2 V
CC
V
TT
V
CC
Figure 25. Single-Ended (LVPECL)
50 Ω
3.3 V or 5 V
LVDS
3.3 V
SN65LVDS122
A
B
100 Ω
50 Ω
Figure 26. Low-Voltage Differential Signaling (LVDS)
13
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2005
PACKAGING INFORMATION
Orderable Device
SN65LVDS122D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS122DR
SN65LVDS122DRG4
SN65LVDS122PW
SN65LVDS122PWR
SN65LVDS122PWRG4
SN65LVDT122D
SOIC
SOIC
D
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDT122DR
SN65LVDT122DRG4
SN65LVDT122PW
SN65LVDT122PWG4
SN65LVDT122PWR
SN65LVDT122PWRG4
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Use of such information may require a license from a third party under the patents or other intellectual property
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
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www.ti.com/automotive
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dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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