SN65LVDS19 [TI]
具有使能端的 2.5V/3.3V 振荡器增益级/缓冲器;
| 型号： | SN65LVDS19 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能端的 2.5V/3.3V 振荡器增益级/缓冲器 振荡器 |
| 文件： | 总17页 (文件大小：879K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS18, SN65LVP18
SN65LVDS19, SN65LVP19
www.ti.com
SLLS624B–SEPTEMBER 2004–REVISED NOVEMBER 2005
2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS
FEATURES
•
2-mm x 2-mm Small-Outline
No-Lead Package
•
Low-Voltage PECL Input and Low-Voltage
PECL or LVDS Outputs
APPLICATIONS
•
•
•
Clock Rates to 1 GHz
PECL-to-LVDS Translation
Clock Signal Amplification
– 250-ps Output Transition Times
– 0.12 ps Typical Intrinsic Phase Jitter
– Less than 630 ps Propagation Delay Times
2.5-V or 3.3-V Supply Operation
•
DESCRIPTION
These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain
outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on
the SN65LVx18) and fully differential inputs on the SN65LVx19.
The SN65LVx18 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV
either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The
Q on the SN65LVx19 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended
PECL input signals. When not used, VBB should be unconnected or open.
All devices are characterized for operation from –40°C to 85°C.
SN65LVDS19, SN65LVP19
4 mA
SN65LVDS18, SN65LVP18
4 mA
Q
Q
A
Y
Z
A
B
Y
Z
V
BB
V
V
REF
V
CC
V
BB
V
CC
REF
EN
EN
GC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
SN65LVDS18, SN65LVP18
SN65LVDS19, SN65LVP19
www.ti.com
SLLS624B–SEPTEMBER 2004–REVISED NOVEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS(1)
INPUT
OUTPUT
LVDS
GAIN CONTROL
BASE PART NUMBER
SN65LVDS18
SN65LVP18
PART MARKING
Single-ended
Single-ended
Differential
Differential
Yes
Yes
No
ER
EP
ET
ES
LVPECL
LVDS
SN65LVDS19
SN65LVP19
LVPECL
No
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
(2)
VCC Supply voltage
–0.5 V to 4 V
–0.5 V to VCC + 0.5 V
–0.5 V to VCC + 0.5 V
±0.5 mA
VI
Input voltage
VO
IO
Output voltage
VBB output current
HBM electrostatic discharge(3)
CDM electrostatic discharge(4)
Continuous power dissipation
±3 kV
±1500 V
See Power Dissipation Ratings Table
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground (see Figure 1).
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A-7
(4) Tested in accordance with JEDEC Standard 22, Test Method C101
DISSIPATION RATINGS
TA < 25°C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
DRF
403 mW
4.0 mW/°C
161 mW
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX UNIT
VCC Supply Voltage
2.375 2.5 or 3.3
3.6
V
V
V
VIC
Common-mode input voltage (VIA + VIB)/2
Differential input voltage magnitude |VIA - VIB
SN65LVDS19 or SN65LVP19
SN65LVDS19 or SN65LVP19
EN
1.2
VCC – (VID/2)
|VID
|
|
0.8
1
VCC
2
VCC– 1.17
0
VIH
VIL
High-level input voltage
Low-level input voltage
V
V
SN65LVDS18 or SN65LVP18
EN
VCC– 0.44
0.8
SN65LVDS18 or SN65LVP18
VCC– 2.25
–400(1)
90
VCC– 1.52
400
IO
Output current to VBB
µA
Ω
RL
TA
Differential load resistance
Operating free-air temperature
132
-40
85
°C
(1) The algebraic convention, where the least positive (more negative) value is designated minimum, is used in this data sheet.
2
SN65LVDS18, SN65LVP18
SN65LVDS19, SN65LVP19
www.ti.com
SLLS624B–SEPTEMBER 2004–REVISED NOVEMBER 2005
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
RL = 100 Ω, EN at 0 V,
Other inputs open
30
36
ICC
Supply current
mA
22
Outputs unloaded,
EN at 0 V, Other inputs open
17
VBB
Reference voltage(2)
IBB = –400 µA
VI = 2 V
VCC– 1.44 VCC– 1.35
VCC– 1.25
V
IIH
High-level input current, EN
High-level input current, A or B
Low-level input current, EN
Low-level input current, A or B
–20
–20
–20
–20
20
20
20
20
IIAH or IIBH
IIL
VI = VCC
µA
VI = 0.8 V
VI = GND
IIAL or IIBL
SN65LVDS18/19 Y AND Z OUTPUT CHARACTERISTICS
Differential output voltage
|VOD
|
247
340
454
50
magnitude, |VOY– VOZ
|
mV
V
Change in differential output voltage
magnitude between logic states
∆|VOD
|
See Figure 1 and Figure 2
Steady-state common- mode output
voltage (see Figure 3)
VOC(SS)
∆VOC(SS)
VOC(PP)
1.125
–50
1.375
Change in steady-state
common-mode output voltage
between logic states
50
See Figure 3
mV
Peak-to-peak common-mode output
voltage
50
100
IOYZ or IOZZ High-impedance output current
IOYS or IOZS Short-circuit output current
EN at VCC, VO = 0 V or VCC
EN at 0 V, VOY or VOZ = 0 V
–1
1
µA
–50
50
mA
Differential short-circuit output
IOS(D)
EN at 0 V,
VOY = VOZ
–12
12
current, |IOY– IOZ
|
SN65LVP18/19 Y AND Z OUTPUT CHARACTERISTICS
VOYH or
VOZH
High-level output voltage
VCC– 1.13
VCC– 1.87
VCC– 1.92
VCC– 0.85
VCC– 1.61
VCC– 1.61
3.3 V; 50 Ω from Y and Z
to VCC - 2 V
VOYL or
VOZL
Low-level output voltage
V
VOYL or
VOZL
2.5 V; 50 Ω from Y and Z
to VCC– 2 V
Low-level output voltage
Differential output voltage
|VOD
|
0.6
–1
0.8
1
1
magnitude, |VOH– VOL
|
IOYZ or IOZZ High-impedance output current
EN at VCC, VO = 0 V or VCC
µA
V
Q OUTPUT CHARACTERISTICS (see Figure 1)
VOH
High-level output voltage
No load
VCC– 0.94
VCC– 1.22
VCC– 1.52
VCC– 1.82
300
GC Tied to GND, No load
GC Open, No load
GC Tied to VCC, No load
GC Tied to GND
GC Open
VOL
Low-level output voltage
V
VO(pp)
Peak-to-peak output voltage
575
mV
CGT Tied to VCC
860
(1) Typical values are at room temperature and with a VCC of 3.3 V.
(2) Single-ended input operation is limited to VCC≥ 3.0 V.
3
SN65LVDS18, SN65LVP18
SN65LVDS19, SN65LVP19
www.ti.com
SLLS624B–SEPTEMBER 2004–REVISED NOVEMBER 2005
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
A to Q
340 460
ps
tPD
Propagation delay time, tPLH or tPHL
See Figure 4
D to Y or Z
460 630
tSK(P) Pulse skew, |tPLH - tPHL
|
20
VCC = 3.3 V
80
ps
(2)
tSK(PP) Part-to-part skew
VCC = 2.5 V
130
LVDS, See Figure 4
LVPECL, See Figure 4
LVDS, See Figure 4
LVPECL, See Figure 4
140 250
ps
tr
tf
20%-to-80% differential signal rise time
20%-to-80% differential signal fall time
190 300
140 250
ps
210 300
tjit(per) RMS period jitter(3)
2
17
4
2-GHz 50%-duty-cycle square-wave input,
See Figure 5
ps
ps
(4)
tjit(cc)
tjit(ph)
Peak cycle-to-cycle jitter
Intrinsic phase jitter
24
1 GHz
0.12
Propagation delay time,
high-level-to-high-impedance output
tPHZ
tPLZ
tPZH
tPZL
30
30
30
30
Propagation delay time,
low-level-to-high-impedance output
See Figure 6
ns
Propagation delay time,
high-impedance-to-high-level output
Propagation delay time,
high-impedance-to-low-level output
(1) Typical values are at room temperature and with a VCC of 3.3 V.
(2) Part-to-part skew is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.
(4) Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles, over a random sample of 1,000 adjacent cycle
pairs.
PARAMETER MEASUREMENT INFORMATION
V
CC
I
CC
8
V
1
3
6
7
CC
Q
2
4
5
A
V
BB
50 W
50 W
I
IA
D.U.T.
I
BB
GC
EN
Z
S1
I
OZ
I
IGC
Y
GND
9
+
V
CC
− 2 V
I
I
_
I
OY
C
L
V
IA
V
IB
V
I
+
OY
−
+
−
+
BB
−
+
−
+
+
+
+
_
_
_
V
V
OZ
V
V
O
V
OC
−
(1) CL is the instrumentation and test fixture capacitance.
(2) S1 is open for the SN65LVDS18 and closed for the SN65LVP18.
Figure 1. Output Voltage Test Circuit and Voltage and Current Definitions for LVDS/LVP18
4
SN65LVDS18, SN65LVP18
SN65LVDS19, SN65LVP19
www.ti.com
SLLS624B–SEPTEMBER 2004–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
I
CC
8
V
1
4
6
7
CC
Q
2
3
5
A
B
V
BB
50 W
50 W
I
IA
D.U.T.
I
BB
Z
S1
I
OZ
I
IB
Y
EN
GND
9
+
V
CC
− 2 V
I
I
_
I
OY
C
L
V
IA
V
IB
V
I
+
OY
−
+
−
+
BB
−
+
−
+
+
+
+
_
_
_
V
V
OZ
V
V
O
V
OC
−
(1) CL is the instrumentation and test fixture capacitance.
(2) S1 is open for the SN65LVDS19 and closed for the SN65LVP19.
Figure 2. Output Voltage Test Circuit and Voltage and Current Definitions for LVDS/LVP19
INPUT
V
dV
OC(SS) OC(PP)
V
OC
Figure 3. VOC Definitions
V
CC
1.2 V
1.125 V
V
V
IA
1.5 V
IB
t
t
PHL
PLH
V
− V
OZ
OY
100%
80%
50%
t
f
t
r
20%
Figure 4. Propagation Delay and Transition Time Test Waveforms
5
SN65LVDS18, SN65LVP18
SN65LVDS19, SN65LVP19
www.ti.com
SLLS624B–SEPTEMBER 2004–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
50 W Cable, X + Y cm, SMA Coax
Connectors, 4 Places
TDS Oscilloscope with
TJIT3 Analysis Pack
Device Under Test
HP3104 Pattern
Generator
50 W
50 W
DC
Figure 5. Jitter Measurement Setup
V
CC
1.2 V
V
V
IA
IB
1.5 V
V to EN
I
2 V
1.4 V
t
t
0.8 V
PZH
PZL
t
t
0 V
PHZ
PLZ
V
− V
100%
80%
OY
OZ
50%
20%
Figure 6. Enable and Disable Time Test Waveforms
6
SN65LVDS18, SN65LVP18
SN65LVDS19, SN65LVP19
www.ti.com
SLLS624B–SEPTEMBER 2004–REVISED NOVEMBER 2005
DEVICE INFORMATION
(1)
FUNCTION TABLE
SN65LVDS18, SN65LVP18
SN65LVDS19, SN65LVP19
A
H
EN
Q
L
Y
H
L
Z
L
A
H
B
H
EN
Q
?
H
L
?
?
?
?
Y
?
L
H
?
Z
?
?
Z
?
H
L
?
Z
?
?
L
L
L
L
H
?
H
Z
?
L
H
L
X
H
Z
?
H
L
L
L
Open
X
L
?
L
L
Open
?
?
?
X
X
H
Open
X
Open
X
L
Open
(1) H = high, L = low, Z = high impedance, ? = indeterminate
DRF PACKAGE
TOP VIEW
1
8
4
5
9
BOTTOM VIEW
Package Pin Assignments – Numerical Listing
SN65LVDS18, SN65LVP18
SN65LVDS19, SN65LVP19
PIN
1
SIGNAL
Q
PIN
1
SIGNAL
Q
A
2
A
2
3
VBB
GC
EN
Z
3
B
4
4
VBB
EN
Z
5
5
6
6
7
Y
7
Y
8
VCC
GND
8
VCC
GND
9
9
7
SN65LVDS18, SN65LVP18
SN65LVDS19, SN65LVP19
www.ti.com
SLLS624B–SEPTEMBER 2004–REVISED NOVEMBER 2005
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
LVDS18/19 RISE/FALL TIME
vs
FREE-AIR TEMPERATURE
FREQUENCY
55
45
35
25
15
5
55
45
35
25
15
5
160
152
144
136
128
120
LVP18/19 = Loaded
LVDS18/19
LVP18/19 = Loaded
LVDS18/19
t
t
f
r
−40 −20
0
20
40
60
80
100
0
200
400
600
800
1000
−40 −20
0
20
40
60
80
100
T
A
− Free−Air Temperature − C
T
A
− Free−Air Temperature − C
f − Frequency − MHz
Figure 7.
Figure 8.
Figure 9.
LVP18/19 RISE/FALL TIME
vs
FREE-AIR TEMPERATURE
LVDS18/19 PROPAGATION DELAY
PERIOD JITTER
vs
FREQUENCY
TIME
vs
FREE-AIR TEMPERATURE
230
220
210
200
190
524
5
4
3
2
500
476
452
428
404
t
f
t
PHL
t
PLH
t
r
1
0
180
170
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
80
100
0
200
400
600
800
1000
T
A
− Free−Air Temperature − C
T
A
− Free−Air Temperature − C
f − Frequency − MHz
Figure 10.
Figure 11.
Figure 12.
CYCLE-TO-CYCLE JITTER
vs
FREQUENCY
25
20
15
10
5
0
0
200
400
600
800
1000
f − Frequency − MHz
Figure 13.
8
SN65LVDS18, SN65LVP18
SN65LVDS19, SN65LVP19
www.ti.com
SLLS624B–SEPTEMBER 2004–REVISED NOVEMBER 2005
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
OUTPUT LVP18/19
OUTPUT LVDS18/19
V
CC
V
CC
V
CC
V
CC
V
CC
R
R
Y
V
CC
Y
Z
7 V
Z
7 V
7 V
7 V
V
CC
ENABLE
400 Ω
300 kΩ
7 V
INPUT
V
CC
OUTPUT
V
BB
V
CC
V
CC
V
CC
A
B
V
BB
V
BB
9
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65LVDS18DRFT
SN65LVDS19DRFT
SN65LVP18DRFT
SN65LVP19DRFT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
DRF
DRF
DRF
DRF
8
8
8
8
250
250
250
250
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
ER
ET
EP
ES
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Sep-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LVDS18DRFT
SN65LVDS19DRFT
SN65LVP18DRFT
SN65LVP19DRFT
WSON
WSON
WSON
WSON
DRF
DRF
DRF
DRF
8
8
8
8
250
250
250
250
330.0
330.0
330.0
330.0
8.8
8.8
8.8
8.8
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.0
1.0
1.0
1.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Sep-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65LVDS18DRFT
SN65LVDS19DRFT
SN65LVP18DRFT
SN65LVP19DRFT
WSON
WSON
WSON
WSON
DRF
DRF
DRF
DRF
8
8
8
8
250
250
250
250
337.0
337.0
337.0
337.0
343.0
343.0
343.0
343.0
29.0
29.0
29.0
29.0
Pack Materials-Page 2
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