SN65LVDS250 [TI]
LVDS 4x4 CROSSPOINT SWITCH; LVDS 4×4交叉点开关
| 型号： | SN65LVDS250 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LVDS 4x4 CROSSPOINT SWITCH |
| 文件： | 总16页 (文件大小：356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS250
SN65LVDT250
www.ti.com
SLLS594B–MARCH 2004–REVISED OCTOBER 2004
LVDS 4x4 CROSSPOINT SWITCH
FEATURES
SN65LVDS250DBT ( Marked as LVDS250)
SN65LVDT250DBT ( Marked as LVDT250)
(TOP VIEW)
•
Greater Than 2.0 Gbps Operation
•
Nonblocking Architecture Allows Each
Output to be Connected to Any Input
S10
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
1
VCC
GND
1Y
S11
1A
2
•
•
Pk-Pk Jitter:
3
– 60 ps Typical at 2.0 Gbps
– 110 ps Typical at 2.5 Gbps
1B
4
1Z
S20
S21
2A
5
1DE
2Y
2Z
2DE
GND
VCC
GND
3Y
6
Compatible With ANSI TIA/EIA-644-A LVDS
Standard
7
2B
8
GND
VCC
GND
3A
9
•
•
•
•
Available Packaging 38-Pin TSSOP
10
11
12
13
14
15
16
17
18
19
25 mV of Input Voltage Threshold Hysteresis
Propagation Delay Times: 800 ps Typical
3B
3Z
3DE
4Y
Inputs Electrically Compatible With LVPECL,
CML and LVDS Signal Levels
S30
S31
4A
4B
S40
S41
•
•
•
Operates From a Single 3.3-V Supply
Low Power: 110 mA Typical
4Z
4DE
GND
VCC
Integrated 110-Ω Line Termination Resistors
Available With SN65LVDT250
APPLICATIONS
EYE PATTERN
•
•
•
•
Clock Buffering/Clock Muxing
Wireless Base Stations
High-Speed Network Routing
Telecom/Datacom
DESCRIPTION
The SN65LVDS250 and SN65LVDT250 are 4x4
nonblocking crosspoint switches in a flow-through
pin-out allowing for ease in PCB layout. Low-voltage
differential signaling (LVDS) is used to achieve a
high-speed data throughput while using low power.
Each of the output drivers includes a 4:1 multiplexer
to allow any input to be routed to any output. Internal
signal paths are fully differential to achieve the high
signaling speeds while maintaining low signal skews.
The SN65LVDT250 incorporates 110-Ω termination
resistors for those applications where board space is
a premium.
76 − ps/div
V
= 1.2 V
IC
|V | = 200 mV
ID
2 Gbps
23
Input = PRBS 2 −1
= 3.3 V
V
CC
The SN65LVDS250 and SN65LVDT250 are
characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LVDS250
SN65LVDT250
www.ti.com
SLLS594B–MARCH 2004–REVISED OCTOBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
LOGIC DIAGRAM
8
S10 - S41
1DE
1A
1B
1Y
1Z
2DE
2A
2B
2Y
2Z
4X4
MUX
3DE
3A
3B
3Y
3Z
4DE
4Y
4A
4B
4Z
Integrated Termination on LVDT Only
2
SN65LVDS250
SN65LVDT250
www.ti.com
SLLS594B–MARCH 2004–REVISED OCTOBER 2004
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
INPUT LVDS250
V
CC
V
CC
A
B
7 V
7 V
V
CC
V
CC
300 kΩ
S10, S41
400 Ω
400 Ω
DE
300 kΩ
7 V
7 V
OUTPUT LVDS250
V
CC
V
CC
V
CC
Y
Z
7 V
7 V
3
SN65LVDS250
SN65LVDT250
www.ti.com
SLLS594B–MARCH 2004–REVISED OCTOBER 2004
Table 1. CROSSPOINT LOGIC TABLES
OUTPUT CHANNEL 1
OUTPUT CHANNEL 2
OUTPUT CHANNEL 3
CONTROL INPUT
PINS
OUTPUT CHANNEL 4
CONTROL
PINS
INPUT
SELECTED
CONTROL
PINS
INPUT
SELECTED
CONTROL
PINS
INPUT
SELECTED
SELECTED
3Y/3Z
S10
S11
0
1Y/1Z
1A/1B
2A/2B
3A/3B
4A/4B
S20
S21
0
2Y/2Z
1A/1B
2A/2B
3A/3B
4A/4B
S30
0
S31
0
S40
S41
0
4Y/4Z
1A/1B
2A/2B
3A/3B
4A/4B
0
0
1
1
0
0
1
1
1A/1B
0
0
1
1
1
1
0
1
2A/2B
1
0
0
1
0
3A/3B
0
1
1
1
1
4A/4B
1
PACKAGE DISSIPATION RATINGS
CIRCUIT BOARD
TA≤ 25°C
POWER RATING
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
MODEL
TSSOP (DBT)
TSSOP (DBT)
Low-K(2)
High-K(3)
1038 mW
9.0 mW/°C
496 mW
1772 mW
15.4 mW/°C
847 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounded and with no air flow.
(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-6
(3) In accordance with the High-K thermal metric definitions of EIA/JESD51-6
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
VALUE
40.3
8.5
UNITS
ΘJB
ΘJC
Junction-to-board thermal resistance
Junction-to-case thermal resistance
°C/W
VCC = 3.3 V, TA = 25°C, 1 GHz
VCC = 3.6 V, TA = 85°C, 1 GHz
356
mW
mW
PD
Device power dissipation
522
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNITS
-0.5 V to 4 V
-0.5 V to 4 V
-0.5 V to 4 V
1 V
Supply voltage range, VCC
S, DE
A, B
Voltage range(2)
|VA - VB| (LVDT only)
Y, Z
-0.5 V to 4 V
±3 kV
Human body model(3)
Charged-device model(4)
All pins
All pins
Electrostatic discharge
±500 V
Continuous power dissipation
See Dissipation Rating Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
4
SN65LVDS250
SN65LVDT250
www.ti.com
SLLS594B–MARCH 2004–REVISED OCTOBER 2004
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
VCC
VIH
VIL
Supply voltage
3
2
3.3
3.6
VCC
0.8
1
V
V
High-level input voltage
Low-level input voltage
S10-S41, 1DE-4DE
S10-S41, 1DE-4DE
LVDS
0
V
0.1
0.1
0
V
|VID
|
Magnitude of differential input voltage
LVDT
0.8
3.3
140
85
V
Input voltage (any combination of common-mode or input signals)
Junction temperature
V
TJ
°C
°C
(1)
TA
Operating free-air temperature
-40
(1) Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
TIMING SPECIFICATIONS
PARAMETER
MIN NOM
MAX UNIT
tSET
Input to select setup time
Input to select hold time
0.6
0.2
1.2
ns
ns
tHOLD
See Figure 7
tSWITCH Select to switch output
1.6 ns
INPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted(1)
PARAMETER
TEST CONDITIONS
See Figure 1
MIN TYP(1)
MAX UNIT
VIT+
Positive-going differential input voltage threshold
100
mV
mV
mV
VIT-
Negative-going differential input voltage threshold See Figure 1
Differential input voltage hysteresis
1DE-4DE
-100
VID(HYS)
25
-10
IIH
High-level input current
VIH = 2 V
µA
S10-S41
1DE-4DE
S10-S41
20
-10
-20
IIL
II
Low-level input current
VIL = 0.8 V
µA
µA
20
20
VI = 0 V or 3.3 V, second input at 1.2 V
(other input open for LVDT)
Input current (A or B inputs)
VCC≤ 1.5 V, VI = 0 V or 3.3 V, second
II(OFF)
IIO
Input current (A or B inputs)
input at 1.2 V(other input open for
LVDT)
-20
-6
20
µA
µA
Input offset current (|IIA - IIB|) (LVDS)
Termination resistance (LVDT)
VIA = VIB, 0 ≤ VIA≤ 3.3 V
6
VID = 300 mV, VIC = 0 V to 3.3 V
90
110
110
2.5
132
RT
CI
Ω
VID = 300 mV, VIC = 0 V to 3.3 V,
VCC = 1.5 V
Termination resistance (LVDT with power-off)
Differential input capacitance
90
132
pF
(1) All typical values are at 25°C and with a 3.3 V supply.
5
SN65LVDS250
SN65LVDT250
www.ti.com
SLLS594B–MARCH 2004–REVISED OCTOBER 2004
OUTPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
247
TYP
MAX UNIT
|VOD
|
Differential output voltage magnitude
350
454
50
mV
mV
V
See Figure 2
VID = ±100 mV
∆|VOD
|
Change in differential output voltage magnitude between logic states
Steady-state common-mode output voltage
-50
VOC(SS)
1.125
1.375
Change in steady-state common-mode output voltage between logic
states
∆VOC(SS)
See Figure 3
-50
50
mV
VOC(PP)
ICC
Peak-to-peak common-mode output voltage
Supply current
50
150
145
27
mV
mA
mA
mA
µA
RL=100 Ω
110
IOS
Short-circuit output current
VOY or VOZ = 0 V
VOD = 0 V
-27
-12
IOSD
IOZ
Differential short circuit output current
High-impedance output current
Differential output capacitance
12
VO = 0 V or VCC
±1
CO
2
pF
SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time (20%-80%)
Differential output signal fall time (20%-80%)
Pulse skew (|tPHL - tPLH|)(1)
Channel-to-channel output skew(2)
Part-to-part skew(3)
Period jitter, rms (1 standard deviation)(4)
Cycle-to-cycle jitter (peak)(5)
Peak-to-peak jitteR(6)
700
700
800 1200
800 1200
See Figure 4
ps
200
200
0
245
245
50
tf
tsk(p)
tsk(o)
tsk(pp)
tjit(per)
tjit(cc)
tjit(pp)
tjit(det)
tPHZ
tPLZ
tPZH
tPZL
ps
ps
ps
ps
ps
ps
ps
175
300
3
See Figure 6
See Figure 6
See Figure 6
See Figure 6
1
8
17
60
48
110
65
Deterministic jitter, peak-to-peak(7)
Propagation delay, high-level-to-high-impedance output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance -to-high-level output
Propagation delay, high-impedance-to-low-level output
6
6
See Figure 5
ns
300
300
(1) tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.
(2) tsk(o) is the maximum delay time difference between drivers over temperature, VCC, and process.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(4) Input voltage = VID = 200 mV, 50% duty cycle at 1.0 GHz, tr = tf= 50 ps (20% to 80%), measured over 1000 samples.
(5) Input voltage = VID = 200 mV, 50% duty cycle at 1.0 GHz, tr = tf= 50 ps (20% to 80%).
(6) Input voltage = VID = 200 mV, 223-1 PRBS pattern at 2.0 Gbps, tr = tf = 50 ps (20% to 80%), measured over 200k samples.
(7) Input voltage = VID = 200 mV, 27-1 PRBS pattern at 2.0 Gbps, tr= tf = 50 ps (20% to 80%).
6
SN65LVDS250
SN65LVDT250
www.ti.com
SLLS594B–MARCH 2004–REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
I
IA
A
B
Y
Z
V
ID
V
OD
V
IA
V
OY
V
IC
V
OC
V
+V
V +V
OY
2
IA IB
OZ
V
IB
V
OZ
I
IB
2
Figure 1. Voltage and Current Definitions
3.75 kΩ
Y
+
0 V ≤ V
≤ 2.4 V
V
OD
100 Ω
(test)
_
Z
3.75 kΩ
Figure 2. Differential Output Voltage (VOD) Test Circuit
A
≈1.4 V
≈1 V
49.9 Ω ±1%
A
B
Y
B
V
ID
V
V
OC(SS)
OC(PP)
V
OC
Z
1 pF
V
49.9 Ω ±1%
OC
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse-repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns; RL = 100Ω ; CL includes instrumentation and fixture capacitance within
0,06 mm of the DUT; the measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 300
MHz.
Figure 3. Test Circuit and Definitions fot the Driver Common-Mode Output Voltage
V
1.4 V
1 V
A
B
IA
IB
Y
1 pF
V
OY
V
OD
V
ID
100 Ω
V
V
IA
Z
V
IB
V
OZ
0.4 V
0 V
V
ID
-0.4 V
t
t
PLH
PHL
0 V
80%
Differential
V
OY
- V
OZ
20%
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 0.25 ns, pulse-repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of
the DUT.
Figure 4. Timing Test Circuit and Waveforms
7
SN65LVDS250
SN65LVDT250
www.ti.com
SLLS594B–MARCH 2004–REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION (continued)
49.9 Ω ±1%
Y
1 V or 1.4 V
1 pF
V
OY
49.9 Ω ±1%
1.2 V
DE
Z
1.2 V
V
OZ
3 V
DE
1.5 V
0 V
1.4 V
V
or V
1.25 V
1.2 V
OY
OZ
OY
t
t
PZH
PHZ
1.2 V
1.15 V
1 V
V
or V
OZ
t
t
PZL
PLZ
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse-repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the DUT.
Figure 5. Enable and Disable Time Circuit and Definitions
V
A
0 V
Clock Input
0 V
Ideal Output
V
B
V
Y
- V
Z
1/fo
1/fo
Period Jitter
Cycle-to-Cycle Jitter
Actual Output
0 V
Actual Output
V
0 V
- V
V
Y
- V
Z
Y
Z
t
t
t
c(n)
c(n)
c(n +1)
t
= | t
- t
|
t
= | t
- 1/fo |
jit(cc)
c(n) c(n + 1)
jit(pp)
c(n)
Peak-to-Peak Jitter
V
A
V
Y
PRBS Input
0 V
0 V
PRBS Output
V
B
V
Z
t
jit(pp)
A. All input pulses are supplied by an Agilent 81250 Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software.
Figure 6. Driver Jitter Measurement Waveforms
8
SN65LVDS250
SN65LVDT250
www.ti.com
SLLS594B–MARCH 2004–REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION (continued)
A/B
A/B
S
t
t
HOLD
SET
OUT
DE
Y/Z
Y/Z
t
SWITCH
A/B
A/B
S
t
t
HOLD
SET
Y/Z
Y/Z
OUT
t
SWITCH
DE
A. tSET and tHOLD times specify that data must be in a stable state before and after mux control switches.
Figure 7. Input to Select for Both Rising and Falling Edge Setup and Hold Times
9
SN65LVDS250
SN65LVDT250
www.ti.com
SLLS594B–MARCH 2004–REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
PROPAGATION DELAY TIME
vs
COMMON-MODE INPUT VOLTAGE
FREQUENCY
118
1000
1000
940
880
820
760
700
V
T
V
= 3.3 V,
= 25°C,
= 1.2 V,
V
T
= 3.3 V,
CC
CC
= 25°C,
V
V
= 3.3 V,
CC
= 1.2 V,
A
A
IC
|V | = 200 mV,
ID
f = 1 MHz
IC
|V | = 200 mV,
ID
f = 1 MHz
|V | = 200 mV
ID
113
900
800
700
600
t
PHL
108
103
98
t
PLH
t
PHL
t
PLH
3
0
200
400
600
800
1000 1200
0
0.5
1
1.5
2
2.5
3.5
−45 −25
−5
15
35
55
75
95
2200
1100
f − Frequency − MHz
V
− Common-Mode Input Voltage − V
T
A
− Free-Air Temperature − °C
ic
Figure 8.
Figure 9.
Figure 10.
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
vs
vs
vs
FREQUENCY
DATA RATE
FREQUENCY
30
25
20
15
10
5
140
120
100
80
30
25
20
15
10
5
V
T
V
= 3.3 V,
= 25°C,
= 400 mV,
V
T
V
= 3.3 V,
CC
CC
V
= 3.3 V,
CC
T = 25°C,
A
= 25°C
A
A
= 400 mV,
IC
IC
V
= 1.2 V,
IC
23
Input = PRBS 2 −1
Input = Clock
Input = Clock
V
= 800 mV
ID
V
= 400 mV
ID
V
= 800 mV
ID
V
= 800 mV
ID
V
= 200 mV
ID
V
= 400 mV
60
ID
V
= 400 mV
ID
40
V
= 200 mV
V
= 200 mV
ID
ID
20
0
0
0
0
220
440
660
880
1100
0
220
440
660
880
1100
0
440
880
1320
1760
f − Frequency − MHz
f − Frequency − MHz
Data Rate − Mbps
Figure 11.
Figure 12.
Figure 13.
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
vs
vs
vs
DATA RATE
FREQUENCY
DATA RATE
140
120
100
80
30
25
20
15
10
5
140
120
100
80
V
T
V
= 3.3 V,
= 25°C,
= 1.2 V,
V
= 3.3 V,
CC
CC
V
= 3.3 V,
CC
= 25°C,
T
= 25°C,
= 2.9 V,
A
A
T
A
V
IC
Input = PRBS 2 −1
IC
V
= 2.9 V,
IC
Input = Clock
23
23
Input = PRBS 2 −1
V
= 400 mV
ID
V
= 200 mV
ID
V
= 800 mV
V
= 800 mV
ID
ID
V
= 400 mV
ID
60
60
V
= 800 mV
ID
V
= 200 mV
ID
40
40
V
= 200 mV
ID
20
0
20
V
= 400 mV
880
ID
0
0
0
440
880
1320
1760
2200
0
440
1320
1760 2200
0
220
440
660
880
Data Rate − Mbps
f − Frequency − MHz
Data Rate − Mbps
Figure 14.
Figure 15.
Figure 16.
10
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SN65LVDT250
www.ti.com
SLLS594B–MARCH 2004–REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
PEAK-TO-PEAK JITTER
vs
FREE-AIR TEMPERATURE
PEAK-TO-PEAK JITTER
vs
DATA RATE
90
120
100
80
V
V
= 3.3 V,
CC
= 1.2 V,
V
V
= 3.3 V,
CC
= 1.2 V,
IC
IC
|V | = 200 mV,
23
Input = PRBS 2 −1
ID
|V | = 200 mV,
23
Input = 2 Gbps PRBS 2 −1
82
74
66
58
50
ID
60
40
20
0
−40 −20
0
20
40
60
80 100
0
560
1120
1680
2240
2800
T
A
− Free-Air Temperature − °C
Data Rate − Mbps
Figure 17.
Figure 18.
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREQUENCY
EYE PATTERN
400
350
300
250
40
V
V
= 3.3 V,
CC
= 1.2 V,
IC
35
30
25
|V | = 200 mV,
ID
T
= 25°C,
A
Input = Clock
200
150
100
20
15
10
50
0
5
0
Added Random Jitter
0
500
1000
1500
2000
2500
f − Frequency − MHz
60 − ps/div
V
= 1.2 V, |V | = 200 mV, 2.5 Gbps,
ID
IC
23
Input = PRBS 2 −1, V = 3.3 V
CC
Figure 19.
Figure 20.
11
SN65LVDS250
SN65LVDT250
www.ti.com
SLLS594B–MARCH 2004–REVISED OCTOBER 2004
APPLICATION INFORMATION
CONFIGURATION EXAMPLES
S10
0
S30
1
S11
0
S31
0
S20
0
S40
1
S21
S10
0
S30
0
S11
0
S31
0
S20
0
S40
0
S21
0
S41
0
1
S41
1
1Y
1Z
1A
1B
1Y
1A
1B
1Z
2Y
2Z
2A
2B
2Y
2Z
3Y
3Z
3A
3B
3Y
3Z
4Y
4Z
4Y
4Z
4A
4B
S10
0
S11
0
S20
0
S21
0
S10
1
S11
1
S20
1
S21
1
S30
1
S31
0
S40
1
S41
0
S30
0
S31
0
S40
0
S41
0
1A
1B
1Y
1Z
1A
1B
1Y
1Z
2Y
2Z
2Y
2Z
3Y
3Z
3A
3B
3Y
3Z
4Y
4Z
4A
4B
4Y
4Z
12
SN65LVDS250
SN65LVDT250
www.ti.com
SLLS594B–MARCH 2004–REVISED OCTOBER 2004
APPLICATION INFORMATION (continued)
TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.)
50 Ω
3.3 V or 5 V
3.3 V
SN65LVDS250
A
B
ECL
50 Ω
50 Ω
50 Ω
V
TT
= V -2 V
CC
V
TT
Figure 21. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
3.3 V
50 Ω
50 Ω
50 Ω
3.3 V
3.3 V
SN65LVDS250
A
B
CML
50 Ω
3.3 V
Figure 22. Current-Mode Logic (CML)
3.3 V
3.3 V
SN65LVDS250
50 Ω
A
B
ECL
50 Ω
1.1 kΩ
3.3 V
1.5 kΩ
V
TT
= V -2 V
CC
V
TT
Figure 23. Single-Ended (LVPECL)
50 Ω
3.3 V or 5 V
LVDS
3.3 V
SN65LVDS250
A
B
100 Ω
50 Ω
Figure 24. Low-Voltage Differential Signaling (LVDS)
13
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SM8
SM8
SM8
SM8
Drawing
SN65LVDS250DBT
SN65LVDS250DBTR
SN65LVDT250DBT
SN65LVDT250DBTR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DBT
38
38
38
38
50
2000
50
None
None
None
None
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
DBT
DBT
DBT
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS019D – FEBRUARY 1996 – REVISED FEBRUARY 2002
DBT (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,27
0,17
M
0,50
30
0,08
16
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
15
0°–ā8°
0,75
0,50
A
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
20
24
28
30
38
44
50
DIM
5,10
4.90
6,60
6,40
7,90
7,70
7,90
7,70
9,80
9,60
11,10
10,90
12,60
12,40
A MAX
A MIN
4073252/E 02/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-153
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