SN65LVDS302ZXH_技术文档

SN65LVDS302

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SLLS733E – JUNE 2006 – REVISED OCTOBER 2020

SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver

1 Features

3 Description

•

Serial interface technology

Compatible with FlatLink^™3G such as

SN65LVDS301

The

SN65LVDS302

receiver

de-serializes

FlatLink™3G compliant serial input data to 27 parallel

data outputs. The SN65LVDS302 receiver contains

one shift register to load 30 bits from 1, 2 or 3 serial

inputs and latches the 24 pixel bits and 3 control bits

out to the parallel CMOS outputs after checking the

parity bit. If the parity check confirms correct parity,

the Channel Parity Error (CPE) output remains low. If

a parity error is detected, the CPE output generates a

high pulse while the data output bus disregards the

newly-received pixel. Instead, the last data word is

held on the output bus for another clock cycle.

•

Supports video interfaces up to 24-bit RGB data

and 3 control bits received over 1, 2 or 3 SubLVDS

differential lines

SubLVDS differential voltage levels

Up to 1.755-Gbps Data Throughput

Three operating modes to conserve power

– Active mode QVGA: 17 mW

– Typical shutdown: 0.7 μW

•

– Typical standby mode: 27 μW Typical

Bus-swap function for PCB-layout flexibility

ESD rating > 4 kV (HBM)

Pixel clock range of 4 MHz to 65 MHz

Failsafe on all CMOS inputs

Device Information ⁽¹⁾

•

PART NUMBER

PACKAGE

BODY SIZE (NOM)

SN65LVDS302

nFBGA (80)

5.00 mm × 5.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Packaged in 5-mm × 5-mm nFBGA with 0.5-mm

ball pitch

•

Very low EMI meets SAE J1752/3 'Kh'-spec

2 Applications

•

Wearables (non-medical)

Tablets

Mobile phones

Portable electronics

Gaming

Retail automation & payment

Building automation

LCD

VDS314

L

or

VDS302

L

Application

Processor

with CMOS

Video Interface

LVDS301

or

LVDS311

Implementation Example

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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SN65LVDS302

SLLS733E – JUNE 2006 – REVISED OCTOBER 2020

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 ESD Ratings............................................................... 6

6.3 Recommended Operating Conditions.........................6

6.4 Thermal Information....................................................7

6.5 Electrical Characteristics.............................................8

6.6 Input Electrical Characteristics....................................9

6.7 Output Electrical Characteristics.................................9

6.8 Timing Requirements................................................10

6.9 Switching Characteristics..........................................10

6.10 Device Power Dissipation....................................... 11

7 Parameter Measurement Information..........................16

7.1 Power Consumption Tests........................................ 20

7.2 Typical IC Power Consumption Test Pattern.............20

7.3 Maximum Power Consumption Test Pattern.............21

7.4 Output Skew Pulse Position and Jitter

Performance................................................................22

8 Detailed Description......................................................25

8.1 Overview...................................................................25

8.2 Functional Block Diagram.........................................26

8.3 Feature Description...................................................27

8.4 Device Functional Modes..........................................28

9 Application and Implementation..................................32

9.1 Application Information............................................. 32

9.2 Typical Applications.................................................. 36

10 Power Supply Recommendations..............................39

11 Layout...........................................................................40

11.1 Layout Guidelines................................................... 40

12 Device and Documentation Support..........................41

12.1 Community Resource............................................. 41

12.2 Trademarks.............................................................41

13 Mechanical, Packaging, and Orderable

Information.................................................................... 42

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (May 2016) to Revision E (October 2020)

Page

•

NOTE: The device in the MicroStar Jr. BGA packaging were redesigned using a laminate nFBGA package.

This nFBGA package offers datasheet-equivalent electrical performance. It is also footprint equivalent to the

MicroStar Jr. BGA. The new package designator in place of the discontinued package designator will be

updated throughout the datasheet......................................................................................................................1

Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 1

Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 3

Changed u*jr ZQE to nFBGA ZXH, updated thermal information.......................................................................7

Correct SN65LVDS822 to SN65LVDS302........................................................................................................39

•

Changes from Revision C (August 2012) to Revision D (May 2016)

Page

•

Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and

Implementation section, Power Supply Recommendations section, Layout section, Device and

Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1

2

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5 Pin Configuration and Functions

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

GND

R6/B1

R4/B3

R2/B5

R0/B7

G6/G1

G4/G3

G2/G5

GND

R7/B0

LS0

R5/B2

R3/B4

R1/B6

G7/G0

GND

G5/G2

G3/G4

GND

G1/G6

B7/R0

B5/R2

B3/R4

B1/R6

F/S

G0/G7

B6/R1

B4/R3

B2/R5

B0/R7

PCLK

HS

V

ꢀ

V

ꢀ

V

ꢀ

DD

D2+

LS1

GND

V

ꢀ

DD

D2–

GND

ꢀ

PLLD

D1+

V

ꢀ

DDPLLD

G

H

J

D1–

GND

ꢀ

LVDS

CPOL

V

ꢀ

V

ꢀ

GND

ꢀ

V

ꢀ

GND

ꢀ

LVDS

GND

VS

DDLVDS

SWAP

DDPLLA

CLK+

PLLA

DDLVDS

D0+

GND

ꢀ

CLK–

D0–

RXEN

DE

CPE

LVDS

Figure 5-1. ZXH Package 80-Pin nFBGA Top View

Table 5-1. Pin Functions

NO.

DESCRIPTION

NAME

CMOS

I/O

B0 to B7

G0 to G7

R0 to R7

See ⁽¹⁾

CMOS Out Blue pixel data

CMOS Out Green pixel data

CMOS Out Red pixel data

Channel parity error

This output indicates the detection of a parity error by generating an

output high-pulse for half of a PCLK clock cycle; this allows counting

parity errors with a simple counter.

CPE

J9

CMOS Out

0: no error

high-pulse: bit error detected

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Table 5-1. Pin Functions (continued)

DESCRIPTION

NAME

NO.

H1

J8

I/O

Output clock polarity selection:

0: rising edge clocking

CPOL

CMOS In

1: falling edge clocking

DE

CMOS Out Data Enable

CMOS bus rise time select:

F/S

G8

CMOS In

1: fast output rise time

0: slow output rise time

HS

H9

C1

D2

G9

CMOS Out Horizontal sync

CMOS In Link select: determines active SubLVDS Data Links and PLL Range) (see Table 8-1)

LS0

LS1

PCLK

CMOS Out Output Pixel Clock; rising or falling clock polarity is selected by control input CPOL

Disables the CMOS Drivers and turns off the PLL, putting device in

shutdown mode.⁽²⁾

RXEN

J7

CMOS In

1: Receiver enabled

0: Receiver disabled (shutdown)

Bus swap: swaps the bus pins to allow device placement on top or

bottom of PCB. See pinout drawing and Table 5-2 for pin

assignments.

SWAP

J2

CMOS In

0: data output from R7 to B0

1: data output from B0 to R7

CMOS Out Vertical sync

VS

H8

SUBLVDS

CLK+,

CLK–

J3, J4

J5, J6

SubLVDS In SubLVDS input pixel clock (polarity is fixed)

D0+, D0–

SubLVDS In SubLVDS data link (active during normal operation)

SubLVDS data link (active during normal operation when LS0 = high and LS1 = low, or

SubLVDS In LS0 = low and LS1 = high; high impedance if LS0 = LS1 = low); input can be left open

if unused.

D1+, D1–

F1, G1

D1, E1

SubLVDS data link (active during normal operation when LS0 = low and LS1 = high,

SubLVDS In

D2+, D2–

POWER SUPPLY

V_DD

high-impedance when LS1 = low); input can be left open if unused.

C2, C4, C6,

D7 to G7

Power Supply Supply voltage

V_DDLVDS

V_DDPLLA

V_DDPLLD

H2, H5

H3

Power Supply SubLVDS I/O supply voltage

Power Supply PLL analog supply voltage

Power Supply PLL digital supply voltage

F2

A1, A9, C5, C7,

D3 to D6, E3 to E6,

F3 to F6,

GND

Ground

Supply ground

G3 to G6, H7

GND_LVDS

GND_PLLA

G2, H6, J1

H4

Ground

SubLVDS ground

PLL analog ground

4

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Table 5-1. Pin Functions (continued)

NO.

E2

DESCRIPTION

NAME

I/O

GND_PLLD

Ground

PLL digital ground

(1) Pin assignment depends on SWAP pin setting. Swappable pins are detailed in Table 5-2.

(2) RXEN input incorporates glitch suppression logic to avoid unwanted switching. The input must be pulled low for longer than 10 µs

continuously to force the receiver to enter Shutdown. The input must be pulled high for at least 10 μs continuously to activate the

receiver. An input pulse shorter than 5 µs is interpreted as glitch and becomes ignored. At power up, the receiver is enabled

immediately if RXEN = H and disabled if RXEN = L.

Table 5-2. Swappable Pins

SIGNAL SWAP⁽¹⁾

F9

B1

F8

A2

E9

B2

E8

A3

D9

B3

D8

A4

C9

B4

C8

A5

B9

B5

B8

A6

A8

B6

B7

A7

B7

B6

A8

A6

B8

B5

B9

SIGNAL SWAP⁽¹⁾

A5

C8

B4

C9

A4

D8

B3

D9

A3

E8

B2

E9

A2

F8

B1

F9

L

B0

G0

R0

H

L

B1

G1

R1

H

L

B2

G2

R2

H

L

B3

G3

R3

H

L

B4

G4

R4

H

L

B5

G5

R5

H

L

B6

G6

R6

H

L

B7

G7

R7

H

(1) The SWAP pin is either set to GND (L) or V_DD(H).

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–0.5

±5

MAX

2.175

UNIT

Supply voltage range

V_DD⁽²⁾, V_DDPLLA, V_DDPLLD, V_DDLVDS

V

When VDDx > 0 V

When VDDx ≤ 0 V

2.175

Voltage range at any input or output terminal

V

V_DD+ 2.175

Ouput current, I_O

mA

°C

Storage temperature, T_stg

–55

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to the GND terminals

6.2 ESD Ratings

VALUE

±4000

±1500

±200

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Machine model

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

see ⁽¹⁾

MIN NOM

MAX UNIT

V_DD

V_DDPLLA

Supply voltages

1.65

1.8

1.95

V

V_DDPLLD

V_DDLVDS

Test set-up see Figure 7-1

f_CLK≤ 50 MHz; f(noise) = 1 Hz to 2 GHz

f_CLK> 50 MHz; f(noise) = 1 Hz to 1 MHz

f_CLK> 50 MHz; f(noise) > 1 MHz

100

40

Supply voltage noise magnitude

50 MHz (all supplies)

V_DDn(PP)

mV

°C

T_A

Operating free-air temperature

–40

85

CLK+ and CLK–

1-Channel receive mode, see Figure 8-4

2-Channel receive mode, see Figure 8-5

3-Channel receive mode, see Figure 8-6

Standby mode⁽²⁾, see Figure 7-10

4

8

15

30 MHz

65

f_CLK±

Input Pixel clock frequency

20

500 kHz

65%

t_DUTCLK

CLK Input Duty Cycle

35%

6

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see ⁽¹⁾

MIN NOM

MAX UNIT

D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK–

|V_D0+– V_D0–|, |V_D1+– V_D1–|, |V_D2+– V_D2–|,

|V_CLK+– V_CLK–| during normal operation

|V_ID|

V_ICM

Magnitude of differential input voltage

Input voltage common mode range

70

200 mV

Receive or Acquire mode

Stand-by mode

0.6

1.2

V

0.9 × V_DDLVDS

V_ICM(n)– V_ICM(m)with

n = {D0, D1, D2, or CLK} and

m = {D0, D1, D2, or CLK}

Input voltage common mode variation

between all SubLVDS inputs

ΔV_ICM

–100

100 mV

10%

V_ID(n)– V_ID(m)with

n = {D0, D1, D2, or CLK} and

m = {D0, D1, D2, or CLK}

Differential input voltage amplitude

variation between all SubLVDS inputs

ΔV_ID

t_R/F

–10%

Input rise and fall time

RXEN at VDD; see figure 10

800

100

ps

t_R(n)– t_R(m)and t_F(n)– t_F(m)with

n = {D0, D1, D2, or CLK} and

m = {D0, D1, D2, or CLK}

Input rise or fall time mismatch

between all SubLVDS inputs

Δt_R/F

–100

LS0, LS1, CPOL, SWAP, RXEN, F/S

V_ICMOSHHigh-level input voltage

V_ICMOSLLow-level input voltage

0.7 × V_DD

V_DD

V

0

0.3 × V_DD

t_inRXEN

R[7:0], G[7:0], B[7:0], VS, HS, PCLK, CPE

C_LOutput load capacitance

RXEN input pulse duration

10

μs

10

pF

(1) Unused single-ended inputs must be held high or low to prevent them from floating.

(2) PCLK input frequencies lower than 500 kHz forces the SN65LVDS302 into standby mode. Input frequencies from 500 kHz to 3 MHz

may or may not activate the SN65LVDS302. Input frequencies beyond 3 MHz activate the SN65LVDS302. TI recommends against

input frequencies from 500 kHz to 4 MHz, which can cause PLL malfunction.

6.4 Thermal Information

SN65LVDS302

ZXH

THERMAL METRIC⁽¹⁾

UNIT

(nFBGA)

80 PINS

41.5

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

29.4

23.8

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.5

ψ_JB

23.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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6.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

9.8

MAX UNIT

f_PCLK= 4 MHz

f_PCLK= 6 MHz

f_PCLK= 15 MHz

f_PCLK= 4 MHz

f_PCLK= 6 MHz

f_PCLK= 15 MHz

f_PCLK= 8 MHz

f_PCLK= 22 MHz

f_PCLK= 30 MHz

f_PCLK= 8 MHz

f_PCLK= 22 MHz

f_PCLK= 30 MHz

f_PCLK= 20 MHz

14

Alternating 1010 Test pattern (see Table 7-5). All CMOS outputs

terminated with 10 pF, F/S and RXEN at V_DD. V_IH= V_DD, V_IL= 0 V,

V_DD= V_DDPLLA= V_DDPLLD= V_DDLVDS

11.7

19.3

4.7

15.9

25

mA

1ChM

Typical power test pattern (see Table 7-2). V_ID= 70 mV. All CMOS

outputs terminated with 10 pF, F/S at GND, and RXEN at V_DD

V_IH= V_DD, V_IL= 0 V, V_DD= V_DDPLLA= V_DDPLLD= V_DDLVDS

.

6

13.2

14.3

25

19.4

33

Alternating 1010 Test pattern (see Table 7-5). All CMOS outputs

terminated with 10 pF, F/S and RXEN at V_DD. V_IH= V_DD, V_IL= 0 V,

V_DD= V_DDPLLA= V_DDPLLD= V_DDLVDS

26.8

6.4

37

2ChM

3ChM

RMS supply

current

Typical power test pattern (see Table 7-3). V_ID= 70 mV. All CMOS

outputs terminated with 10 pF, F/S at GND, and RXEN at V_DD

V_IH= V_DD, V_IL= 0 V, V_DD= V_DDPLLA= V_DDPLLD= V_DDLVDS

I_DD

.

13.7

18.3

17.1

Alternating 1010 Test pattern (see Table 7-5). All CMOS outputs

terminated with 10 pF, F/S and RXEN at V_DD. V_IH= V_DD, V_IL= 0 V,

V_DD= V_DDPLLA= V_DDPLLD= V_DDLVDS

27

68

mA

f_PCLK= 65 MHz

f_PCLK= 20 MHz

f_PCLK= 65 MHz

60.8

8.6

Typical power test pattern (see Table 7-4). V_ID= 70 mV. All CMOS

outputs terminated with 10 pF, F/S at GND, and RXEN at V_DD

V_IH= V_DD, V_IL= 0 V, V_DD= V_DDPLLA= V_DDPLLD= V_DDLVDS

.

22.2

Standby mode;

RXEN = V_IH

15

100

10

μA

CLK and D[0:2] inputs are left open. All control inputs held static high or low.

All CMOS outputs terminated with 10 pF. V_IH= V_DD, V_IL= 0 V,

V_DD= V_DDPLLA= V_DDPLLD= V_DDLVDS

Shutdown mode;

RXEN = V_IL

0.4

(1) All typical values are at 25°C and with 1.8-V supply unless otherwise noted.

8

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6.6 Input Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP⁽¹⁾

MAX UNIT

D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK–

Input voltage common mode threshold to switch

V_thstbybetween receive and acquire mode and standby

mode

RXEN at V_DD

1.3

0.9 × V_DDLVDS

V

V_D0+– V_D0–, V_D1+– V_D1–

V_D2+– V_D2–, V_CLK+– V_CLK–

,

V_THL

V_THH

Low-level differential input voltage threshold

High-level differential input voltage threshold

–40

mV

V_D0+– V_D0–, V_D1+– V_D1–

,

40 mV

V_D2+– V_D2–, V_CLK+– V_CLK–

V_DD= 1.95 V, V_I+= V_I–,

V_I= 0.4 V and V_I= 1.5 V

I_I+, I_I–Input leakage current

75

μA

I_IOFF

R_ID

Power-off input current

V_DD= GND; V_I= 1.5 V

–75

122

μA

Ω

Differential input termination resistor value

78

21

100

1

Measured between input

terminal and GND

C_IN

Input capacitance

pF

Within one signal pair

Between all signals

0.2

1

ΔC_IN

Input capacitance variation

pF

kΩ

R_BBDCPull-up resistor for standby detection

30

39

LS0, LS1, CPOL, SWAP, RXEN, F/S

V_IK

Input clamp voltage

I_I= –18 mA, V_DD= V_DD(min)

–1.2

100

V

0 V ≤ V_DD≤ 1.95 V;

V_I= {GND, 1.95 V}

I_ICMOSInput current⁽²⁾

nA

C_IN

I_IH

Input capacitance

2

pF

nA

V

High-level input current

Low-level input current

High-level input voltage

Low-level input voltage

V_IN= 0.7 × V_DD

V_IN= 0.3 × V_DD

–200

200

I_IL

V_IH

V_IL

0.7 × V_DD

0

V_DD

0.3 × V_DD

V

(1) All typical values are at 25°C and with 1.8-V supply unless otherwise noted.

(2) Do not leave any CMOS Input unconnected or floating to minimize leakage currents. Every input must be connected to a valid logic

level V_IHor V_OLwhile power is supplied to V_DD

.

6.7 Output Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R[0:7], G[0:7], B[0:7], VS, HS, PCLK, CPE

1-ChM, F/S = L, I_OH= –250 μA

2- or 3-ChM, F/S = L, I_OH= –500 μA

1-ChM, F/S = H, I_OH= –500 μA

2- or 3-ChM, F/S = H, I_OH= –2 mA

1-ChM, F/S = L, I_OL= 250 μA

2- or 3-ChM, F/S = L, I_OL= 500 μA

1-ChM, F/S = H, I_OL= 500 μA

2- or 3-ChM, F/S = H, I_OL= 2 mA

1-ChM, F/S = L

V_OH

High-level output current

0.8 × V_DD

V_DD

V

V_OL

Low-level output current

High-level output current

0

0.2 × V_DD

V

–250

–500

I_OH

2- or 3-ChM, F/S = L; 1-ChM, F/S = H

2- or 3-ChM, F/S = H

μA

–2000

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over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

250

UNIT

1-ChM, F/S = L

I_OL

Low-level output current

2- or 3-ChM, F/S = L; 1-ChM, F/S = H

2- or 3-ChM, F/S = H

500

μA

2000

6.8 Timing Requirements

PARAMETER

TEST CONDITIONS

MIN UNIT

1ChM: x = 0.29, f_PCLK= 15 MHz,

RXEN at V_DD, V_IH= V_DD, V_IL= GND,

R_L= 100 Ω, test setup as in Figure 7-2,

test pattern as in Table 7-7

f_CLK= 15 MHz⁽⁴⁾

630

f_CLK= 4 MHz to 15 MHz⁽⁵⁾

f_CLK= 30 MHz⁽⁴⁾

1 / (60 × f_CLK) – 480

2ChM: x = 0.14, f_PCLK= 30 MHz,

RXEN at V_DD, V_IH= V_DD, V_IL= GND,

R_L= 100 Ω, test setup as in Figure 7-2,

test pattern as in Table 7-8

630

Receiver input skew margin⁽¹⁾

(see Figure 9-2)

(2) (3)

t_RSKMx

ps

f_CLK= 8 MHz to 30 MHz⁽⁵⁾

f_CLK= 65 MHz⁽⁴⁾

1 / (30 × f_CLK) – 480

3ChM: RXEN at V_DD, V_IH= V_DD, V_IL= GND,

test setup as in Figure 7-2,

test pattern as in Table 7-9

360

f_CLK= 20 MHz to 65 MHz⁽⁵⁾

1 / (20 × f_CLK) – 410

(1) This includes the receiver internal set-up and hold time uncertainty, all PLL related high-frequency random and deterministic jitter

components that impact the jitter budget, ISI and duty cycle distortion from the front end receiver, and the skew from CLK to data D0,

D1, and D2; The pulse position minimum and maximum variation is given with a bit error rate target of 10^–12; Measurements of the total

jitter are taken over a sample amount of > 10^–12samples.

(2) Receiver Input Skew Margin (t_RSKM) is the timing margin available for transmitter output pulse position (t_PPOS), interconnect skew, and

interconnect inter-symbol interference. tRSKM represents the reminder of the serial bit time not taken up by the receiver strobe

uncertainty;. The t_RSKMassumes a bit error rate better than 10^-12

.

(3) t_RSKMis indirectly proportional to the internal set-up and hold time uncertainty, ISI and duty cycle distortion from the front end receiver,

the skew mismatch from CLK to data D0, D1, and D2, as well as the PLL cycle-to-cycle jitter.

(4) The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temp

ranges.

(5) These Minimum and Maximum Limits are simulated only.

6.9 Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK–

t_R/F

Input rise and fall time

RXEN at V_DD; see Figure 7-4

800

100

ps

Input rise or fall time

mismatch between all

SubLVDS inputs

t_R(n) – t_R(m) and t_F(n) – t_F(m) with

n = {D0, D1, D2, or CLK} and

m = {D0, D1, D2, or CLK}

Δt_R/F

–100

R[7:0], G[7:0], B[7:0], VS, HS, PCLK, CPE

1-channel mode, F/S = L

2-channel mode, F/S = L

3-channel mode, F/S = L

1-channel mode, F/S = H

2-channel mode, F/S = H

3-channel mode, F/S = H

8

4

16

8

Rise and fall time

20% to 80% of V_DD

C_L= 10 pF⁽³⁾

(see Figure 7-3)

4

8

t_R/F

ns

(2)

4

8

1

2

1

2

1-channel and 3-channel mode

CPOL = V_IL, 2-channel mode

CPOL = V_IH, 2-channel mode

45%

48%

41%

50%

53%

47%

55%

59%

52%

t_OUTP

PCLK output duty cycle

Output skew from PCLK to

t_OSK

R[0:7], G[0:7], B0:7], HS, see Figure 7-3

VS, and DE

–500

500

ps

INPUT TO OUTPUT RESPONSE TIME

10

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over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

Propagation delay time

from CLK+ input to PCLK

output

RXEN at V_DD, V_IH= V_DD, V_IL= GND, C_L= 10 pF,

see Figure 7-8

t_PD(L)

1.4 / f_PCLK1.9 / f_PCLK2.5 / f_PCLK

s

RXEN glitch suppression V_IH= V_DD, V_IL= GND, RXEN toggles from

t_GS

3.8

2

μs

pulse width⁽⁴⁾

V_ILto V_IH; see Figure 7-9 and Figure 7-10

Enable time from power

down (↑RXEN)

Time from RXEN pulled high to data outputs

enabled and outputs valid data; see Figure 7-10

t_pwrup

ms

RXEN is pulled low during receive mode;

time measurement until all outputs held static:

R[0:7] = G[0:7] = B[0:7] = VS = HS = high,

DE = PCLK = low and PLL is Shutdown;

see Figure 7-10

Disable time from active

mode (↓RXEN)

t_pwrdn

11

2

μs

RXEN at V_DD; device is in standby; time

Enable time from Standby measurement from CLK input starts switching to

t_wakeup

ms

(↑↓CLK)

PCLK and data outputs enabled and outputting

valid data; see Figure 7-11

RXEN at V_DD; device is receiving data; time

measurement from CLK input signal stops (input

open or input common mode VICM exceeds

Disable time from active

t_sleep

mode (CLK transitions to threshold voltage V_thstby) until all outputs held

3

μs

high-impedance)

static: R[0:7] = G[0:7] = B[0:7] = VS = HS = high,

DE = PCLK = low and PLL is Shutdown;

see Figure 7-11

2-ChM; f_PCLK= 22 MHz

3-ChM; f_PCLK= 65 MHz

0.087 × f_PCLK

0.075 × f_PCLK

Tested from CLK

input to PCLK output

f_BW

PLL bandwidth⁽⁵⁾

MHz

(1) All typical values are at 25°C and with 1.8-V supply unless otherwise noted.

(2) t_R/Fdepends on the F/S setting and the capacitive load connected to each output. Some application information of how to calculate t_R/F

based on the output load and how to estimate the timing budget to interconnect to an LCD driver are provided in the application section

near the end of this data sheet.

(3) The output rise and fall time is optimized for an output load of 10 pF. The rise and fall time can be adjusted by changing the output load

capacitance.

(4) The RXEN input incorporates a glitch-suppression logic to disregard short input pulses. t_GSis the duration of either a high-to-low or

low-to-high transition that is suppressed.

(5) When using the SN65LVDS302 receiver in conjunction with the SN65LVDS301 transmitter in one link, the PLL bandwidth of the

SN65LVDS302 receiver always exceed the bandwidth of the SN65LVDS301 transmit PLL. This ensures stable PLL tracking under all

operating conditions and maximizes the receiver skew margin.

6.10 Device Power Dissipation

PARAMETER

TEST CONDITIONS

TYP

16.8

64.7

MAX

UNIT

f_CLK= 4 MHz

f_CLK= 65 MHz

f_CLK= 4 MHz

f_CLK= 65 MHz

V_DDx= 1.8 V, T_A= 25°C,

mW

all outputs terminated with 10 pF

Device Power

Dissipation

P_D

27.4

V_DDx= 1.95 V, T_A= –40°C,

all outputs terminated with 10 pF

mW

128.8

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Typical Characteristics

Some of the plots in this section show more than one curve representing various device pin relationships. Taken

together, they represent a working range for the tested parameter.

100.0

30

2-Channel Mode, 22 MHz (VGA), F/S = 1

25

STANDBY

2-Channel Mode, 11 MHz (HVGA), F/S = 1

10.0

20

2-Channel Mode, 22 MHz (VGA), F/S = 0

15

2-Channel Mode, 11 MHz (HVGA), F/S = 0

1.0

10

POWERDOWN

5

0.1

0

-50

-30

-10

10

30

50

70

90

-50

-30

-10

10

30

50

70

90

Temperature - °C

Figure 6-2. Quiescent Supply Current vs

Temperature

Figure 6-1. Supply Current vs Temperature

40

35

2 - ChM, F/S = 1, typ pwr

30

2 - ChM, F/S = 1, jitter test

25

1 - ChM, F/S = 1, jitter test

20

15

20

1 - ChM,

F/S = 1,

typ pwr

1 - ChM F/S = 0, jitter test

15

10

2 - ChM F/S = 0, jitter test

5

0

1 - ChM, F/S = 0, typ pwr

2 - ChM, F/S = 0, typ pwr

0

5

10

15

20

25

30

0

5

10

15

20

f - Frequency - MHz

Figure 6-3. Supply Current vs Frequency, 1-

Channel Mode

Figure 6-4. Supply Current vs Frequency, 2-

Channel Mode

450

40

3 - ChM, F/S = 1, jitter test

Limit with RSKM=130 ps

400

35

3 - ChM, F/S = 1, typ pwr

350

30

25

20

FL3G Limit

300

3-ChM 56 MHz (XGA)

2-ChM 22 MHz (VVGA)

250

200

3 - ChM F/S = 0, jitter test

15

3-ChM 65 MHz

150

10

1-ChM 11 MHz (HVGA)

100

3 - ChM, F/S = 0, typ pwr

5

0

50

0

30

40

15

20

25

35

45

50

55

60

-40

-20

0

20

40

60

80

f - Frequency - MHz

Temperature - °C

Figure 6-5. Supply Current vs Frequency, 3-

Channel Mode

Figure 6-6. Receiver Strobe Position vs

Temperature

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12.0

900

800

700

600

500

400

300

200

100

0

3-ChM

Spec Limit 2ChM

MHz: 9%

10.0

8.0

6.0

4.0

2.0

0.0

3-ChM

8

2-ChM

Spec Limits

3-Ch Mode

2-ChM

1-ChM

3-ChM

Spec Limit 3ChM

Spec Limits

1-Ch Mode

Spec Limits

2-Ch Mode

3-ChM

2-ChM

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

0

10

20

30

40

50

60

70

Frequency - MHz

Figure 6-7. PLL Bandwidth

Figure 6-8. PCLK Cycle-to-Cycle Output Jitter

2000

1500

1000

Receiver Strobe

Position uncertainty

T(PPOS )

Additional interconnect margin

500

225

Minimum desired interconnect budget

0

-225-

-500

-1000

-1500

-2000

120

170

220

270

dR - Mbps

320

370

420

Bit width

Trskm

1ChM

Trskm - Tppos

225ps

Figure 6-9. RSKM, 1-Channel Mode vs Bit Rate

2000

1500

1000

2000

1500

Bit width

Trskm

Bit width

Trskm - Tppos

1000

Trskm

Trskm - Tppos

500

0

500

225 ps

0

225 ps

-500

Trskm - Tppos

-500

-1000

-1500

-2000

Trskm - Tppos

Trskm

-1000

Trskm

Bit width

-1500

-2000

120

170

220

270

320

370

420

200 250 300 350 400 450 500 550 600 650

dR - Mbps

Figure 6-10. RSKM, 2-Channel Mode vs Bit Rate

Figure 6-11. RSKM, 3-Channel Mode vs Bit Rate

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249

190

0

3-Channel Mode,

f(PCLK) = 56 MHz

–190

3-Channel Mode,

f(PCLK) = 56 MHz

–251

300 ps/div

3.5 ns/div

Response Over 80-inch FR-4 + 1m Coax Cable

Response With 10-pF Load

Figure 6-12. XGA 3-Channel Output Waveform

Figure 6-13. XGA 3-Channel Output Waveform

0.0

-2.0

-10.0

-20.0

-30.0

-40.0

-50.0

-60.0

-4.0

-6.0

-8.0

-10.0

-12.0

-14.0

-16.0

-18.0

-20.0

0

200 400 600 800 1000 1200 1400 1600 1800 2000

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Frequency - MHz

Figure 6-14. Input Common-Mode Noise Rejection

vs Frequency

Figure 6-15. Input Return Loss

-50

-60

0.0

-10.0

-20.0

-30.0

-40.0

-50.0

-60.0

-70.0

-80.0

-70

-80

-90

f(PCLK) = 65 MHz

-100

-110

-120

-130

-140

-150

-160

-170

-180

0

200 400 600 800 1000 1200 1400 1600 1800 2000

1

10

100

1k

10k

FREQUENCY - Hz

100k

1M

10M

Frequency - MHz

Figure 6-17. Phase Noise

Figure 6-16. Input Differential Crosstalk vs

Frequency

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9.0

8.5

12

11

10

8 MHz

9 %

20 MHz

8.7 %

4 MHz

9 %

Spec Limit

1 ChM

Spec Limit

2 ChM

Spec Limit

3 ChM

8.0

7.5

7.0

15 MHz

8.1 %

9

8

7

6

5

30 MHz

8.1 %

65 MHz

7.5 %

6.5

6.0

4

0

100

200

300

400

500

600

700

70

50

60

30

40

20

0

10

PLL - Frequency - MHz

PCLK - Frequency - MHz

Figure 6-18. SN65LVDS302 PLL Bandwidth

Figure 6-19. SN65LVDS301 PLL Bandwidth

30

f(PCLK)=62 MHz

25

20

15

10

5

0

200

400

600

800

1000

1200

1400

1600

1800

2000

FREQUENCY - MHz

Figure 6-20. GTEM SAE J1752/3 EMI Test

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7 Parameter Measurement Information

SN65LVDS302

V

2

1

DDPLLD

V

DDPLLA

Noise

V

1 W

DD

10µF

Generator

100 mV

V

DDLVDS

GND

1.8V

Supply

Note: The generator regulates the

1

1.6 H

noise amplitude at point to the

target amplitude given under the table

Recommended Operating Conditions

Figure 7-1. Power Supply Noise Test Set-Up

To measure t_RSKM,CLK is advanced or delayed with respect to data until errors are observed at the receiver outputs. The advance

or delay is then reduced until there are no data errors observed over 10^-12serial bit times. The magnitude of the advance or delay

is t_RSKM

Programmable delay

CLK

D1

CLK and Data

Pattern

Generator

DUT:

SN65LVDS302

Bit error

Detector

D2

D3

Ideal receiver strobe position

t_{PG_ERROR}

T_RSKM(p)

C

T_RSKM(n)

t_bit

t_RSKM

t_{PG_ERROR}

t_bit

- is the smaller of the two measured values t_RSKM(p) and t_RSKM(n)

- Test equipment (pattern generator) intrinsic output pulse position timing uncertainty

- serial bit time

C - LVDS302 set-up and hold-time uncertainty

Note: C can be derived by subtracting the receiver skew margin t_RSKM(p) + t_RSKM(p) from one serial bit time

Figure 7-2. Jitter Budget

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t

F

t

setup

80% (V_OH-V_OL

20% (V_OH-V_OL

)

R[7:0], G[7:0],

B[7:0], HS, VS, DE

t

hold

t

OSK

t

R

V

OH

80% (V_OH-V_OL

)

PCLK

(CPOL=0)

50% (V - –V

)

OH OL

20% (V_OH-V_OL

)

V

OL

t

R

t

F

Note:

The Set-up and Hold-time of CMOS outputs R[7:0], G[7:0],

B[7:0], HS, VS, and DE in relation to PCLK can be

calulated by:

1

t

=

-t

- t

- Dt

DUTP

S&H

REF OSK

2 -r

PCLK

Figure 7-3. Output Rise and Fall, Setup and Hold Time

V

– V

Dx–

, V

– V

CLK–

Dx+

CLK+

100%(V

)

IC

t

f

t

r

80%(V

)

ID

0V

20%(V

0%(V

)

ID

)

ID

Figure 7-4. SubLVDS Differential Input Rise and Fall Time Defintion

CLK+, Dx+

V_DDLVDS

R_ID/2

R_BBDC

Gain

Stage

R_ID/2

CLK–, Dx–

Standby

detection

line end

termination

ESD

Figure 7-5. Equivalent Input Circuit Design

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SWAP,

CPOL, LSx,

RXEN, F/S

I

ICMOS

CMOS Input

CLK+, Dx+

(V +V )/2

I+ I-

I

I+

V

ICMOS

I

O

RGB, VS, HS,

CPE PCLK

V

I

ID

I-

CLK-, Dx-

V

I+

V

ICM

O

V

I-

SubLVDS Input

CMOS Output

Figure 7-6. I/O Voltage and Current Definition

RGB, VS, HS,

CPE, PCLK

V

O

SN65LVDS302

C_L=10 pF

Figure 7-7. CMOS Output Test Circuit, Signal and Timing Definition

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Pixel_(n)

Pixel_(n–1)

Pixel_(n+1)

R7_(n+1)

R7_(n–1)

R7_(n)

CP R7

R7_(n–2)

D0+

R7 R6 R5 R4

CP R7

CLK–

CLK+

t_PD(L)

V_DD/2

PCLK

(CPOL = 0)

Pixel_(n–1)

CMOS Data Out

R7_(n–3)

R7_(n–1)

R7

R6

R6_(n–3)

R6_(n–1)

Figure 7-8. Propagation Delay Input to Output (LS0 = LS1 = 0)

/2

V

DD

RXEN

t

GS

CLK

t

PLL

PLL Approaches Lock

VCO Internal Signal

t

pwrup

PCLK

R[7:0], G[7:0], B[7:0], VS, HS

DE

Figure 7-9. Receiver Phase Lock Loop Set Time and Receiver Enable Time

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20 ns

<

3 ms

2 ms

Glitch shorter

than t will be

GS

ignored

less than 20ns

Spike will be

rejected

Glitch shorter

than t will be

GS

ignored

RXEN

t

pwrup

t

pwrdn

PCLK

t

I

GS

CC

t

GS

CLK

RX

RX disabled

turns

OFF

Receiver disabled

(OFF)

Receiver enabled

(ON)

Receiver aquires lock

(OFF)

Figure 7-10. Receiver Enable and Disable Glitch Suppression Time

CLK

t

wakeup

sleep

PCLK

R[7:0], G[7:0], B[7:0], VS, HS,

RX enabled;

output data

invalid

RX

disabled

(OFF)

RX enabled

output data valid

Receiver aquires lock,

outputs still disabled

Receiver disabled

(OFF)

Figure 7-11. Standby Detection

7.1 Power Consumption Tests

Table 7-1 shows an example test pattern word.

Table 7-1. Example Test Pattern Word

WORD

R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE

1

0x7C3E1E7

7

C

3

E

1

E

7

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

0

VS HS DE

0

1

0

1

0

1

0

1

7.2 Typical IC Power Consumption Test Pattern

Typical power-consumption test patterns consist of sixteen 30-bit receive words in 1-channel mode, eight 30-bit

receive words in 2-channel mode and five 30-bit receive words in 3-channel mode. The pattern repeats itself

throughout the entire measurement. It is assumed that every possible code on the RGB outputs has the same

probability to occur during typical device operation.

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Table 7-2. Typical IC Power Consumption Test Pattern, 1-Channel Mode

TEST PATTERN:

R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE

WORD

1

2

0x0000007

0xFFF0007

0x01FFF47

0xF0E07F7

0x7C3E1E7

0xE707C37

0xE1CE6C7

0xF1B9237

0x91BB347

0xD4CCC67

0xAD53377

0xACB2207

0xAAB2697

0x5556957

0xAAAAAB3

0xAAAAAA5

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Table 7-3. Typical IC Power Consumption Test Pattern, 2-Channel Mode

TEST PATTERN:

R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE

WORD

1

2

3

4

5

6

7

8

0x0000001

0x03F03F1

0xBFFBFF1

0x1D71D71

0x4C74C71

0xC45C451

0xA3aA3A5

0x5555553

Table 7-4. Typical IC Power Consumption Test Pattern, 3-Channel Mode

Test Pattern:

WORD

R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE

1

2

3

4

5

0xFFFFFF1

0x0000001

0xF0F0F01

0xCCCCCC1

0xAAAAAA7

7.3 Maximum Power Consumption Test Pattern

The maximum (or worst-case) power consumption of the SN65LVDS302 is tested using the two different test

pattern shown in table. Test patterns consist of sixteen 30-bit receive words in 1-channel mode, eight 30-bit

receive words in 2-channel mode, and five 30-bit receive words in 3-channel mode. The pattern repeats itself

throughout the entire measurement. It is assumed that every possible code on RGB outputs has the same

probability to occur during typical device operation.

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Table 7-5. Worst-Case Power Consumption Test Pattern

TEST PATTERN:

R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE

WORD

1

2

0xAAAAAA5

0x5555555

Table 7-6. Worst-Case Power Consumption Test Pattern

TEST PATTERN:

R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE

WORD

1

2

0x0000000

0xFFFFFF7

7.4 Output Skew Pulse Position and Jitter Performance

The following test patterns are used to measure the output skew pulse position and the jitter performance of the

SN65LVDS302. The jitter test pattern stresses the interconnect, particularly to test for ISI, using very long run-

lengths of consecutive bits, and incorporating very high and low data rates, maximizing switching noise. Each

pattern is self-repeating for the duration of the test.

Table 7-7. Receive Jitter Test Pattern, 1-Channel Mode

TEST PATTERN:

R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE

WORD

1

0x0000001

0x0000031

0x00000F1

0x00003F1

0x0000FF1

0x0003FF1

0x000FFF1

0x0F0F0F1

0x0C30C31

0x0842111

0x1C71C71

0x18C6311

0x1111111

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

0x3333331

0x2452413

0x22A2A25

0x5555553

0xDB6DB65

0xCCCCCC1

0xEEEEEE1

0xE739CE1

0xE38E381

0xF7BDEE1

0xF3CF3C1

0xF0F0F01

0xFFF0001

0xFFFC001

0xFFFF001

0xFFFFC01

22

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Table 7-7. Receive Jitter Test Pattern, 1-Channel Mode (continued)

TEST PATTERN:

R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE

WORD

30

31

32

0xFFFFF01

0xFFFFFC1

0xFFFFFF1

Table 7-8. Receive Jitter Test Pattern, 2-Channel Mode

TEST PATTERN:

R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE

WORD

1

0x0000001

0x000FFF3

0x8008001

0x0030037

0xE00E001

0x00FF001

0x007E001

0x003C001

0x0018001

0x1C7E381

0x3333331

0x555AAA5

0x6DBDB61

0x7777771

0x555AAA3

0xAAAAAA5

0x5555553

0xAAA5555

0x8888881

0x9242491

0xAAA5571

0xCCCCCC1

0xE3E1C71

0xFFE7FF1

0xFFC3FF1

0xFF81FF1

0xFE00FF1

0x1FF1FF1

0xFFCFFC3

0x7FF7FF1

0xFFF0007

0xFFFFFF1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Table 7-9. Receive Jitter Test Pattern, 3-Channel Mode

TEST PATTERN:

R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE

WORD

1

2

3

0x0000001

0x0000003

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Table 7-9. Receive Jitter Test Pattern, 3-Channel Mode (continued)

TEST PATTERN:

R[7:4], R[3:0], G[7:4], G[3:0], B[7–4], B[3–0], 0, VS, HS, DE

WORD

4

0x0101013

0x0303033

0x0707073

0x1818183

0xE7E7E71

0x3535351

0x0202021

0x5454543

0xA5A5A51

0xADADAD1

0x5555551

0xA6A2AA3

0xA6A2AA5

0x5555553

0x5555555

0xAAAAAA1

0x5252521

0x5A5A5A1

0xABABAB1

0xFDFCFD1

0xCAAACA1

0x1818181

0xE7E7E71

0xF8F8F81

0xFCFCFC1

0xFEFEFE1

0xFFFFFF1

0xFFFFFF5

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

24

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8 Detailed Description

8.1 Overview

The SN65LVDS302 is a de-serialising device where the input serial data and clock are received through Sub

Low-Voltage Differential Signaling (SubLVDS) lines. The SN65LVDS302 supports three operating power modes

(Shutdown, Standby, and Active) to conserve power.

Two Link Select lines LS0 and LS1 select whether 1, 2, or 3 serial links are used. The RXEN input may be used

to put the SN65LVDS302 in a Shutdown mode. The SN65LVDS302 enters an active Standby mode if the

common mode voltage of the CLK input becomes shifted to V_DDLVDS, as when the transmitter releases the CLK

output into high-impedance. This minimizes power consumption without the need of switching an external control

pin. The SN65LVDS302 is characterized for operation over ambient air temperatures of –40°C to 85°C. All

CMOS and SubLVDS signals are 2-V tolerant with V_DD= 0 V. This feature allows signal power-up before V_CCis

stabilized.

When receiving, the PLL locks to the incoming clock (CLK) and generates an internal high-speed clock at the

line rate of the data lines. The data is serially loaded into a shift register using the internal high-speed clock. The

de-serialized data is presented on the parallel output bus with a recreation of the Pixel clock (PCLK) generated

from the internal high-speed clock. If no input CLK signal is present, the output bus is held static with the PCLK

and DE held low, while all other parallel outputs are pulled high.

The parallel (CMOS) output bus offers a bus-swap feature. The SWAP control pin controls the output pin order of

the output pixel data to be either R[7:0]. G[7:0], B[7:0], VS, HS, DE or B[0:7], G[0:7], R[0:7], VS, HS, DE. This

gives a PCB designer the flexibility to better match the bus to the LCD driver pinout or to put the receiver device

on the top side or the bottom side of the PCB. The F/S control input selects between a slow CMOS bus output

rise time for best EMI and power consumption and a fast CMOS output for increased speed or higher load

designs.

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8.2 Functional Block Diagram

V_DDLVDS

R_BBDC

CPE

iPCLK

D0+

SWAP

F/S

50

Parity

Check

SubLVDS

AND

50

D0-

1

0

8

V_DDLVDS

R[0:7]

R_BBDC

D1+

50

8

SubLVDS

G[0:7]

B[0:7]

0

1

50

D1-

V_DDLVDS

R_BBDC

D2+

HS

VS

50

SubLVDS

RGB=1

HS=VS=1

DE=0

50

D2-

V_DDLVDS

standby or

pwr down

DE

R_BBDC

x10, x15, or x30

CLK+

50

PLL

multiplier

SubLVDS

50

iPCLK

CLK-

x1

0

1

PCLK

CPOL

standby

V_thstby

Glitch

Suppression

RXEN

LS0

Control

LS1

26

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8.3 Feature Description

8.3.1 Swap Pin Functionality

The SWAP pin allows the pcb designer to reverse the RGB bus, minimizing potential signal crossovers due to

signal routing. The two drawings beneath show the RGB signal pin assignment based on the SWAP pin setting.

9

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

A

B

C

D

E

F

A

B

C

D

E

F

R6

R5

R4

R2

R1

R0

G7

G6

G5

G4

G3

G2

G1

B7

B5

B3

B1

B2

B3

B5

B6

B7

G0

G1

G2

G3

G4

G5

G6

R0

R2

R4

R6

R7

R3

G0

B6

B0

B4

G7

R1

B4

R3

SN65LVDS302

Top View

SN65LVDS302

Top View

B2

R5

B0

R7

G

H

J

G

H

J

PCLK

HS

PCLK

HS

VS

DE

VS

DE

Figure 8-1. Pinout With SWAP PIN = GND

8.3.2 Parity Error Detection and Handling

Figure 8-2. Pinout With SWAP PIN = VDD

The SN65LVDS302 receiver performs error checking on the basis of a parity bit that is transmitted across the

subLVDS interface from the transmitting device. Once the SN65LVDS302 detects the presence of the clock and

the PLL has locked onto PCLK, then the parity is checked. Parity-error detection ensures detection of all single

bit errors in one pixel and 50% of all multi-bit errors.

The parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus VS, HS, and DE. Odd Parity

bit signalling is used. The parity error is output on the CPE pin. If the sum of the 27 data bits and the parity bit

result in an odd number, the receive data are assumed to be valid. The CPE output is held low. If the sum equals

an even number, parity error is declared. The CPE output indicates high for half a PCLK period. The CPE output

is set with the data bit transition and cleared after 1/2 the data bit time. This allows counting every detected

parity error with a simple counter connected to CPE.

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A Parity error is indicated by a

high pulse on CPE; the width of

the pulse is 1/2 the length of a

PCLK cycle

Also if there is a parity error detected then the

CPE

data on that PCLK cycle is not output. Instead,

the last valid data from a previous PCLK cycle

is repeated on the output bus. This is to prevent

any bit error that may occur on the LVDS link

from causing perturbations in VS, HS, or DE that

may be visually disruptive to a display.

R[0:7], G[0:7],

B[0:7], HS, VS, DE

PCLK

The reserved bits are not covered in the parity

calculations.

(CPOL=0)

When a parity error is

detected, the receiver outputs

the previous pixel on the bus

Hence no data transitions

occur.

Figure 8-3. Parity Error Detection and Handling

8.4 Device Functional Modes

8.4.1 Deserialization Modes

The SN65LVDS302 receiver has three modes of operation controlled by link-select pins LS0 and LS1. Table 8-1

shows the deserializer modes of operation.

Table 8-1. Logic Table: Link Select Operating Modes

LS1

LS0

MODE OF OPERATION

DATA LINKS STATUS

D0 active;

D1, D2 disabled

0

1ChM

1-channel mode (30-bit serialization rate)

D0, D1 active;

D2 disabled

0

1

2ChM

3ChM

2-channel mode (15-bit serialization rate)

1

0

1

3-channel mode (10-bit serialization rate)

Reserved

D0, D1, D2 active

Reserved

8.4.1.1 1-Channel Mode

While LS0 and LS1 are held low, the SN65LVDS302 receives payload data over a single SubLVDS data pair,

D0. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 30. The internal

high speed clock is used to shift in the data payload on D0 and to deserialize 30 bits of data. Figure 8-4

illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal high speed clock is

divided by a factor of 30 to recreate the pixel clock and the data payload with the pixel clock is presented on the

output bus. The reserved bits and parity bit are not output. While in this mode, the PLL can lock to a clock that is

in the range of 4 MHz through 15 MHz. This mode is intended for smaller video display formats that do not need

the full bandwidth capabilities of the SN65LVDS302.

CLK -

CLK +

res res CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 VS HS DE res res CP R7 R6

D0 +/- CHANNEL

Figure 8-4. Data and Clock Input in 1-ChM (LS0 and LS1 = low)

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8.4.1.2 2-Channel Mode

While LS0 is held high and LS1 is held low, the SN65LVDS302 receives payload data over two SubLVDS data

pairs, D0 and D1. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 15.

The internal high speed clock is used to shift in the data payload on D0 and D1 and to deserialize 15 bits of data

from each pair. Figure 8-5 illustrates the timing and the mapping of the data payload into the 30-bit frame. The

internal high speed clock is divided by a factor of 15 to recreate the pixel clock, and the data payload with pixel

clock is presented on the output bus. The reserved bits and parity bit are not output. While in this mode the PLL

can lock to a clock that is in the range of 8 MHz through 30 MHz.

CLK -

CLK +

CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS res CP R7 R6

res G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 HS DE res G3 G2

D0 +/- CHANNEL

D1 +/- CHANNEL

Figure 8-5. Data and Clock Input in 2-ChM (LS0 = high; LS1 = low)

8.4.1.3 3-Channel Mode

While LS0 is held low and LS1 is held high the SN65LVDS302 receives payload data over three SubLVDS data

pairs: D0, D1, and D2. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of

10. The internal high speed clock is used to shift in the data payload on D0, D1, and D2, and to deserialize 10

bits of data from each pair. Figure 8-6 illustrates the timing and the mapping of the data payload into the 30-bit

frame. While in this mode the PLL can lock to a clock that is in the range of 20 MHz through 65 MHz.

CLK -

CLK +

D0 +/- CHANNEL CP R7 R6 R5 R4 R3 R2 R1 R0 VS CP R7 R6

D1 +/- CHANNEL res G7 G6 G5 G4 G3 G2 G1 G0 HS res G7 G6

D2 +/- CHANNEL res B7 B6 B5 B4 B3 B2 B1 B0 DE res B7 B6

Figure 8-6. Data and Clock Input in 3-ChM (LS0 = low; LS1 = high)

8.4.2 Powerdown Modes

The SN65LVDS302 Receiver has two powerdown modes to facilitate efficient power management.

8.4.2.1 Shutdown Mode

A low input signal on the RXEN pin puts the SN65LVDS302 into Shutdown mode. This turns off most of the

receiver circuitry including the SubLVDS receivers, PLL, and deserializers. The subLVDS differential-input

resistance remains 100 Ω, while any input signal is ignored. All outputs hold a static output pattern:

R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low.

The current draw in Shutdown mode is nearly zero if the SubLVDS inputs are left open or pulled high.

8.4.2.2 Standby Mode

The SN65LVDS302 enters the Standby mode when the SN65LVDS302 is not in Shutdown mode but the

SubLVDS clock-input common-mode voltage is above 0.9 × V _DDLVDS. The CLK input incorporates a pull-up

circuit to shift the SubLVDS clock-input common-mode voltage to V_DDLVDSin the absence of an input signal. All

circuitry except the SubLVDS clock-input Standby monitor is shut down. The SN65LVDS302 also enters Standby

mode when the input clock frequency on the CLK input is less than 500 kHz. The SubLVDS input resistance

remains 100 Ω while any input signal on the data inputs D0, D1, and D2 becomes ignored. All outputs holds a

static output pattern:

R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low.

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The current drawn in Standby mode is very low.

8.4.3 Active Modes

A high input signal on RXEN combined with a CLK input signal switching faster than 3 MHz and V_ICMsmaller

than 1.3 V forces the SN65LVDS302 into Active mode. Current consumption in active mode depends on

operating frequency and the number of data transitions in the data payload. CLK-input frequencies from 3 MHz

to 4 MHz activates the device but proper PLL functionality is not secured. The SN65LVDS302 must not be

operated in active mode at CLK frequencies below 4 MHz.

8.4.3.1 Acquire Mode (PLL Approaches Lock)

When the SN65LVDS302 is enabled and a SubLVDS clock input present, the PLL pursues lock to the input

clock. While the PLL pursues lock the output data bus holds a static output pattern:

R[0:7] = G[0:7] = B[0:7] = VS = HS = high; DE = PCLK = low.

For proper device operation, the pixel clock frequency must fall within the valid f _PCLKrange specified under

recommended operating conditions. If the pixel clock frequency is larger than 3 MHz but smaller than f_PCLK(min)

,

the SN65LVDS302 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the

pixel clock, causing the PLL monitor to release the device into active receive mode. If this happens, the PLL may

or may not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and

PLL deadlock (loss of VCO oscillation).

8.4.3.2 Receive Mode

After the PLL achieves lock the device enters the normal receive mode. The output data bus presents the de-

serialized data. The PCLK output pin outputs the recovered pixel clock.

8.4.4 Status Detect and Operating Modes Flow

The SN65LVDS302 switches between the power saving and active modes in the following way:

Power Up

RXEN = 1

CLK Input Inactive

RXEN Low

for > 10 ms

Power Up

RXEN = 0

Standby

Mode

ShutDown

Mode

RXEN High

for > 10 ms

V_ICM(CLK) > 0.9 V_DDLVDS

RXEN Low

for > 10 ms

V_ICM(CLK) > 0.9 V_DDLVDS

or f_CLK< 500 kHz

CLK Input Active

Power Up

RXEN = 1

CLK Active

Receive

Mode

Acquire

Mode

PLL Achieved Lock

RXEN Low

for > 10 ms

Figure 8-7. Operating Modes and State Machine Diagram

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Table 8-2. Status Detect and Operating Modes Descriptions

CHARACTERISTICS

CONDITIONS

Least amount of power consumption (most circuitry turned off);

All outputs held static:

R[0:7] = G[0:7] = B[0:7] = VS = HS = high DE = PCLK = low;

Shutdown

Mode

RXEN is set low for longer than 10 μs^{(1) (2)}

Low power consumption (Standby monitor circuit active;

PLL is shutdown to conserve power); All outputs held static:

R[0:7] = G[0:7] = B[0:7] = VS = HS = high DE = PCLK = low;

RXEN is high for longer than 10 μs, and both CLK input

common-mode V_ICM(CLK)above 0.9 × V_DDLVDS, or CLK

input floating⁽²⁾

Standby

Mode

RXEN is high; CLK input monitor detected clock input

common mode and woke up receiver out of Standby

mode

Acquire

Mode

PLL pursues lock; All outputs held static:

R[0:7] = G[0:7] = B[0:7] = VS = HS = high DE = PCLK = low;

Receive

Mode

Data transfer (normal operation);

receiver deserializes data and provides data on parallel output

RXEN is high and PLL is locked to incoming clock

(1) In Shutdown Mode, all SN65LVDS302 internal switching circuits (for example: PLL, serializer, etc.) are turned off to minimize power

consumption. The input stage of any input pin remains active.

(2) Leaving CMOS control inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All

CMOS inputs must be tied to a valid logic level V_ILor V_IHduring Shutdown or Standby Mode. Exceptions are the subLVDS inputs CLK

and Dx, which can be left unconnected while not in use.

Table 8-3. Operating Mode Transitions

MODE TRANSITION

USE CASE

TRANSITION SPECIFICS

1. RXEN high > 10 μs

2. Receiver enters standby mode

Shutdown → Standby Drive RXEN high to enable receiver

a. R[0:7] = G[0:7] = B[0:7] = VS = HS remain high and DE = PCLK low

b. Receiver activates clock input monitor

1. CLK input monitor detects clock input activity

2. Outputs remain static

Standby → Acquire

Acquire → Receive

Transmitter activity detected

Link is ready to receive data

3. PLL circuit is enabled

1. PLL is active and approaches lock

2. PLL achieves lock within t_wakeup

3. D1, D2, or D3 become active depending on LS0 and LS1 selection

4. First Data word was recovered

Parallel output bus turns on switching from static output pattern to

output first valid data word

5.

1. Receiver disables outputs within t_sleep

Transmitter requested to enter Standby

mode by input common mode voltage V

_ICM> 0.9 V_DDLVDSas when transmitter

output clock stops or enters high-

impedance state.

2. RX Input monitor detects V_ICM> 0.9 VDD_LVDSwithin t_sleep

Receive → Standby

R[0:7] = G[0:7] = B[0:7] = VS = HS transition to high and DE = PCLK to

low on next falling PLL clock edge

3.

4. PLL shuts down. Clock activity input monitor remains active

1. RXEN pulled low for > t_pwrdn

Receive and Standby

→ Shutdown

R[0:7] = G[0:7] = B[0:7] = VS = HS remain static high or transition to

static high and DE = PCLK remain or transition to static low

Turn off Receiver

2.

3. Most IC circuitry is shut down for least power consumption

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

9.1.1 Application Information

General application guidelines and hints for LVDS drivers and receivers may be found in the LVDS application

notes and design guides.

9.1.2 Preventing Increased Leakage Currents in Control Inputs

A floating (left open) CMOS input allows leakage currents to flow from V_DDto GND. Do not leave any CMOS

input unconnected or floating. Every input must be connected to a valid logic level V_IHor V_OLwhile power is

supplied to V_DD. This also minimizes the power consumption of standby and power down mode.

9.1.3 Calculation Example: HVGA Display

The following calculation shows an example for a Half-VGA display with the following parameters:

Display Resolution:

Frame Refresh Rate:

480 × 320

58.4 Hz

Hsync =5

HFP=20

Visible area = 480 Columns

Horizontal Visible Pixel:

Horizontal Front Porch:

Horizontal Sync:

480 columns

20 columns

5 columns

3 columns

Vsync =5

VBP=3

Horizontal Back Porch:

Visible area

=320 lines

Vertical Visible Pixel:

Vertical Front Porch:

Vertical Sync:

320 lines

10 lines

5 lines

Visible area

Vertical Back Porch:

3 lines

Entire Display

VFP=10

Figure 9-1. HVGA Display

Calculation of the total number of pixel and blanking overhead:

Visible Area Pixel Count:

Total Frame Pixel Count:

Blanking Overhead:

480 × 320 = 153600 pixel

( 480 + 20 + 5 + 3 ) × ( 320 + 10 + 5 + 3 ) = 171704 pixel

( 171704 – 153600 ) ÷ 153600 = 11.8%

The application requires the following serial-link parameters:

Pixel Clk Frequency:

171704 × 58.4 Hz = 10 MHz

1-channel mode: 10 MHz × 30 bit/channel = 300 Mbps

2-channel mode: 10 MHz × 15 bit/channel = 150 Mbps

Serial Data Rate:

32

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9.1.4 How to Determine Interconnect Skew and Jitter Budget

Designing a reliable data link requires examining the interconnect skew and jitter budget. The sum of all

transmitter, PCB, connector, FPC, and receiver uncertainties must be smaller than the available serial bit time.

The highest pixel clock frequency defines the available serial bit time. The transmitter timing uncertainty is

defined by t_PPOSin the transmitter data sheet. For a bit-error-rate target of ≤ 10^–12, the measurement duration for

t_PPOSis ≥ 10¹². The SN65LVDS302 receiver can tolerate a maximum timing uncertainty defined by t_RSKM. The

interconnect budget is calculated by Equation 1.

t_{int erconnect}= t_RSKM- t_PPOS

(1)

Example:

f_PCLK(max)

23 MHz (VGA display resolution, 60 Hz)

Transmission mode: 2-ChM; t_PPOS(SN65LVDS301)

Target bit error rate

330 ps

10^–12

t_RSKM(SN65LVDS302)

1 / (2 × 15 × f_PCLK) – 480 ps = 969 ps

The interconnect budget for cable skew and ISI must be smaller than the output of Equation 2.

t_{int erconnect}= t_RSKM- t_PPOS= 639ps

(2)

data transition

Ideal T

PPosn

Data Period /2

D0, D1, D2

Ideal receiver strobe position

T_PPosn(max)

T_PPosn(min)

RSKM

RX internal sampling clock

(max)

R

(min)

SPosn

Tppos: Transmitter output pulse position (min and max)

T_PPosx(max) -T_PPosx(min) = TJ_{TXPLL(non-trackable)}+ t_TXskew+ t_TXDJ

RSKM: Receiver Skew Margin

R_SPosn: Receiver input strobe position (min and max)

RSKM = SKEW_PCB+ XTALK_PCB+ ISI_PCB

R

_SPosn(max) - R_SPosn(min) = Skew_RX+ S&H_RX+ TJ_{(RXPLL(non-trackable)}

:

non-trackable TX PLL jitter; this jitter is the integration

f

TJ

SKEW

XTALK

ISI

: PCB induced Skew (trace + connector);

PCB

TXPLL(non-trackable)

of total jitter above the receiver PLL bandwidth

>

TXPLL

TJ

(BWRX);

;

:

PCB induced cross-talk;

PCB

TJ=RJ[ps-rms]*14 DJ[ps]

transmitter output skew (skew between CLK and data)

+

:

Inter-symbol interference of PCB; is

Skew

S&H

TJ

: Receiver input skew (skew between CLK and Dx input)

RX

PCB

t

:

TXskew

dependent on interconnect frequency loss; may be

:

Receiver input latch Sample

&

Hold uncertainty

RX

zero for short interconnects.

:

Intrinsic RX PLL jitter above RX PLL bandwidth; PLL

>

TJ

(RXPLL(non-trackable)

); TJ=RJ[ps-rms]*14

t

Transmitter Deterministic JItter of TX output stage (includes TX

TXIDJ

Intersymbol Interference ISI)

f(BW

+ DJ[ps]

RX

Figure 9-2. Jitter Budget

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9.1.5 F/S Pin Setting and Connecting the SN65LVDS302 to an LCD Driver

Note

Receiver PLL tracking: To maximize the design margin for the interconnect, good RX PLL tracking of

the TX PLL is important. FlatLink3G requires the RX PLL to have a bandwidth higher than the

bandwidth of the TX PLL. The SN65LVDS302 PLL design is optimized to track the SN65LVDS0301

PLL particularly well, thus providing a very large receiver skew margin. A FlatLink3G-compliant link

must provide at least ±225 ppm of receiver skew margin for the interconnect.

It is important to understand the tradeoff between power consumption, EMI, and maximum speed when selecting

the F/S signal. It is beneficial to choose the slowest rise time possible to minimize EMI and power consumption.

Unfortunately a slower rise time also reduces the timing margin left for the LCD driver. Hence it is necessary to

calculate the timing margin to select the correct F/S pin setting.

The output rise time depends on the output driver strength and the output load. An LCD driver typical capacitive

load is assumed with approximately 10 pF. As the capacitive load increases, the rise time also increases. Rise

time of the SN65LVDS302 is measured as the time duration it takes the output voltage to rise from 20% of V_DD

and 80% of V_DDand fall time is defined as the time for the output voltage to transition from 80% of V_DDdown to

20%.

Within one mode of operation and one F/S pin setting, the rise time of the output stage is fixed and does not

adjust to the pixel frequency. Due to the short bit time at very fast pixel clock speeds and the real capacitive load

of the display driver, the output amplitude might not reach V_DDand GND saturation fully. To ensure sufficient

signal swing and verify the design margin, it becomes necessary to determine that the output amplitude under

any circumstance reaches the display driver’s input stage logic threshold (usually 30% and 70% of V_DD).

Figure 9-3 shows a worst-case rise time simulation assuming a LCD driver load of 16 pF at VGA display

resolution. PCLK is the fastest switching output. With F/S set to GND (Figure 9-4), the PCLK output voltage

amplitude is significantly reduced. The voltage amplitude of the output data RGB[7:0], VS, HS, and DE shows

less amplitude attenuation because these outputs carry random data pattern and toggle equal or less than half

of the PCLK frequency. It is necessary to determine the timing margin between the LVDS302 output and LCD

driver input.

Application: VGA (2-channel mode)

2

1.8

1.6

1.4

1.2

1

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

100

150

200

250

300

350

400

450

500

550

600

100

150

200

250

300

350

400

450

500

550

600

RX Rise/Fall Time (ns)

data 22 Mbps

CLK 22 MHz

F/S = V_DD

CL = 16 pF

F/S = 0

CL = 16 pF

The data signal has a slower maximum switching frequency, and

therefore drives a larger amplitude than the clock signal.

Figure 9-3. Output Amplitude vs Toggling

Frequency (F/S = 1)

Figure 9-4. Output Amplitude vs Toggling

Frequency (F/S = 0)

34

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9.1.6 How to Determine the LCD Driver Timing Margin

To determine the timing margin, it is necessary to specify the frequency of operation, identify the set-up and hold

time of the LCD driver, and specify the output load of the SN65LVDS302 as a combination of the LCD driver

input parasitics plus any capacitance caused by the connecting PCB trace. Furthermore, the setting of pin F/S

and the SN65LVDS302 output skew impact the margin. The total remaining design margin calculates as

following:

t_{rise max}´ C_LOAD

1

(

)

t_DM

=

- t_{DUTP max_ error}

-

- t_OSK

(

)

2´ ƒ_PCLK

10 pF

(3)

where

•

t_DMis the design margin

f_PCLKis the pixel clock frequency

t_{DUTP(max_error)}is the maximum duty cycle error

t_rise(max)is the maximum rise or fall time; see t_R/Funder switching characteristics

C_Lis the parasitic capacitance (sum of LCD driver input parasitics + connecting PCB trace)

t_skewis the clock to data output skew SN65LVDS302

Example:

At a pixel clock frequeny of 5.5 MHz (QVGA), and an assumed LCD driver load of 15 pF, the remaining timing

margin is:

t_DUTPmax - 50

)

(

100%

5%

1

t_{DUTP max_ error}

=

´ t_PCLK

=

´

100% 5.5 MHz

= 9.1ns

(

)

(4)

16 ns

´15 pF

F/S=GND

1

(

)

t_DM

=

- 9 ns -

- 500 ps = 57.3 ns

2´ 5.5 MHz

10 pF

(5)

As long as the set-up and hold time of the LCD driver are each less than 57 ns, the timing budget is met

sufficiently.

9.1.7 Typical Application Frequencies

The SN65LVDS302 supports pixel clock frequencies from 4 MHz to 65 MHz over 1, 2, or 3 data lanes. Table 9-1

provides a few typical display resolution examples and shows the number of data lanes necessary to connect

the SN65LVDS302 with the display. The blanking overhead is assumed to be 20%. Often, blanking overhead is

smaller, resulting in a lower data rate. Furthermore, the examples in the table assumes a display frame refresh

rate of 60 Hz. The actual refresh rate may differ depending on the application-processor clock implementation.

Table 9-1. Typical Application Data Rates and Serial Lane Usage

SERIAL DATA RATE PER LANE

DISPLAY SCREEN

RESOLUTION

VISIBLE PIXEL

COUNT

BLANKING

OVERHEAD

DISPLAY REFRESH

RATE

PIXEL CLOCK

FREQUENCY [MHz]

1-ChM

2-ChM

3-ChM

176x220 (QCIF+)

240x320 (QVGA)

640x200

38,720

76,800

20%

90 Hz

60 Hz

4.2 MHz

5.5 MHz

125 Mbps

166 Mbps

276 Mbps

316 Mbps

335 Mbps

332 Mbps

432 Mbps

442 Mbps

128,000

146,432

154,880

153,600

200,000

204,800

307,200

327,680

409,920

9.2 MHz

138 Mbps

158 Mbps

167 Mbps

166 Mbps

216 Mbps

221 Mbps

332 Mbps

354 Mbps

443 Mbps

352x416 (CIF+)

352x440

10.5 MHz

11.2 MHz

11.1 MHz

14.4 MHz

14.7 MHz

22.1 MHz

23.6 MHz

29.5 MHz

320x480 (HVGA)

800x250

640x320

640x480 (VGA)

1024x320

221 Mbps

236 Mbps

295 Mbps

854x480 (WVGA)

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Table 9-1. Typical Application Data Rates and Serial Lane Usage (continued)

SERIAL DATA RATE PER LANE

DISPLAY SCREEN

RESOLUTION

VISIBLE PIXEL

COUNT

BLANKING

OVERHEAD

DISPLAY REFRESH

RATE

PIXEL CLOCK

FREQUENCY [MHz]

1-ChM

2-ChM

3-ChM

800x600 (SVGA)

1024x768 (XGA)

480,000

786,432

20%

60 Hz

34.6 MHz

56.6 MHz

346 Mbps

566 Mbps

9.2 Typical Applications

9.2.1 VGA Application

Figure 9-5 shows a possible implementation of a standard 640x480 VGA display. The LVDS301 interfaces to the

SN65LVDS302, which is the corresponding receiver device to deserialize the data and drive the display driver.

The pixel clock rate of 22 MHz assumes approximately 10% blanking overhead and 60 Hz display refresh rate.

The application assumes 24-bit color resolution. Also shown is how the application processor provides a

powerdown (reset) signal for both serializer and the display driver. The signal count over the Flexible Printed

Circuit board (FPC) could be further decreased by using the standby option on the SN65LVDS302 and pulling

RXEN high with a 30 kΩ resistor to V_DD

.

2x0.1uF

FPC

GND

2.7V

1.8V

GND

2.7V

1.8V

GND

2x0.01uF

Application

Processor

(e.g. OMAP)

Video Mode Display

Driver

CLK+

CLK–

CLK+

CLK–

22MHz

D0+

D0–

D0+

D0–

330Mbps

PCLK

Pixel CLK

PCLK

22MHz

27

22MHz

27

D1+

D1–

D1+

D1–

D[7:0]

D[15:8]

D[23:16]

R[7:0]

G[7:0]

B[7:0]

R[7:0]

G[7:0]

B[7:0]

HS, VS, DE

SN65LVDS301

SN65LVDS 302

18. V

1.8V

If FPC wire count is critical, replace this

connection with a pull-up resistor at RXEN

Serial port interface

(3-wire IF)

3

Figure 9-5. Typical VGA Display Application

9.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 9-2 as the input parameters.

Table 9-2. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

–40°C to 85°C

1.65 V to 1.95 V

70 mV to 200 mV

0.6 V to 1.2 V

< 630 ps

Operating free-air temperature range

Supply voltages, V_DD, V_DDLVDS, V_DDPLLA, V_DDPLLD

Magnitude of differential input voltage, V_ID

Input voltage common mode range, V_ICM

Receiver input skew, 2-channel mode

36

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9.2.1.2 Detailed Design Procedure

Configuration and Connection:

•

Include a power supply capable of providing the power requirements of the whole system.

Configure the Application Processor to transmit the RGB data at 22 MHz.

Configure the transmitter and the SN65LVDS302 to work using two channels.

Connect the SN65LVDS302 to the LCD display following the same color mapping. See Section 8.3.1 for more

information.

9.2.1.2.1 Power-Up and Power-Down Sequences

The SN65LVDS302 does not require a specific power up sequence for the voltage lines. However, TI

recommends using the power-up and power-down sequences detailed below.

Power-up sequence (SN65LVDS301 RXEN input initially low):

1. Ramp up LCD power and SN65LVDS302 (approximately 0.5 ms to 10 ms) but keep the backlight turned off.

2. Wait for an additional 0 ms to 200 ms to ensure display noise does not occur.

3. Enable video source output; start sending black video data.

4. Toggle SN65LVDS301 TXEN = V_IH.

5. Toggle SN65LVDS302 RXEN = V_IH.

6. Send at least 1 ms of black video data. This allows the SN65LVDS301 to be phase locked, and the display to

show black data first.

7. Start sending true image data.

8. Enable backlight.

Power-down sequence (SN65LVDS301 RXEN input initially high):

1. Disable LCD backlight and wait for the minimum time specified in the LCD datasheet for the backlight to go

low.

2. Switch the video source output from active video data to black image data (all visible pixels turn black) for at

least 2 frame times.

3. Set SN65LVDS301 TXEN = GND and wait for 250 ns.

4. Set SN65LVDS302 RXEN = GND and wait for 250 ns.

5. Disable the video output of the video source.

6. Remove power from the LCD panel for lowest system power.

9.2.1.3 Application Curves

250

190

249

190

2-Channel Mode,

f(PCLK) = 22 MHz

2-Channel Mode,

f(PCLK) = 22 MHz

0

–190

–250

–190

–251

500 ps/div

Response Over 8-inch FR-4 + 1m Coax Cable

Response Over 80-inch FR-4 + 1m Coax Cable

Figure 9-6. VGA 2-Channel Output Waveform

Figure 9-7. VGA 2-Channel Output Waveform

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249

190

3-Channel Mode,

f(PCLK) = 22 MHz

0

–190

–251

1 ns/div

Response Over 80-inch FR-4 + 1m Coax Cable

Figure 9-8. VGA3-Channel Output Waveform

9.2.2 Dual LCD-Display Application

The example in Figure 9-9 shows a possible application setup driving two video-mode displays from one

application processor. The data rate of 330 Mbps at a pixel clock rate of 5.5 MHz corresponds to a 320x240

QVGA resolution at 60 Hz refresh rate and 10% blanking overhead.

2x0.1uF

FPC

GND

2. 7V

1. 8V

GND

2. 7V

1. 8V

GND

2x0.01uF

Display Driver

1

Application

Processor

21

(e.g. OMAP )

CLK+

CLK-

CLK+

CLK-

5.5MHz

330Mbps

PCLK

Pixel CLK

PCLK

5.5MHz

18+3

D0+

D0-

R[ 5: 0]

G[ 5: 0]

B[ 5: 0]

D0+

D0-

EN

SIN

SOUT

SCLK

D[ 5: 0]

D[ 11 : 6]

D[ 17: 12]

HS, VS, DE

R[ 5: 0]

G[ 5: 0]

B[ 5: 0]

HS, VS, DE

SN65LVDS 301

SN65LVDS 302

Display Driver

2

PCLK

EN

SIN

1.8V

SOUT

SCLK

Figure 9-9. Example Dual-QVGA Display Application

9.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-3 as the input parameters.

Table 9-3. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

–40°C to 85°C

1.65 V to 1.95 V

70 mV to 200 mV

0.6 V to 1.2 V

< 630 ps

Operating free-air temperature range

Supply voltages, V_DD, V_DDLVDS, V_DDPLLA, V_DDPLLD

Magnitude of differential input voltage, V_ID

Input voltage common mode range, V_ICM

Receiver input skew, 1-channel mode

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9.2.2.2 Application Curve

249

190

1-Channel Mode,

f(PCLK) = 5.5 MHz

0

–190

–251

1 ns/div

Response Over 80-inch of FR-4 + 1m Coax Cable

Figure 9-10. QVGA Output Waveform

10 Power Supply Recommendations

To minimize the power supply noise floor, provide good decoupling near the SN65LVDS302 power pins. TI

recommends placing one 0.01-μF ceramic capacitor at each power pin, and two 0.1-μF ceramic capacitors on

each power node. The distance between the SN65LVDS302 and capacitors must be minimized to reduce loop

inductance and provide optimal noise filtering. Placing the capacitor underneath the SN65LVDS302 on the

bottom of the PCB is often a good choice. A 100-pF ceramic capacitor can be put at each power pin to optimize

the EMI performance.

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11 Layout

11.1 Layout Guidelines

Use chamfered corners (45° bends) instead of right-angle (90°) bends. Right-angle bends increase the effective

trace width, which changes the differential trace impedance creating large discontinuities. A 45° bend is seen as

a smaller discontinuity.

When routing traces next to a via or between an array of vias, make sure that the via clearance section does not

interrupt the path of the return current on the ground plane below.

Avoid metal layers and traces underneath or between the pads of the LVDS connectors for better impedance

matching. Otherwise they cause the differential impedance to drop below 75 Ω and fail the board during TDR

testing.

Use solid power and ground planes for 100 Ω impedance control and minimum power noise.

For a multilayer PCB, TI recommends keeping one common GND layer underneath the device and connect all

ground terminals directly to this plane. For 100 Ω differential impedance, use the smallest trace spacing

possible, which is usually specified by the PCB vendor.

Keep the trace length as short as possible to minimize attenuation.

Place bulk capacitors (10 μF) close to power sources, such as voltage regulators or where the power is supplied

to the PCB.

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12 Device and Documentation Support

12.1 Community Resource

12.2 Trademarks

FlatLink^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

42

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PACKAGE OUTLINE

ZXH0080A

NFBGA - 1 mm max height

S

C

A

L

E

3

.

0

BALL GRID ARRAY

5.1

4.9

A

B

BALL A1 CORNER

INDEX AREA

5.1

4.9

0.7

0.6

C

1 MAX

SEATING PLANE

0.08 C

BALL TYP

0.25

TYP

0.15

4 TYP

SYMM

J

H

G

F

SYMM

80X

4

E

D

C

B

A

TYP

0.35

0.25

0.15

0.05

C B

C

A

0.5 TYP

1

2

3

4

5

6

7

8

9

0.5 TYP

4221325/A 01/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis is for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This is a Pb-free solder ball design.

www.ti.com

EXAMPLE BOARD LAYOUT

ZXH0080A

NFBGA - 1 mm max height

BALL GRID ARRAY

(0.5) TYP

0.265

0.235

80X

6

7

9

2

3

4

5

8

1

A

B

C

(0.5) TYP

D

E

F

G

H

J

SYMM

LAND PATTERN EXAMPLE

SCALE:15X

0.05 MAX

0.05 MIN

METAL

UNDER

MASK

(

0.25)

METAL

(

0.25)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4221325/A 01/2014

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

See Texas Instruments Literature No. SBVA017 (www.ti.com/lit/sbva017).

www.ti.com

EXAMPLE STENCIL DESIGN

ZXH0080A

NFBGA - 1 mm max height

BALL GRID ARRAY

(0.5) TYP

80X ( 0.25)

(R0.05) TYP

5

4

3

6

7

9

2

8

1

A

(0.5)

TYP

B

C

METAL

TYP

D

E

F

G

H

J

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:20X

4221325/A 01/2014

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	SN65LVDS302ZXH
厂家：	TEXAS INSTRUMENTS
描述：	SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver
文件：	总49页 (文件大小：2695K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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