SN65LVDS314RSKR [TI]
可编程 27 位串行至并行接收器 | RSK | 64 | -40 to 85;
| 型号： | SN65LVDS314RSKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 可编程 27 位串行至并行接收器 | RSK | 64 | -40 to 85 驱动 接口集成电路 驱动器 |
| 文件： | 总43页 (文件大小：1952K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS314
www.ti.com.cn
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
可编程 27 位串行至并行接收器
查询样品: SN65LVDS314
1
特性
2
•
串行接口技术
串行数据和时钟通过超低压差分信令 (subLVDS) 线路
•
与 Flatlink™3G 兼容，例如 SN65LVDS301 和
SN65LVDS311
接收。 为了节能，SN65LVDS314 支持三个运行模
式（关断、待机和激活）。
•
支持在 1，2 或 3 条超低压 (subLVDS) 差分线路
上接收高达 24 位 RGB 数据和 3 个控制位的视频
接口
当接收时，锁相环 (PLL) 锁定至下一个时钟 CLK 并且
在数据线路的线路速率上生成一个内部高速时钟。 使
用此内部高速时钟将数据串行载入到一个的移位寄存器
内。 在从内部高速时钟中重新创建像素时钟 PCLK
时，被并行化的数据出现在并行输出总线上。 如果没
有出现输入 CLK 信号，在 PCLK 和 DE 被保持在低电
平时，输出总线被保持在静止状态，而所有其它并行输
出被拉至高电平。
•
•
•
•
subLVDS 差分电压电平
1.8V 至 3.3V 灵活的 RGB 信令电平
高达 1.755Gbps 数据吞吐量
三个运行模式以达到节能的目的
–
–
–
有源模式四分之一 VGA (QVGA)-17mW
典型关断模式 - 0.6μW
典型待机模式-典型值 54μW
并行 (CMOS) 输出总线提供一个总线交换特性。
SAWP（交换）控制位将输出像素数据的输出引脚顺序
控制为 R[7:0] G[7:0]，B[7:0]，VS，HS，DE 或
B[0:7]，G[0:7]，R[0:7]，VS，HS，DE。 这为 PCB
设计人员提供了适当的灵活性来更好将总线与 LCD 驱
动器输出引脚相匹配或者将接收器器件放置在 PCB 的
顶部或者底部。 F/S 控制输入在一个针对最佳 EMI 的
慢速 CMOS 总线输出上升时间与功耗和针对增速或者
更高负载设计的快速 CMOS 输出间进行选择。
•
•
用于实现印刷电路板 (PCB) 布局布线灵活性的总线
交换
静电放电 (ESD) 额定值 > 4kV（人体模型
(HBM)）
•
•
•
4MHz-65MHz 的像素时钟范围
全部 CMOS 输入上的故障安全特性
采用 8mm x 8mm 四方扁平无引线 (QFN) 封装，
焊球间距 0.4mm
•
极低的电磁干扰 (EMI)，符合 SAE J1752/3 'Kh' 技
术规范
应用范围
•
•
•
图形控制器和 LCD 显示间的小型低辐射接口
相机、摄像机、嵌入式计算机
便携式多媒体播放器
说明
SN65LVDS314 接收器将与 FlatLink™3G 兼容的串行
输入数据解串行并成为 27 个并行数据输出。
SN65LVDS314 接收器包含一个移位寄存器，在检查
奇偶校验位之后，此寄存器从 1，2 或 3 个串行输入载
入 30 个位，并且锁存 24 个像素位和 3 个控制位输出
至并行 CMOS 输出。 如果奇偶校验确认奇偶校验正
确，通道奇偶校验错误 (CPE) 输出保持低电平。 如果
检测到奇偶校验错误，CPE 输出生成一个高脉冲，而
数据输出总线忽略刚刚接收到的像素。 或者，最后一
LCD
VDS314
L
or
VDS302
L
Application
Processor
with CMOS
Video Interface
LVDS301
or
LVDS311
个数据字在下一个时钟周期内被保持在输出总线上。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Flatlink is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
版权 © 2012, Texas Instruments Incorporated
English Data Sheet: SLLSE98
SN65LVDS314
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
www.ti.com.cn
这些装置包含有限的内置 ESD 保护。
存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损伤。
说明（继续）
两个链路选择线路 LS0 和 LS1 选择使用的 1，2 或 3 条串行链路。 RXEN 输入可被用于将 SN65LVDS314 置于一
个关断模式中。 如果 CLK 输入的共模电压被移位至 VDDLVDS（例如，发送器将 CLK 输出释放为高阻抗状
态），那么 SN65LVDS314 进入一个有源待机模式。 这在无需切换一个外部控制引脚的前提下可大大减少功耗。
SN65LVDS314 额定运行环境温度范围为 -40°C 至 85°C。 所有 CMOS 和 subLVDS 信号在 VDD=0V 时的耐压为
2V。这一特性可实现 VDD稳定前的信号加电。
FUNCTIONAL BLOCK DIAGRAM
VDDLVDS
RBBDC
Level Shifter
CPE
SWAP
F/S
iPCLK
D0+
50
50
Parity
Check
SubLVDS
AND
D0-
1
0
8
VDDLVDS
R[0:7]
RBBDC
D1+
50
50
8
8
SubLVDS
G[0:7]
B[0:7]
0
1
D1-
D2+
D2-
VDDLVDS
RBBDC
HS
VS
50
50
SubLVDS
RGB=1
HS=VS=1
DE=0
VDDLVDS
standby or
pwr down
DE
RBBDC
x10, x15, or x30
CLK+
CLK-
50
50
PLL
multiplier
SubLVDS
iPCLK
x1
0
1
PCLK
CPOL
standby
Vthstby
Glitch
Suppression
RXEN
LS0
Control
LS1
2
Copyright © 2012, Texas Instruments Incorporated
SN65LVDS314
www.ti.com.cn
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
PINOUT – TOP VIEW
RSK PACKAGE
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
G0/G7 49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
HS
VDD
G1/G6 50
G2/G5 51
G3/G4 52
G4/G3 53
G5/G2 54
G6/G1 55
G7/G0 56
CPE
VS
RXEN
VDD_PLLA
GND_PLLA
SWAP
GND
VDD_LVDS
VDD_LVDS
GND_LVDS
D0-
57
58
59
GND
VDD_IO
VDD
R0/B7 60
R1/B6 61
R2/B5 62
R3/B4 63
R4/B3 64
D0+
GND_LVDS
CLK-
CLK+
•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RGB output pin assignment based on SWAP pin setting:
SWAP = 0 / SWAP = 1
Copyright © 2012, Texas Instruments Incorporated
3
SN65LVDS314
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
www.ti.com.cn
SWAP PIN FUNCTIONALITY
The SWAP pin allows the pcb designer to reverse the RGB bus, minimizing potential signal crossovers due to
signal routing. The two drawings beneath show the RGB signal pin assignment based on the SWAP-pin setting.
RSK PACKAGE
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
G0
G1
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
HS
VDD
G2
CPE
G3
VS
G4
RXEN
G5
VDD_PLLA
GND_PLLA
SWAP
G6
G7
GND
VDD_LVDS
VDD_LVDS
GND_LVDS
D0-
GND
VDD_IO
VDD
R0
R1
R2
R3
R4
D0+
GND_LVDS
CLK-
CLK+
•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 1. Pinout With SWAP PIN = GND
4
Copyright © 2012, Texas Instruments Incorporated
SN65LVDS314
www.ti.com.cn
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
RSK PACKAGE
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
G7
G6
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
HS
VDD
G5
CPE
G4
VS
G3
RXEN
G2
VDD_PLLA
GND_PLLA
SWAP
G6
G0
GND
VDD_LVDS
VDD_LVDS
GND_LVDS
D0-
GND
VDD_IO
VDD
B7
B6
B5
B4
B3
D0+
GND_LVDS
CLK-
CLK+
•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 2. Pinout With SWAP PIN = VDD
Copyright © 2012, Texas Instruments Incorporated
5
SN65LVDS314
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
www.ti.com.cn
Table 1. Pin Description
PIN
SWAP
SIGNAL
R5
PIN
SWAP
.
SIGNAL
PIN
SWAP
SIGNAL
B5
L
H
L
H
L
H
-
L
H
L
H
L
H
-
1
22
-
GND_LVDS
43
B2
R2
R6
B6
2
3
23
24
-
-
VDD_LVDS
VDD_LVDS
44
45
B1
R1
R7
B7
B0
R0
4
5
6
LS0
VDD
LS1
25
26
27
-
-
-
SWAP
46
47
48
GND
VDD_IO
CPOL
G0
-
GND_PLLA
VDD_PLLA
-
-
-
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
-
7
-
-
-
-
-
-
-
-
VDD_PLLD
GND_PLLD
VDD_LVDS
GND_LVDS
D2+
28
29
30
31
32
33
34
35
-
-
-
-
-
-
-
-
RXEN
VS
49
50
51
52
53
54
55
56
G7
G1
8
G6
G2
9
CPE
VDD
HS
G5
G3
10
11
12
13
14
G4
G4
G3
G5
D2-
DE
G2
G6
GND_LVDS
D1+
VDD_IO
F/S
G1
G7
G0
15
16
-
-
D1-
36
37
-
PCLK
GND
B0
57
58
GND
VDD_IO
GND_LVDS
-
-
L
H
L
H
L
H
L
H
L
H
17
18
19
20
21
-
-
-
-
-
CLK+
CLK-
38
39
40
41
42
59
60
61
62
63
64
-
VDD
R7
B1
L
H
L
R0
B7
R1
B6
R2
B5
R3
B4
R4
B3
R6
B2
GND_LVDS
D0+
R5
H
L
B3
R4
H
L
B4
D0-
R3
H
L
H
6
Copyright © 2012, Texas Instruments Incorporated
SN65LVDS314
www.ti.com.cn
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
TERMINAL FUNCTIONS
NAME
I/O
DESCRIPTION
D0+, D0–
SubLVDS Data Link (active during normal operation)
SubLVDS Data Link (active during normal operation when LS0 = high and LS1 = low, or LS0 = low and
LS1=high; high impedance if LS0 = LS1 = low); input can be left open if unused
D1+, D1–
D2+, D2–
SubLVDS in
SubLVDS Data Link (active during normal operation when LS0 = low and LS1 = high, high-impedance
when LS1 = low); input can be left open if unused
CLK+, CLK–
R0–R7
G0–G7
B0–B7
HS
SubLVDS Input Pixel Clock; Polarity is fixed.
Red Pixel Data (8); pin assignment depends on SWAP pin setting
Green Pixel Data (8); pin assignment depends on SWAP pin setting
Blue Pixel Data (8); pin assignment depends on SWAP pin setting
Horizontal Sync
CMOS out
VS
Vertical Sync
DE
Data Enable
PCLK
LS0, LS1
Output Pixel Clock; rising or falling clock polarity is selected by control input CPOL
Link Select (Determines active SubLVDS Data Links and PLL Range) See Table 2
Disables the CMOS Drivers and Turns Off the PLL, putting device in shutdown mode
1 – Reciver enabled
0 – Receiver disabled (Shutdown)
Note: RXEN input incorporates glitch suppression logic to avoid unwanted switching. The input must be
pulled low for longer than 10µs continuously to force the receiver to enter Shutdown. The input must be
pulled high for at least 10μs continuously to activate the receiver. An input pulse shorter than 5us will be
interpreted as glitch and becomes ignored. At power up, the receiver is enabled immediately if RXEN=H
and disabled if RXEN=L
RXEN
Output Clock Polarity Selection
CMOS in
CPOL
SWAP
F/S
0 – rising edge clocking
1 – falling edge clocking
Bus Swap swaps the bus pins to allow device placement on top or bottom of PCB. See pinout drawing
for pin assignments.
0 – data output from R7...B0
1 – data output from B0...R7
CMOS bus rise time select
1 – fast output rise time
0 – slow output rise time
Channel Parity Error
This output indicates the detection of a parity error by generating an output high-pulse for half of a PCLK
clock cycle; this allows counting parity errors with a simple counter.
CPE
CMOS out
0 – no error
high-pulse – bit error detected
VDD
Supply Voltage
VDD_IO
RGB interface supply voltage
Supply Ground
GND
VDDLVDS
GNDLVDS
VDDPLLA
GNDPLLA
VDDPLLD
GNDPLLD
SubLVDS I/O supply Voltage
SubLVDS Ground
Power Supply
PLL analog supply Voltage
PLL analog GND
PLL digital supply Voltage
PLL digital GND
Copyright © 2012, Texas Instruments Incorporated
7
SN65LVDS314
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
www.ti.com.cn
FUNCTIONAL DESCRIPTION
Deserialization Modes
The SN65LVDS314 receiver has three modes of operation controlled by link-select pins LS0 and LS1. Table 2
shows the deserializer modes of operation.
Table 2. Logic Table: Link Select Operating Modes
LS1
LS0
Mode of Operation
Data Links Status
0
0
1ChM
2ChM
3ChM
1-channel mode (30-bit serialization rate)
D0 active;
D1, D2 disabled
0
1
2-channel mode (15-bit serialization rate)
D0, D1 active;
D2 disabled
1
1
0
1
3-channel mode (10-bit serialization rate)
Reserved
D0, D1, D2 active
Reserved
1-Channel Mode
While LS0 and LS1 are held low, the SN65LVDS314 receives payload data over a single SubLVDS data pair,
D0. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 30. The internal
high speed clock is used to shift in the data payload on D0 and to deserialize 30 bits of data. Figure 3 illustrates
the timing and the mapping of the data payload into the 30-bit frame. The internal high speed clock is divided by
a factor of 30 to recreate the pixel clock and the data payload with the pixel clock is presented on the output bus.
The reserved bits and parity bit are not output. While in this mode, the PLL can lock to a clock that is in the range
of 4 MHz through 15 MHz. This mode is intended for smaller video display formats that do not need the full
bandwidth capabilities of the SN65LVDS314.
CLK -
CLK +
res res CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 VS HS DE res res CP R7 R6
D0 +/- CHANNEL
Figure 3. Data and Clock Input in 1-ChM (LS0 and LS1 = low)
2-Channel Mode
While LS0 is held high and LS1 is held low, the SN65LVDS314 receives payload data over two SubLVDS data
pairs, D0 and D1. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 15.
The internal high speed clock is used to shift in the data payload on D0 and D1 and to deserialize 15 bits of data
from each pair. Figure 4 illustrates the timing and the mapping of the data payload into the 30-bit frame. The
internal high speed clock is divided by a factor of 15 to recreate the pixel clock, and the data payload with pixel
clock is presented on the output bus. The reserved bits and parity bit are not output. While in this mode the PLL
can lock to a clock that is in the range of 8 MHz through 30 MHz.
CLK -
CLK +
CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS res CP R7 R6
res G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 HS DE res G3 G2
D0 +/- CHANNEL
D1 +/- CHANNEL
Figure 4. Data and Clock Input in 2-ChM (LS0 = high; LS1 = low)
8
Copyright © 2012, Texas Instruments Incorporated
SN65LVDS314
www.ti.com.cn
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
3-Channel Mode
While LS0 is held low and LS1 is held high the SN65LVDS314 receives payload data over three SubLVDS data
pairs: D0, D1, and D2. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of
10. The internal high speed clock is used to shift in the data payload on D0, D1, and D2, and to deserialize 10
bits of data from each pair. Figure 5 illustrates the timing and the mapping of the data payload into the 30-bit
frame. While in this mode the PLL can lock to a clock that is in the range of 20 MHz through 65 MHz.
CLK -
CLK +
D0 +/- CHANNEL CP R7 R6 R5 R4 R3 R2 R1 R0 VS CP R7 R6
D1 +/- CHANNEL res G7 G6 G5 G4 G3 G2 G1 G0 HS res G7 G6
D2 +/- CHANNEL res B7 B6 B5 B4 B3 B2 B1 B0 DE res B7 B6
Figure 5. Data and Clock Input in 3-ChM (LS0 = low; LS1 = high)
POWERDOWN MODES
The SN65LVDS314 Receiver has two powerdown modes to facilitate efficient power management.
SHUTDOWN MODE
A low input signal on the RXEN pin puts the SN65LVDS314 into Shutdown mode. This turns off most of the
receiver circuitry including the SubLVDS receivers, PLL, and deserializers. The subLVDS differential-input
resistance remains 100 Ω, while any input signal is ignored. All outputs will hold a static output pattern:
R[0:7]=G[0:7]=B[0:7]=VS=HS=high; DE=PCLK=low.
The current draw in Shutdown mode will be nearly zero if the subLVDS inputs are left open or pulled high.
STANDBY MODE
The SN65LVDS314 will enter the Standby mode when the SN65LVDS314 is not in Shutdown mode but the
SubLVDS clock-input common-mode voltage is above 0.9 × VDDLVDS. The CLK input incorporates a pull-up circuit
to shift the SubLVDS clock-input common-mode voltage to VDDLVDS in the absence of an input signal. All circuitry
except the SubLVDS clock-input Standby monitor is shut down. The SN65LVDS314 will also enter Standby
mode when the input clock frequency on the CLK input is less than 500 kHz. The SubLVDS input resistance
remains 100 Ω while any input signal on the data inputs D0, D1, and D2 becomes ignored. All outputs will hold a
static output pattern:
R[0:7]=G[0:7]=B[0:7]=VS=HS=high; DE=PCLK=low.
The current drawn in Standby mode will be very low.
ACTIVE MODES
A high input signal on RXEN combined with a CLK input signal switching faster than 3 MHz and VICM smaller
than 1.3 V force the SN65LVDS314 into Active mode. Current consumption in active mode depends on operating
frequency and the number of data transitions in the data payload. CLK-input frequencies between 3 MHz and 4
MHz activate the device but proper PLL functionality is not secured. It is not recommended to operate the
SN65LVDS314 in active mode at CLK frequencies below 4 MHz.
ACQUIRE MODE (PLL Approaches Lock)
When the SN65LVDS314 is enabled and a SubLVDS clock input present, the PLL will pursue lock to the input
clock. While the PLL pursues lock the output data bus will hold a static output pattern:
R[0:7]=G[0:7]=B[0:7]=VS=HS=high; DE=PCLK=low.
Copyright © 2012, Texas Instruments Incorporated
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SN65LVDS314
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
www.ti.com.cn
For proper device operation, the pixel clock frequency must fall within the valid fPCLK range specified under
recommended operating conditions. If the pixel clock frequency is larger than 3 MHz but smaller than fPCLK(min)
,
the SN65LVDS314 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the
pixel clock, causing the PLL monitor to release the device into active receive mode. If this happens, the PLL may
or may not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and
PLL deadlock (loss of VCO oscillation).
RECEIVE MODE
After the PLL achieves lock the device enters the normal receive mode. The output data bus presents the de-
serialized data. The PCLK output pin outputs the recovered pixel clock.
PARITY ERROR DETECTION AND HANDLING
The SN65LVDS314 receiver performs error checking on the basis of a parity bit that is transmitted across the
subLVDS interface from the transmitting device. Once the SN65LVDS314 detects the presence of the clock and
the PLL has locked onto PCLK, then the parity is checked. Parity-error detection ensures detection of all single
bit errors in one pixel and 50% of all multi-bit errors.
The parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus VS, HS, and DE. Odd Parity
bit signalling is used. The parity error is output on the CPE pin. If the sum of the 27 data bits and the parity bit
result in an odd number, the receive data are assumed to be valid. The CPE output will be held low. If the sum
equals an even number, parity error is declared. The CPE output will indicate high for half a PCLK period. The
CPE output will be set with the data bit transition and cleared after 1/2 the data bit time. This allows counting
every detected parity error with a simple counter connected to CPE.
A Parity error is indicated by a
high pulse on CPE; the width of
the pulse is 1/2 the length of a
PCLK cycle
Also if there is a parity error detected then the
data on that PCLK cycle is not output. Instead,
CPE
the last valid data from a previous PCLK cycle
is repeated on the output bus. This is to prevent
R[0:7], G[0:7],
any bit error that may occur on the LVDS link
B[0:7], HS, VS, DE
from causing perturbations in VS, HS, or DE that
may be visually disruptive to a display.
PCLK
The reserved bits are not covered in the parity
calculations.
(CPOL=0)
When a parity error is
detected, the receiver outputs
the previous pixel on the bus
Hence no data transitions
occur.
10
Copyright © 2012, Texas Instruments Incorporated
SN65LVDS314
www.ti.com.cn
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
STATUS DETECT AND OPERATING MODES FLOW DIAGRAM
The SN65LVDS314 switches between the power saving and active modes in the following way:
Power Up
RXEN = 1
CLK Input Inactive
RXEN Low
for > 10 ms
Power Up
RXEN = 0
Standby
Mode
ShutDown
Mode
RXEN High
for > 10 ms
VICM(CLK) > 0.9 VDDLVDS
RXEN Low
for > 10 ms
VICM(CLK) > 0.9 VDDLVDS
or fCLK < 500 kHz
CLK Input Active
Power Up
RXEN = 1
CLK Active
Receive
Mode
Acquire
Mode
PLL Achieved Lock
RXEN Low
for > 10 ms
Table 3. Status Detect and Operating Modes Descriptions
Mode
Characteristics
Conditions
(1) (2)
Shutdown Mode
Least amount of power consumption (most circuitry turned
off); All outputs held static:
RXEN is set low for longer than 10μs
R[0:7]=G[0:7]=B[0:7]=VS=HS=high DE=PCLK=low;
Standby Mode
Low power consumption (Standby monitor circuit active; PLL RXEN is high for longer than 10 μs, and both CLK input
is shutdown to conserve power);
All outputs held static:
common-mode VICM(CLK) above 0.9×VDDLVDS, or CLK
input floating
(2)
R[0:7]=G[0:7]=B[0:7]=VS=HS=high DE=PCLK=low;
Acquire Mode
Receive Mode
PLL pursues lock; All outputs held static:
R[0:7]=G[0:7]=B[0:7]=VS=HS=high DE=PCLK=low;
RXEN is high; CLK input monitor detected clock input
common mode and woke up receiver out of Standby
mode
Data transfer (normal operation);
receiver deserializes data and provides data on parallel
output
RXEN is high and PLL is locked to incoming clock
(1) In Shutdown Mode, all SN65LVDS314 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power
consumption. The input stage of any input pin remains active.
(2) Leaving CMOS control inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All CMOS
inputs must be tied to a valid logic level VIL or VIH during Shutdown or Standby Mode. Exceptions are the subLVDS inputs CLK and Dx,
which can be left unconnected while not in use.
Copyright © 2012, Texas Instruments Incorporated
11
SN65LVDS314
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
www.ti.com.cn
Table 4. Operating Mode Transitions
MODE TRANSITION
USE CASE
TRANSITION SPECIFICS
Shutdown → Standby Drive RXEN high to enable
1. RXEN high > 10 μs
receiver
2. Receiver enters standby mode
a. R[0:7]=G[0:7]=B[0:7]=VS=HS remain high and DE=PCLK low
b. Receiver activates clock input monitor
1. CLK input monitor detects clock input activity
2. Outputs remain static
Standby → Acquire
Acquire → Receive
Transmitter activity
detected
3. PLL circuit is enabled
Link is ready to receive
data
1. PLL is active and approaches lock
2. PLL achieves lock within twakeup
3. D1, D2, and/or D3 become active depending on LS0 and LS1 selection
4. First Data word was recovered
5. Parallel output bus turns on switching from static output pattern to output first
valid data word
Receive → Standby
Transmitter requested to
enter Standby mode by
input common mode
1. Receiver disables outputs within tstandby
2. RX Input monitor detects VICM > 0.9 VDDLVDS within tstandby
3. R[0:7]=G[0:7]=B[0:7]=VS=HS transition to high and DE=PCLK to low on next
falling PLL clock edge
voltage VICM > 0.9 VDDLVDS
(e.g. transmitter output
clock stops or enters high-
impedance state)
4. PLL shuts down. Clock activity input monitor remains active
Receive/Standby →
Turn off Receiver
1. RXEN pulled low for > tpwrdn
Shutdown
2. R[0:7]=G[0:7]=B[0:7]=VS=HS remain static high or transition to static high and
DE=PCLK remain or transition to static low
3. Most IC circuitry is shut down for least power consumption
RGB Signaling Level
The signaling level of the R[0:7], G[0:7], B[0:7], HS, VS, DE, and PCLK outputs of the SN65LVDS314 can be
configured to be between 1.8 V and 3.3 V (nominal), depending on the voltage applied to the VDD_IO terminals.
This provides compatibility with LCD drivers with interface voltages between 1.8 V and 3.3 V without the need for
external level shifters.
12
Copyright © 2012, Texas Instruments Incorporated
SN65LVDS314
www.ti.com.cn
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
–0.3 to 2.175
–0.3 to 3.6
–0.5 to 2.175
–0.5 to VDD + 2.175
±4
UNIT
V
Supply voltage range, VDD (2), VDDPLLA, VDDPLLD, VDDLVDS
Supply voltage range, VDD_IO
V
Voltage range at any input When VDDx > 0 V
V
kV
V
or output terminal
When VDDx ≤ 0 V
Human Body Model(3) (all Pins)
Electrostatic discharge
Charged-Device Mode(4) (all Pins)
Machine Model(5) (all pins)
±1000
±200
Continuous power dissipation
Ouput current, IO
See Dissipation Rating Table
±5
–65 to 150
125
mA
°C
Storage temperature, TSTG
Maximum junction temperature, TJ
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminals
(3) In accordance with JEDEC Standard 22, Test Method A114-B
(4) In accordance with JEDEC Standard 22, Test Method C101
(5) In accordance with JEDEC Standard 22, Test Method A115-A
THERMAL INFORMATION
SN65LVDS314
THERMAL METRIC(1)
RSK
64 PINS
31.7
20
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
9.9
°C/W
ψJT
0.3
ψJB
9.9
θJCbot
2.4
xxx
(1) 有关传统和新的热 度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。
(2) 在 JESD51-2a 描述的环境中，按照 JESD51-7 的指定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然 对流条件下的结至环
境热阻。
(3) 通过在封装顶部模拟一个冷板测试来获得结至芯片外壳（顶部）的热阻。 不存在特定的 JEDEC 标准测试，但 可在 ANSI SEMI 标准 G30-
88 中能找到内容接近的说明。
(4) 按照 JESD51-8 中的说明，通过 在配有用于控制 PCB 温度的环形冷板夹具的环境中进行仿真，以获得结板热阻。
(5) 结至顶部特征参数， ψJT，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中 描述的程序从仿真数据中 提取出该参
数以便获得 θJA
(6) 结至电路板特征参数， ψJB，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中 描述的程序从仿真数据中 提取出该
参数以便获得 θJA
。
。
(7) 通过在外露（电源）焊盘上进行冷板测试仿真来获得 结至芯片外壳（底部）热阻。 不存在特定的 JEDEC 标准 测试，但可在 ANSI SEMI
标准 G30-88 中能找到内容接近的说明。
空白
DEVICE POWER DISSIPATION
PARAMETER
TEST CONDITIONS
TYP
12.8
59.2
MAX
UNIT
fCLK at 4 MHz
fCLK at 65 MHz
fCLK at 4 MHz
fCLK at 65 MHz
VDDx = 1.8 V, TA = 25°C, all outputs terminated with 10 pF
mW
Device Power
Dissipation
PD
41
VDD = VDDPLLA = VDDPLLD = VDDLVDS = 1.95 V, VDD_IO = 3.6 V,
all outputs terminated with 10 pF
mW
261.9
Copyright © 2012, Texas Instruments Incorporated
13
SN65LVDS314
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
www.ti.com.cn
MAX UNIT
RECOMMENDED OPERATING CONDITIONS(1)
MIN
1.65
1.65
TYP
VDD
VDDPLLA
Supply voltages
VDDPLLD
1.8
1.95
3.6
V
V
VDDLVDS
VDD_IO
Supply voltage for CMOS outputs
Test set-up see Figure 7
CLK ≤ 50MHz; f(noise) = 1Hz to 2 GHz
f
100
100
40
Supply voltage noise magnitude
50MHz (all supplies)
VDDn(PP)
mV
fCLK > 50MHz; f(noise) = 1Hz to 1MHz
fCLK > 50 MHz; f(noise) > 1MHz
TA
TC
Operating free-air temperature
Case temperature
–40
85
°C
°C
93.1
CLK+ and CLK–
1-Channel receive mode, see Figure 3
2-Channel receive mode, see Figure 4
3-Channel receive mode, see Figure 5
Standby mode(2), See Figure 16
4
8
15
30
MHz
fCLK±
Input Pixel clock frequency
20
65
500
65
kHz
%
tDUTCLK
CLK Input Duty Cycle
35
70
D0+, D0–, D1+, D1–, D2+, D2-, CLK+, and CLK–
|VID
|
Magnitude of differential input voltage |VD0+-VD0-|, |VD1+-VD1-|, |VD2+-VD2-|,
|VCLK+-VCLK-| during normal operation
200
1.2
mV
V
VICM
Input Voltage Common Mode Range Receive or Acquire mode
Stand-by mode
0.6
0.9 × VDDLVDS
–100
ΔVICM
Input Voltage Common Mode
Variation between all SubLVDS
inputs
VICM(n) – VICM(m) with n=D0, D1, D2, or CLK
and m=D0, D1, D2, or CLK
100
10
mV
%
ΔVID
Differential Input Voltage Amplitude
Variation between all SubLVDS
inputs
VID(n) – VID(m) with n=D0, D1, D2, or CLK
and m=D0, D1, D2, or CLK
–10
tR/F
Input Rise and Fall Time
RXEN at VDD; see figure 10
800
100
ps
ps
Δ tR/F
Input Rise or Fall Time mismatch
between all SubLVDS inputs
tR(n) – tR(m) and tF(n) – tF(m) with n=D0, D1,
D2, or CLK and m=D0, D1, D2, or CLK
–100
LS0, LS1, CPOL, SWAP, RXEN, F/S
VICMOSH
VICMOSL
tinRXEN
High-level input voltage
Low-level input voltage
RXEN input pulse duration
0.7×VDD
VDD
V
V
0
0.3×VDD
10
μs
R[7:0], G[7:0], B[7:0], VS, HS, DE, PCLK, CPE
CL Output load capacitance
(1) Unused single-ended inputs must be held high or low to prevent them from floating.
(2) PCLK input frequencies lower than 500 kHz force the SN65LVDS314 into standby mode. Input frequencies between 500 kHz and
10
pF
3 MHz may or may not activate the SN65LVDS314. Input frequencies beyond 3 MHz activate the SN65LVDS314. Input frequencies
between 500 kHz and 4 MHz are not recommended, and can cause PLL malfunction.
14
Copyright © 2012, Texas Instruments Incorporated
SN65LVDS314
www.ti.com.cn
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1) MAX(2) UNIT
VDD_IO = 1.8 V
VDD_IO = 2.5 V
VDD_IO = 3.3 V
VDD_IO = 1.8 V
VDD_IO = 2.5 V
VDD_IO = 3.3 V
VDD_IO = 1.8 V
VDD_IO = 2.5 V
VDD_IO = 3.3 V
VDD_IO = 1.8 V
VDD_IO = 2.5 V
VDD_IO = 3.3 V
VDD_IO = 1.8 V
VDD_IO = 2.5 V
VDD_IO = 3.3 V
VDD_IO = 1.8 V
VDD_IO = 2.5 V
VDD_IO = 3.3 V
VDD_IO = 1.8 V
VDD_IO = 2.5 V
VDD_IO = 3.3 V
VDD_IO = 1.8 V
VDD_IO = 2.5 V
VDD_IO = 3.3 V
VDD_IO = 1.8 V
VDD_IO = 2.5 V
VDD_IO = 3.3 V
VDD_IO = 1.8 V
VDD_IO = 2.5 V
VDD_IO = 3.3 V
VDD_IO = 1.8 V
VDD_IO = 2.5 V
VDD_IO = 3.3 V
VDD_IO = 1.8 V
VDD_IO = 2.5 V
VDD_IO = 3.3 V
7.1
Typical power test pattern (see Table 6);
VID = 70 mV,
All CMOS outputs terminated with 10 pF;
fPCLK = 4 MHz
fPCLK = 15 MHz
fPCLK = 4 MHz
fPCLK = 15 MHz
fPCLK = 8 MHz
fPCLK = 30 MHz
fPCLK = 8 MHz
fPCLK = 30 MHz
fPCLK = 20 MHz
fPCLK = 65 MHz
fPCLK = 20 MHz
fPCLK = 65 MHz
8.2
10.3
15.3
17.4
21
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
F/S at GND and RXEN at VDD
;
VIH = VDD, VIL = 0 V;
VDD = VDDPLLA = VDDPLLD = VDDLVDS
1ChM
2ChM
3ChM
8.9
12.3
12.8
16
10.7
13.5
19.3
23.3
28.4
9.7
Alternating 1010 Test pattern (see Table 9);
All CMOS outputs terminated with 10 pF;
F/S and RXEN at VDD; VIH = VDD, VIL = 0 V;
VDD = VDDPLLA = VDDPLLD = VDDLVDS
25
28.6
35.2
Typical power test pattern (see Table 7);
VID = 70 mV,
All CMOS outputs terminated with 10 pF;
11.3
14
F/S at GND and RXEN at VDD
;
20.4
24.3
29.1
12.9
15.6
20.3
30.4
37.2
45.9
15.5
19
VIH = VDD, VIL = 0 V;
VDD = VDDPLLA = VDDPLLD = VDDLVDS
Total
Average
Supply
Current
IDD
17.3
19.3
26.9
40.4
48.3
61.7
Alternating 1010 Test pattern (see Table 9);
All CMOS outputs terminated with 10 pF;
F/S and RXEN at VDD; VIH = VDD, VIL = 0 V;
VDD = VDDPLLA = VDDPLLD = VDDLVDS
Typical power test pattern (see Table 8);
VID = 70 mV,
All CMOS outputs terminated with 10 pF;
23.5
32.9
39.9
48.7
21.4
26.4
33.1
49.9
62.5
77.9
30
F/S at GND and RXEN at VDD
;
VIH =VDD, VIL = 0 V;
VDD = VDDPLLA = VDDPLLD = VDDLVDS
29.7
33.7
41.3
66.9
80.3
102.3
80
Alternating 1010 Test pattern (see Table 9);
All CMOS outputs terminated with 10 pF;
F/S and RXEN at VDD; VIH = VDD, VIL = 0 V;
VDD = VDDPLLA = VDDPLLD = VDDLVDS
CLK and D[0:2] inputs are left open;
Standby mode; RXEN = VIH
μA
μA
All control inputs held static high or low;
All CMOS outputs terminated with 10 pF;
VIH = VDD, VIL = 0V; VDD = VDDPLLA = VDDPLLD = VDDLVDS
Shutdown mode; RXEN = VIL
0.3
6
(1) All typical values are at 25°C with VDD = VDDPLLA = VDDPLLD = VDDLVDS = 1.8 V.
(2) All max values are at the worst-case process corner, voltage, and temperature. The VDD_IO voltage is the described voltage + 10%.
Copyright © 2012, Texas Instruments Incorporated
15
SN65LVDS314
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
www.ti.com.cn
MAX UNIT
INPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK–
Vthstby Input voltage common mode threshold to
switch between receive/acquire mode and
standby mode
RXEN at VDD
1.3
0.9×VDDLVDS
V
VTHL
Low-level differential input voltage
threshold
VD0+–VD0–, VD1+–VD1–, VD2+–VD2–
VCLK+–VCLK-
,
–40
mV
mV
μA
VTHH High-level differential input voltage
threshold
40
75
II+, II– Input leakage current
VDD=1.95 V; VI+ = VI–;
VI = 0.4 V and VI = 1.5 V
IIOFF
RID
Power-off input current
VDD=GND; VI = 1.5V
–75
122
μA
Differential input termination resistor value
Input capacitance
78
21
100
1
Ω
CIN
Measured between input terminal
and GND
pF
ΔCIN
Input capacitance variation
Within one signal pair
Between all signals
0.2
1
pF
RBBDC Pull-up resistor for standby detection
30
39
kΩ
LS0, LS1, CPOL, SWAP, RXEN, F/S
VIK
Input clamp voltage
II= –18 mA, VDD=VDD(min)
-1.2
100
V
IICMOS Input current(2)
0 V ≤ VDD≤ 1.95 V; VI=GND or
nA
VI=1.95 V
CIN
IIH
Input capacitance
2
pF
nA
High-level input current
Low-level input current
High-level input voltage
Low-level input voltage
VIN = 0.7 × VDD
VIN = 0.3 × VDD
-200
–200
200
200
IIL
VIH
VIL
0.7×VDD
0
VDD
V
0.3×VDD
(1) All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
(2) Do not leave any CMOS Input unconnected or floating to minimize leakage currents. Every input must be connected to a valid logic level
VIH or VOL while power is supplied to VDD
.
16
Copyright © 2012, Texas Instruments Incorporated
SN65LVDS314
www.ti.com.cn
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
OUTPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, CPE
1-ChM, F/S=L, IOH= –250 μA
2-or 3-ChM, F/S=L, IOH= –500 μA
1-ChM, F/S=H, IOH= –500 μA
2- or 3-ChM, F/S=H, IOH= –1.33 mA
1-ChM, F/S=L, IOL= 250 μA
2- or 3-ChM, F/S=L, IOL= 500 μA
1-ChM, F/S=H, IOL= 500 μA
2- or 3-ChM, F/S=H, IOL= 1.33 mA
1-ChM, F/S=L
VOH High-level output voltage
VOL Low-level output voltage
0.8×VDD_IO
VDD_IO
V
V
0
0.5
–250
–500
IOH
High-level output current
Low-level output current
2- or 3-ChM, F/S=L; 1-ChM, F/S=H
2- or 3-ChM, F/S=H
–1333
μA
1-ChM, F/S=L
250
500
IOL
2- or 3-ChM, F/S=L; 1-ChM, F/S=H
2- or 3-ChM, F/S=H
1333
Copyright © 2012, Texas Instruments Incorporated
17
SN65LVDS314
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
www.ti.com.cn
MAX UNIT
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK–
tR/F
Input rise and fall time
RXEN at VDD; see figure 6-2
800
100
ps
ps
Input rise or fall time
mismatch between all
SubLVDS inputs
tR(n)– tR(m) and tF(n)- tF(m) with n=D0, D1, D2, or CLK
and m=D0, D1, D2, or CLK
ΔtR/F
–100
R[7:0], G[7:0], B[7:0], VS, HS, DE, PCLK, CPE
1-channel mode, F/S=L
2-channel mode, F/S=L
3-channel mode, F/S=L
1-channel mode, F/S=H
2-channel mode, F/S=H
3-channel mode, F/S=H
8
4
16
8
Rise and fall time 20%–
80% of VDD_IO
CL = 10 pF(3)
see Figure 9
4
8
tR/F
ns
(2)
4
8
1.3
1.3
45%
48%
41%
–2
3
3
1-channel and 3-channel mode
CPOL=VIL, 2-channel mode
CPOL=VIH, 2-channel mode
50%
53%
47%
55%
59%
52%
2
tOUTP
PCLK output duty cycle
1-channel mode, F/S=L
1-channel mode, F/S=H or
2-channel mode, F/S=L or
3-channel mode, F/S=L
Output skew between PCLK
and R[0:7], G[0:7], B0:7],
HS, VS, and DE
–1
1
tOSK
see Figure 9
ns
2-channel mode, F/S=H or
3-channel mode, F/S=H
–0.5
0.5
INPUT TO OUTPUT RESPONSE TIME
Propagation delay time from RXEN at VDD, VIH=VDD, VIL=GND, CL=10 pF,
tPD(L)
1.4/fPCLK
1.9/fPCLK
2.5/fPCLK
s
CLK+ input to PCLK output
See Figure 14
RXEN glitch to suppress
pulse width(4)
VIH=VDD, VIL=GND, RXEN toggles between VIL and VIH
See Figure 15 and Figure 16
;
tGS
3.8
2
μs
ms
Enable time from power
down (↑RXEN)
Time from RXEN pulled high to data outputs enabled and
outputs valid data; See Figure 16
tpwrup
RXEN is pulled low during receive mode; time
measurement until all outputs held static:
R[0:7]=G[0:7]=B[0:7]=VS=HS=high, DE=PCLK=low and
PLL is Shutdown; See Figure 16
Disable time from active
mode (↓RXEN)
tpwrdn
11
2
μs
RXEN at VDD; device is in standby; time measurement
from CLK input starts switching to PCLK and data outputs
enabled and outputting valid data; See Figure 17
Enable time from Standby
(↑↓CLK)
twakeup
ms
RXEN at VDD; device is receiving data; time
measurement from CLK input signal stops (input open or
input common mode VICM exceeds threshold voltage
Vthstby) until all outputs held static:
Disable time from active
mode (CLK transitions to
high-impedance)
tstandby
3
μs
R[0:7]=G[0:7]=B[0:7]=VS=HS=high,
DE=PCLK=low and PLL is Shutdown;
See Figure 17
2-ChM; fPCLK=22MHz
0.087×fPCLK
0.075×fPCLK
Tested from CLK input to
PCLK output
fBW
PLL bandwidth(5)
MHz
3-ChM; fPCLK=65MHz
(1) All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
(2) tR/F depends on the F/S setting and the capacitive load connected to each output. Some application information of how to calculate tR/F
based on the output load and how to estimate the timing budget to interconnect to an LCD driver are provided in the application section
near the end of this data sheet.
(3) The output rise and fall time is optimized for an output load of 10 pF. This model does not take into account trace or connector loading,
so the actual rise and fall times in different systems will vary.
(4) The RXEN input incorporates a glitch-suppression logic to disregard short input pulses. tGS is the duration of either a high-to-low or low-
to-high transition that is suppressed.
(5) When using the SN65LVDS314 receiver in conjunction with the SN65LVDS301 transmitter in one link, the PLL bandwidth of the
SN65LVDS314 receiver always exceed the bandwidth of the SN65LVDS301 transmit PLL. This ensures stable PLL tracking under all
operating conditions and maximizes the receiver skew margin.
18
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9.0
8.5
12
11
10
8 MHz
9 %
20 MHz
8.7 %
4 MHz
9 %
Spec Limit
1 ChM
Spec Limit
2 ChM
Spec Limit
3 ChM
8.0
7.5
7.0
15 MHz
8.1 %
9
8
7
6
5
30 MHz
8.1 %
65 MHz
7.5 %
6.5
6.0
4
0
70
50
60
30
40
20
0
10
100
200
300
400
500
600
700
PCLK - Frequency - MHz
PLL - Frequency - MHz
Figure 6. SN65LVDS314 PLL Bandwidth (also showing the SN65LVDS301 PLL bandwidth)
TIMING CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
1ChM: x=0..29, fPCLK=15 MHz;
fCLK=15 MHz(4)
630
RXEN at VDD, VIH=VDD
,
fCLK=4 MHz to 15 MHz(5)
VIL=GND, RL=100 Ω, test setup
as in Figure 8, test pattern as in
Table 11
1
- 480 ps
- 480ps
- 410ps
2 · 30 · fCLK
2ChM: x = 0..14,
fPCLK =30 MHz
RXEN at VDD, VIH=VDD,
VIL=GND, RL=100 Ω, test setup
as in Figure 8, test pattern as in
Table 12
fCLK=30 MHz(4)
fCLK=8 MHz to 30 MHz(5)
630
Receiver input skew
margin; see (3) and
Figure 21
tRSKMx
1
ps
(1) (2)
2 ·15 · fCLK
3ChM:
fCLK= 65 MHz(4)
360
RXEN at VDD, VIH=VDD
,
fCLK = 20 MHz to 65
MHz(5)
VIL=GND, test setup as in
Figure 8, test pattern as in
Table 13
1
2 ·10 · fCLK
(1) Receiver Input Skew Margin (tRSKM) is the timing margin available for transmitter output pulse position (tPPOS), interconnect skew, and
interconnect inter-symbol interference. tRSKM represents the reminder of the serial bit time not taken up by the receiver strobe
uncertainty;. The tRSKM assumes a bit error rate better than 10-12
.
(2) tRSKM is indirectly proportional to the internal set-up and hold time uncertainty, ISI and duty cycle distortion from the front end receiver,
the skew missmatch between CLK and data D0, D1, and D2, as well as the PLL cycle-to-cycle jitter.
(3) This includes the receiver internal set-up and hold time uncertainty, all PLL related high-frequency random and deterministic jitter
components that impact the jitter budget, ISI and duty cycle distortion from the front end receiver, and the skew between CLK and data
D0, D1, and D2; The pulse position min/max variation is given with a bit error rate target of 10–12; Measurements of the total jitter are
taken over a sample amount of > 10–12 samples.
(4) The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temp ranges.
(5) These Minimum and Maximum Limits are simulated only.
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PARAMETER MEASUREMENT INFORMATION
SN65LVDS314
V
DDPLLD
2
1
V
DDPLLA
V
DD
Noise
Generator
100 mV
1 W
10µF
V
DDLVDS
V
DD_IO
GND
1.8V
Supply
Note: The generator regulates the
1
1.6 H
noise amplitude at point to the
target amplitude given under the table
Recommended Operating Conditions
Figure 7. Power Supply Noise Test Set-Up
To measure tRSKM, CLK is advanced or delayed with respect to data until errors are observed at the receiver outputs. The advance
or delay is then reduced until there are no data errors observed over 10-12 serial bit times. The magnitude of the advance or delay
is tRSKM
Programmable delay
CLK
D1
CLK and Data
Pattern
Generator
DUT:
SN65LVDS314
Bit error
Detector
D2
D3
Ideal receiver strobe position
tPG_ERROR
TRSKM(p)
C
TRSKM(n)
tbit
tRSKM
tPG_ERROR
- is the smaller of the two measured values tRSKM(p) and tRSKM(n)
- Test equipment (pattern generator) intrinsic output pulse position timing uncertainty
- serial bit time
tbit
C
- LVDS314 set-up and hold-time uncertainty
Note: C can be derived by subtracting the receiver skew margin tRSKM(p) + tRSKM(p) from one serial bit time
Figure 8. Jitter Budget
20
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ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
PARAMETER MEASUREMENT INFORMATION (continued)
t
F
t
setup
80% (VOH-VOL
20% (VOH-VOL
)
)
R[7:0], G[7:0],
B[7:0], HS, VS, DE
t
hold
t
OSK
t
R
V
OH
80% (VOH-VOL
)
PCLK
(CPOL=0)
50% (V - –V
)
OH OL
20% (VOH-VOL
)
V
OL
t
R
t
F
Note:
The Set-up and Hold-time of CMOS outputs R[7:0], G[7:0],
B[7:0], HS, VS, and DE in relation to PCLK can be
calulated by:
1
t
=
-t
- t
- Dt
DUTP
S&H
REF OSK
2 -r
PCLK
Figure 9. Output Rise/Fall, Setup/Hold Time
V
– V
, V
– V
CLK–
Dx+
Dx–
CLK+
100%(V
)
IC
t
f
t
r
80%(V
)
ID
0V
20%(V
0%(V
)
ID
)
ID
Figure 10. SubLVDS Differential Input Rise and Fall Time Defintion
CLK+, Dx+
VDDLVDS
RID /2
RBBDC
Gain
Stage
RID/2
CLK–, Dx–
Standby
detection
line end
termination
ESD
Figure 11. Equivalent Input Circuit Design
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PARAMETER MEASUREMENT INFORMATION (continued)
SWAP,
CPOL, LSx,
RXEN, F/S
I
ICMOS
CMOS Input
CLK+, Dx+
(V +V )/2
I+ I-
I
I+
RGB, VS,
HS, DE,
CPE, PCLK
V
ICMOS
I
O
V
I
ID
I-
CLK-, Dx-
V
I+
V
V
ICM
O
V
I-
SubLVDS Input
CMOS Output
Figure 12. I/O Voltage and Current Definition
RGB, VS,
HS, DE,
CPE, PCLK
V
O
SN65LVDS314
CL=10 pF
Figure 13. CMOS Output Test Circuit, Signal and Timing Definition
22
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ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
PARAMETER MEASUREMENT INFORMATION (continued)
Pixel(n)
Pixel(n–1)
Pixel(n+1)
R7(n+1)
R7(n–1)
R7(n)
CP R7
R7(n–2)
D0+
R7 R6 R5 R4
CP R7
CLK–
CLK+
tPD(L)
VDD/2
PCLK
(CPOL = 0)
Pixel(n–1)
CMOS Data Out
R7(n–3)
R7(n–1)
R7
R6
R6(n–3)
R6(n–1)
Figure 14. Propagation Delay Input to Output (LS0=LS1=0)
/2
V
DD
RXEN
t
GS
CLK
t
PLL
PLL Approaches Lock
VCO Internal Signal
t
pwrup
PCLK
R[7:0], G[7:0], B[7:0], VS, HS
DE
Figure 15. Receiver Phase Lock Loop Set TIme and Receiver Enable Time
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PARAMETER MEASUREMENT INFORMATION (continued)
20 ns
<
3 ms
2 ms
Glitch shorter
than t will be
GS
ignored
less than 20ns
Spike will be
rejected
Glitch shorter
than t will be
GS
ignored
RXEN
t
pwrup
t
pwrdn
PCLK
t
I
GS
CC
t
GS
CLK
RX
RX disabled
turns
OFF
Receiver disabled
(OFF)
Receiver enabled
(ON)
Receiver aquires lock
(OFF)
Figure 16. Receiver Enable/Disable Glitch Suppression Time
CLK
t
t
standby
wakeup
PCLK
R[7:0], G[7:0], B[7:0], VS, HS,
RX enabled;
output data
invalid
RX
disabled
(OFF)
RX enabled
output data valid
Receiver aquires lock,
outputs still disabled
Receiver disabled
(OFF)
Figure 17. Standby Detection
POWER CONSUMPTION TESTS
Table 5 shows an example test pattern word.
Table 5. Example Test Pattern Word
Word R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x7C3E1E7
7
C
3
E
1
E
7
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
0
0
VS HS DE
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
24
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ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
TYPICAL IC POWER CONSUMPTION TEST PATTERN
Typical power-consumption test patterns consist of sixteen 30-bit receive words in 1-channel mode, eight 30-bit
receive words in 2-channel mode and five 30-bit receive words in 3-channel mode. The pattern repeats itself
throughout the entire measurement. It is assumed that every possible code on the RGB outputs has the same
probability to occur during typical device operation.
Table 6. Typical IC Power Consumption Test Pattern,
1-Channel Mode
Word Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
0x0000007
0xFFF0007
0x01FFF47
0xF0E07F7
0x7C3E1E7
0xE707C37
0xE1CE6C7
0xF1B9237
0x91BB347
0xD4CCC67
0xAD53377
0xACB2207
0xAAB2697
0x5556957
0xAAAAAB3
0xAAAAAA5
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Table 7. Typical IC Power Consumption Test Pattern,
2-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
3
4
5
6
7
8
0x0000001
0x03F03F1
0xBFFBFF1
0x1D71D71
0x4C74C71
0xC45C451
0xA3aA3A5
0x5555553
Table 8. Typical IC Power Consumption Test Pattern,
3-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
3
4
5
0xFFFFFF1
0x0000001
0xF0F0F01
0xCCCCCC1
0xAAAAAA7
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MAXIMUM POWER CONSUMPTION TEST PATTERN
The maximum (or worst-case) power consumption of the SN65LVDS314 is tested using the two different test
pattern shown in table. Test patterns consist of sixteen 30-bit receive words in 1-channel mode, eight 30-bit
receive words in 2-channel mode, and five 30-bit receive words in 3-channel mode. The pattern repeats itself
throughout the entire measurement. It is assumed that every possible code on RGB outputs has the same
probability to occur during typical device operation.
Table 9. Worst-Case Power Consumption Test Pattern
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
0xAAAAAA5
0x5555555
Table 10. Worst-Case Power Consumption Test Pattern
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
0x0000000
0xFFFFFF7
OUTPUT SKEW PULSE POSITION and JITTER PERFORMANCE
The following test patterns are used to measure the output skew pulse position and the jitter performance of the
SN65LVDS314. The jitter test pattern stresses the interconnect, particularly to test for ISI, using very long run-
lengths of consecutive bits, and incorporating very high and low data rates, maximizing switching noise. Each
pattern is self-repeating for the duration of the test.
Table 11. Receive Jitter Test Pattern, 1-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
0x0000001
0x0000031
0x00000F1
0x00003F1
0x0000FF1
0x0003FF1
0x000FFF1
0x0F0F0F1
0x0C30C31
0x0842111
0x1C71C71
0x18C6311
0x1111111
0x3333331
0x2452413
0x22A2A25
0x5555553
0xDB6DB65
0xCCCCCC1
0xEEEEEE1
0xE739CE1
0xE38E381
0xF7BDEE1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
26
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ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
Table 11. Receive Jitter Test Pattern, 1-Channel
Mode (continued)
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
24
25
26
27
28
29
30
31
32
0xF3CF3C1
0xF0F0F01
0xFFF0001
0xFFFC001
0xFFFF001
0xFFFFC01
0xFFFFF01
0xFFFFFC1
0xFFFFFF1
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Table 12. Receive Jitter Test Pattern, 2-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
0x000FFF3
0x8008001
0x0030037
0xE00E001
0x00FF001
0x007E001
0x003C001
0x0018001
0x1C7E381
0x3333331
0x555AAA5
0x6DBDB61
0x7777771
0x555AAA3
0xAAAAAA5
0x5555553
0xAAA5555
0x8888881
0x9242491
0xAAA5571
0xCCCCCC1
0xE3E1C71
0xFFE7FF1
0xFFC3FF1
0xFF81FF1
0xFE00FF1
0x1FF1FF1
0xFFCFFC3
0x7FF7FF1
0xFFF0007
0xFFFFFF1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
28
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SN65LVDS314
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ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
Table 13. Receive Jitter Test Pattern, 3-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
2
0x0000001
3
0x0000003
4
0x0101013
5
0x0303033
6
0x0707073
7
0x1818183
8
0xE7E7E71
9
0x3535351
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
0x0202021
0x5454543
0xA5A5A51
0xADADAD1
0x5555551
0xA6A2AA3
0xA6A2AA5
0x5555553
0x5555555
0xAAAAAA1
0x5252521
0x5A5A5A1
0xABABAB1
0xFDFCFD1
0xCAAACA1
0x1818181
0xE7E7E71
0xF8F8F81
0xFCFCFC1
0xFEFEFE1
0xFFFFFF1
0xFFFFFF5
0xFFFFFF5
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TYPICAL CHARACTERISTIC CURVES
The SN65LVDS314 device has very similar parametric curves as the SN65LVDS302. Please refer to this section
in the SN65LVDS302 datasheet (SLLS733) for a general understanding of SN65LVDS314 characteristics.
30
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ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
APPLICATION INFORMATION
Preventing Increased Leakage Currents in Control Inputs
A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. Do not leave any CMOS
input unconnected or floating. Every input must be connected to a valid logic level VIH or VOL while power is
supplied to VDD. This also minimizes the power consumption of standby and power down mode.
Power Supply Design Recommendation
For a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all
ground terminals directly to this plane.
SN65LVDS314 DECOUPLING RECOMMENDATION
The SN65LVDS314 was designed to operate reliably in a constricted environment with other digital switching
ICs. In many designs, the SN65LVDS314 often shares a power supply with various other ICs. The
SN65LVDS314 can operate with power supply noise as specified in Recommend Device Operating Conditions.
To minimize the power supply noise floor, provide good decoupling near the SN65LVDS314 power pins. The use
of four ceramic capacitors (two 0.01 μF and two 0.1 μF) provides good performance. At the very least, it is
recommended to install one 0.1 μF and one 0.01 μF capacitor near the SN65LVDS314. To avoid large current
loops and trace inductance, the trace length between decoupling capacitor and IC power inputs pins must be
minimized. Placing the capacitor underneath the SN65LVDS314 on the bottom of the PCB is often a good
choice.
VGA APPLICATION
Figure 18 shows a possible implementation of a standard 640x480 VGA display. The LVDS301 interfaces to the
SN65LVDS314, which is the corresponding receiver device to deserialize the data and drive the display driver.
The pixel clock rate of 22 MHz assumes ~10% blanking overhead and 60 Hz display refresh rate. The application
assumes 24-bit color resolution. Also shown is how the application processor provides a powerdown (reset)
signal for both serializer and the display driver. The signal count over the Flexible Printed Circuit board (FPC)
could be further decreased by using the standby option on the SN65LVDS314 and pulling RXEN high with a 30
kΩ resistor to VDD
.
2x0.1uF
2x0.1uF
FPC
GND
2.7V
1.8V
GND
GND
2.7V
1.8V
GND
2x0.01uF
2x0.01uF
Application
Processor
(e.g. OMAP)
Video Mode Display
Driver
CLK+
CLK–
CLK+
CLK–
22MHz
D0+
D0–
D0+
D0–
330Mbps
330Mbps
PCLK
Pixel CLK
PCLK
22MHz
27
22MHz
27
D1+
D1–
D1+
D1–
D[7:0]
D[15:8]
D[23:16]
R[7:0]
G[7:0]
B[7:0]
R[7:0]
G[7:0]
B[7:0]
HS, VS, DE
HS, VS, DE
HS, VS, DE
SN65LVDS301
SN65LVDS314
1.8 V
1.8 V
If FPC wire count is critical, replace this
connection with a pull-up resistor at RXEN
Serial port interface
(3-wire IF)
3
Figure 18. Typical VGA Display Application
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DUAL LCD-DISPLAY APPLICATION
The example in Figure 19 shows a possible application setup driving two video-mode displays from one
application processor. The data rate of 330 Mbps at a pixel clock rate of 5.5 MHz corresponds to a 320x240
QVGA resolution at 60 Hz refresh rate and 10% blanking overhead.
2x0.1uF
2x0.1uF
FPC
GND
2. 7V
1. 8V
GND
GND
2. 7V
1. 8V
GND
2x0.01uF
2x0.01uF
Display Driver
1
Application
Processor
21
(e.g. OMAP )
CLK+
CLK-
CLK+
CLK-
5.5MHz
330Mbps
PCLK
PCLK
Pixel CLK
PCLK
5.5MHz
18+3
D0+
D0-
R[ 5: 0]
G[ 5: 0]
B[ 5: 0]
D0+
D0-
EN
SIN
SOUT
SCLK
D[ 5: 0]
D[ 11 : 6]
D[ 17: 12]
HS, VS, DE
R[ 5: 0]
G[ 5: 0]
B[ 5: 0]
HS, VS, DE
HS, VS, DE
SN65LVDS 301
SN65LVDS314
Display Driver
2
PCLK
EN
SIN
1.8V
1.8V
SOUT
SCLK
Figure 19. Example Dual-QVGA Display Application
TYPICAL APPLICATION FREQUENCIES
The SN65LVDS314 supports pixel clock frequencies from 4 MHz to 65 MHz over 1, 2, or 3 data lanes. Table 14
provides a few typical display resolution examples and shows the number of data lanes necessary to connect the
SN65LVDS314 with the display. The blanking overhead is assumed to be 20%. Often, blanking overhead is
smaller, resulting in a lower data rate. Furthermore, the examples in the table assumes a display frame refresh
rate of 60-Hz. The actual refresh rate may differ depending on the application-processor clock implementation.
Table 14. Typical Application Data Rates and Serial Lane Usage
Display Screen
Resolution
Visible
Pixel Count Overhead
Blanking
Display
Refresh
Rate
Pixel Clock Frequency
[MHz]
Serial Data Rate Per Lane
1-ChM
2-ChM
3-ChM
176x220 (QCIF+)
240x320 (QVGA)
640x200
38,720
76,800
20%
20%
20%
20%
20%
20%
20%
20%
20%
20%
20%
20%
20%
90 Hz
60 Hz
60 Hz
60 Hz
60 Hz
60 Hz
60 Hz
60 Hz
60 Hz
60 Hz
60 Hz
60 Hz
60 Hz
4.2 MHz
5.5 MHz
125 Mbps
166 Mbps
276 Mbps
316 Mbps
335 Mbps
332 Mbps
432 Mbps
442 Mbps
128,000
146,432
154,880
153,600
200,000
204,800
307,200
327,680
409,920
480,000
786,432
9.2 MHz
138 Mbps
158 Mbps
167 Mbps
166 Mbps
216 Mbps
221 Mbps
332 Mbps
354 Mbps
443 Mbps
352x416 (CIF+)
352x440
10.5 MHz
11.2 MHz
11.1 MHz
14.4 MHz
14.7 MHz
22.1 MHz
23.6 MHz
29.5 MHz
34.6 MHz
56.6 MHz
320x480 (HVGA)
800x250
640x320
640x480 (VGA)
1024x320
221 Mbps
236 Mbps
295 Mbps
346 Mbps
566 Mbps
854x480 (WVGA)
800x600 (SVGA)
1024x768 (XGA)
32
Copyright © 2012, Texas Instruments Incorporated
SN65LVDS314
www.ti.com.cn
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
CALCULATION EXAMPLE: HVGA DISPLAY
The following calculation shows an example for a Half-VGA display with the following parameters:
Display Resolution:
Frame Refresh Rate:
480 x 320
58.4 Hz
Hsync =5
HFP=20
Visible area = 480 Columns
Horizontal Visible Pixel:
Horizontal Front Porch:
Horizontal Sync:
480 columns
20 columns
5 columns
3 columns
Vsync =5
VBP=3
Horizontal Back Porch:
Visible area
=320 lines
Visible area
Vertical Visible Pixel:
Vertical Front Porch:
Vertical Sync:
320 lines
10 lines
5 lines
Entire Display
VFP=10
Vertical Back Porch:
3 lines
Figure 20. HVGA Display
Calculation of the total number of pixel and blanking overhead:
Visible Area Pixel Count: 480 × 320 = 153600 pixel
Total Frame Pixel Count: (480+20+5+3) × (320+10+5+3) = 171704 pixel
Blanking Overhead: (171704-153600) ÷ 153600 = 11.8 %
The application requires the following serial-link parameters:
Pixel Clk Frequency:
Serial Data Rate:
171704 × 58.4 Hz = 10.0 MHz
1-channel mode: 10.0 MHz × 30 bit/channel = 300 Mbps
2-channel mode: 10.0 MHz × 15 bit/channel = 150 Mbps
Copyright © 2012, Texas Instruments Incorporated
33
SN65LVDS314
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
www.ti.com.cn
How To Determine Interconnect Skew and Jitter Budget
Designing a reliable data link requires examining the interconnect skew and jitter budget. The sum of all
transmitter, PCB, connector, FPC, and receiver uncertainties must be smaller than the available serial bit time.
The highest pixel clock frequency defines the available serial bit time. The transmitter timing uncertainty is
defined by tPPOS in the transmitter data sheet. For a bit-error-rate target of ≤ 10-12, the measurement duration for
tPPOS is ≥ 1012. The SN65LVDS314 receiver can tolerate a maximum timing uncertainty defined by tRSKM. The
interconnect budget is calculated by:
tint erconnect = tRSKM - tPPOS
(1)
Example:
fPCLK(max) = 23 MHz (VGA display resolution, 60 Hz)
Transmission mode: 2-ChM; tPPOS(SN65LVDS301) = 330 ps
Target bit error rate: 10-12
tRSKM(SN65LVDS314) = 1/(2*15*fPCLK) – 480 ps = 969 ps
The interconnect budget for cable skew and ISI needs to be smaller than:
tint erconnect = tRSKM - tPPOS = 639ps
(2)
data transition
Ideal T
PPosn
Data Period /2
D0, D1, D2
Ideal receiver strobe position
TPPosn(max)
TPPosn(min)
RSKM
RSKM
RX internal sampling clock
(max)
R
R
(min)
SPosn
SPosn
Tppos: Transmitter output pulse position (min and max)
TPPosx(max) -TPPosx(min) = TJTXPLL(non-trackable) + tTXskew + tTXDJ
RSKM: Receiver Skew Margin
RSPosn: Receiver input strobe position (min and max)
RSKM = SKEWPCB + XTALKPCB + ISIPCB
R
SPosn(max) - RSPosn(min) = SkewRX + S&HRX + TJ(RXPLL(non-trackable)
:
non-trackable TX PLL jitter; this jitter is the integration
f
TJ
SKEW
XTALK
ISI
: PCB induced Skew (trace + connector);
PCB
TXPLL(non-trackable)
of total jitter above the receiver PLL bandwidth
>
TXPLL
TJ
(BWRX);
;
:
PCB induced cross-talk;
PCB
TJ=RJ[ps-rms]*14 DJ[ps]
transmitter output skew (skew between CLK and data)
+
:
Inter-symbol interference of PCB; is
Skew
S&H
TJ
: Receiver input skew (skew between CLK and Dx input)
RX
PCB
t
:
TXskew
dependent on interconnect frequency loss; may be
:
Receiver input latch Sample
&
Hold uncertainty
RX
zero for short interconnects.
:
Intrinsic RX PLL jitter above RX PLL bandwidth; PLL
>
TJ
(RXPLL(non-trackable)
); TJ=RJ[ps-rms]*14
t
Transmitter Deterministic JItter of TX output stage (includes TX
TXIDJ
Intersymbol Interference ISI)
f(BW
+ DJ[ps]
RX
Figure 21. Jitter Budget
34
Copyright © 2012, Texas Instruments Incorporated
SN65LVDS314
www.ti.com.cn
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
F/S-PIN SETTING AND CONNECTING THE SN65LVDS314 TO AN LCD DRIVER
NOTE
Receiver PLL tracking: To maximize the design margin for the interconnect, good RX
PLL tracking of the TX PLL is important. FlatLink3G requires the RX PLL to have a
bandwidth higher than the bandwidth of the TX PLL. The SN65LVDS314 PLL design is
optimized to track the SN65LVDS0301 PLL particularly well, thus providing a very large
receiver skew margin. A FlatLink3G-compliant link must provide at least ±225 ppm of
receiver skew margin for the interconnect.
It is important to understand the tradeoff between power consumption, EMI, and maximum speed when selecting
the F/S signal. It is beneficial to choose the slowest rise time possible to minimize EMI and power consumption.
Unfortunately a slower rise time also reduces the timing margin left for the LCD driver. Hence it is necessary to
calculate the timing margin to select the correct F/S pin setting.
The output rise time depends on the output driver strength and the output load. An LCD driver typical capacitive
load is assumed with ~10pF. The higher the capacitive load, the slower will be the rise time. Rise time of the
SN65LVDS314 is measured as the time duration it takes the output voltage to rise from 20% of VDD and 80% of
VDD and fall time is defined as the time for the output voltage to transition from 80% of VDD down to 20%.
Within one mode of operation and one F/S pin setting, the rise time of the output stage is fixed and does not
adjust to the pixel frequency. Due to the short bit time at very fast pixel clock speeds and the real capacitive load
of the display driver, the output amplitude might not reach VDD and GND saturation fully. To ensure sufficient
signal swing and verify the design margin, it becomes necessary to determine that the output amplitude under
any circumstance reaches the display driver’s input stage logic threshold (usually 30% and 70% of VDD).
Figure 22 shows a worst-case rise time simulation assuming a LCD driver load of 16pF at VGA display resolution
and a VDD_IO of 1.8 V. PCLK is the fastest switching output. With F/S set to GND (Figure 22-a), the PCLK output
voltage amplitude is significantly reduced. The voltage amplitude of the output data RGB[7:0], VS, HS, and DE
shows less amplitude attenuation because these outputs carry random data pattern and toggle equal or less than
half of the PCLK frequency. It is necessary to determine the timing margin between the LVDS314 output and
LCD driver input.
Application: VGA (2-channel mode);F/S set to GND; Display driver load ~16 pF
Application: VGA (2-channel mode);F/S set to VDD; Display driver load ~16 pF
2.0V
1.8V
1.6V
1.4V
1.2V
1.0V
0.8V
0.6V
0.4V
0.2V
0.0V
2.0V
1.8V
1.6V
1.4V
1.2V
1.0V
0.8V
0.6V
0.4V
0.2V
0.0V
The data signal has a slower maximum switching
frequency, and therefore drives a larger amplitude
than the clock signal
(
100ns
150ns
200ns
250ns
300ns
350ns
400ns
450ns
500ns
550ns
600ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
450ns
500ns
550ns
600ns
clk 22 MHz, F/S=0, CL=16 pF
data 22 Mbps, F/S=0, CL=16 pF
clk 22 MHz, F/S=1, CL=16 pF
data 22 Mbps, F/S=1, CL=16 pF
(b)
(a)
Figure 22. Output Amplitude as a Function of Output Toggling Frequency,
Capacitive Load and F/S Setting
Copyright © 2012, Texas Instruments Incorporated
35
SN65LVDS314
ZHCS415A –AUGUST 2012–REVISED SEPTEMBER 2012
www.ti.com.cn
HOW TO DETERMINE THE LCD DRIVER TIMING MARGIN
To determine the timing margin, it is necessary to specify the frequency of operation, identify the set-up and hold
time of the LCD driver, and specify the output load of the SN65LVDS314 as a combination of the LCD driver
input parasitics plus any capacitance caused by the connecting PCB trace. Furthermore, the setting of pin F/S
and the SN65LVDS314 output skew impact the margin. The total remaining design margin calculates as
following:
t
C
rise(max)
LOAD
1
* Ťt Ť
t
+
* t
*
DM
DUTP(max_error)
OSK
2 ƒ
10 pF
PCLK
(3)
where:
tDM – Design margin
fPCLK – Pixel clock frequency
tDUTP(max_error) – maximum duty cycle error
trise(max) – maximum rise or fall time; see tR/F under switching characteristics
CL – parasitic capacitance (sum of LCD driver input parasitics + connecting PCB trace)
tskew – clock to data output skew SN65LVDS314
Example:
At a pixel clock frequeny of 5.5MHz (QVGA), and an assumed LCD driver load of 15 pF, the remaining timing
margin is:
Ťt
(max) * 50Ť
DUTP
5%
100%
1
t
+
t
+
+ 9.1ns
DUTP(max_error)
1
PCLK
100%
5.5MHz
16ns
15pF
(FńS+GND)
t
+
* 9ns *
* 500ps + 57.3ns
DM
2 5.5MHz
10pF
As long as the set-up and hold time of the LCD driver are each less than 57 ns, the timing budget is met
sufficiently.
36
Copyright © 2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65LVDS314RSKR
ACTIVE
VQFN
RSK
64
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
LVDS314
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LVDS314RSKR
VQFN
RSK
64
2000
330.0
16.4
8.3
8.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2017
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RSK 64
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
SN65LVDS314RSKR
2000
Pack Materials-Page 2
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