SN65LVDS33PWRG4 [TI]
HIGH-SPEED DIFFERENTIAL RECEIVERS; 高速差分接收器型号: | SN65LVDS33PWRG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | HIGH-SPEED DIFFERENTIAL RECEIVERS |
文件: | 总23页 (文件大小:530K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
www.ti.com
SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
HIGH-SPEED DIFFERENTIAL RECEIVERS
The high-speed switching of LVDS signals usually
necessitates the use of a line impedance matching
resistor at the receiving-end of the cable or
transmission media. The SN65LVDT series of
receivers eliminates this external resistor by
integrating it with the receiver. The nonterminated
SN65LVDS series is also available for multidrop or
other termination circuits.
FEATURES
•
400-Mbps Signaling Rate(1) and 200-Mxfr/s
Data Transfer Rate
•
•
Operates With a Single 3.3-V Supply
-4 V to 5 V Common-Mode Input Voltage
Range
•
•
Differential Input Thresholds <±50 mV With 50
mV of Hysteresis Over Entire Common-Mode
Input Voltage Range
SN65LVDS33D, SN65LVDT33D
SN65LVDS33PW, SN65LVDT33PW
Integrated 110-Ω Line Termination Resistors
D OR PW PACKAGE
logic diagram (positive logic)
On LVDT Products
(TOP VIEW)
•
•
•
TSSOP Packaging (33 Only)
G
1B
1A
1Y
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
Complies With TIA/EIA-644 (LVDS)
G
4B
4A
4Y
G
SN65LVDT33 ONLY
Active Failsafe Assures a High-Level Output
With No Input
1A
1B
1Y
G
2Y
•
•
Bus-Pin ESD Protection Exceeds 15 kV HBM
Input Remains High-Impedance on Power
Down
2A
11 3Y
2A
2B
10
9
2B
GND
3A
3B
2Y
3Y
4Y
•
•
TTL Inputs Are 5 V Tolerant
Pin-Compatible With the AM26LS32,
3A
3B
4A
4B
SN65LVDS32B, µA9637, SN65LVDS9637B
(1)
The signalling rate of a line, is the number of voltage transitions
that are made per second expressed in the units bps (bits per
second).
DESCRIPTION
SN65LVDS34D, SN65LVDT34D
This family of four LVDS data line receivers offers the
widest common-mode input voltage range in the
industry. These receivers provide an input voltage
range specification compatible with a 5-V PECL
signal as well as an overall increased ground-noise
tolerance. They are in industry standard footprints
with integrated termination as an option.
D PACKAGE
(TOP VIEW)
logic diagram (positive logic)
V
1A
1B
2A
2B
1
2
3
4
8
7
6
5
CC
1A
1Y
2Y
1Y
1B
SN65LVDT34 ONLY
GND
Precise control of the differential input voltage
thresholds allows for inclusion of 50 mV of input
voltage hysteresis to improve noise rejection on
slowly changing input signals. The input thresholds
are still no more than ±50 mV over the full input
common-mode voltage range.
2A
2Y
2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
www.ti.com
SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVALIABLE OPTIONS(1)
PART
NUMBER OF
RECEIVERS
TERMINATION
RESISTOR
SYMBOLIZATION
NUMBER(2)
SN65LVDS33D
4
4
4
4
2
2
No
No
LVDS33
LVDS33
LVDT33
LVDT33
LVDS34
LVDS34
SN65LVDS33PW
SN65LVDTS33D
SN65LVDT33PW
SN65LVDS34D
SN65LVDT34D
Yes
Yes
No
Yes
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Add the suffix R for taped and reeled carrier.
DESCRIPTION (CONTINUED)
The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic
discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled
and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns
after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or
powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these
fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of
the SN65LVDS32B application note.
The intended application and signaling technique of these devices is point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media and the noise coupling to the environment.
The SN65LVDS33, SN65LVDT33, SN65LVDS34 and SN65LVDT34 are characterized for operation from –40°C
to 85°C.
Function Tables(1)
SN65LVDS33 and SN65LVDT33
DIFFERENTIAL INPUT ENABLES
VID = VA - VB
SN65LVDS34 and SN65LVDT34
OUTPUT
DIFFERENTIAL INPUT
VID = VA– VB
OUTPUT
G
H
X
H
X
H
X
L
G
X
L
Y
H
H
?
Y
H
?
VID ≥ –32 mV
VID ≥ –32 mV
–100 mV < VID≤ –32 mV
X
L
VID ≤ –100 mV
L
–100 mV < VID ≤ –32 mV
?
Open
H
X
L
L
VID ≤ –100 mV
L
X
H
X
L
Z
H
H
H
X
Open
(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
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SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
Attenuation
Network
6.5 kΩ
6.5 kΩ
V
CC
1 pF
60 kΩ
B Input
A Input
200 kΩ
3 pF
7 V
7 V
7 V
7 V
250 kΩ
LVDT Only 110 Ω
V
CC
V
CC
300 kΩ
(G Only)
100 Ω
Enable
Inputs
37 Ω
Y Output
7 V
7 V
300 kΩ
(G Only)
3
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SN65LVDS34, SN65LVDT34
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SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
(2)
Supply voltage range, VCC
–0.5 V to 4 V
–1 V to 6 V
Enables or Y
Voltage range
A or B
–5 V to 6 V
|VA– VB| (LVDT)
1 V
(3)
Electrostatic discharge
A, B, and GND
All pins(4)
Class 3, A: 15 kV, B: 500 V
±500 V
Charged-device mode
Continuous power dissipation
Storage temperature range
See Dissipation Rating Table
–65°C to 150°C
260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
DISSIPATION RATING TABLE
T
A ≤ 25°C
OPERATING FACTOR(1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
D8
PW16
D16
725 mW
5.8 mW/°C
6.2 mW/°C
7.6 mW/°C
377 mW
402 mW
494 mW
774 mW
950 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air
flow.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
VCC
VIH
VIL
Supply voltage
3
2
3.3
3.6
5
V
V
V
High-level input voltage
Low-level input voltage
Enables
Enables
LVDS
0
0.8
3
0.1
| VID
|
Magnitude of differential input voltage
V
LVDT
0.8
5
VI or VIC
TA
Voltage at any bus terminal (separately or common-mode)
Operating free-air temperature
–4
V
–40
85
°C
4
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SN65LVDS34, SN65LVDT34
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SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1) MAX
UNIT
VIT1
Positive-going differential input voltage threshold
50
VIB = –4 V or 5 V,
mV
Negative-going differential input voltage
threshold
See Figure 1 and Figure 2
See Table 1 and Figure 5
VIT2
–50
–32
VIT3
Differential input failsafe voltage threshold
–100
50
mV
mV
Differential input voltage hysteresis,
VIT1– VIT2
VID(HYS)
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = –4 mA
2.4
V
V
IOL = 4 mA
0.4
G at VCC, No load, Steady-state
G at GND
16
1.1
8
23
5
SN65LVDx33
Supply current
ICC
mA
SN65LVDx34
No load, Steady-state
12
VI = 0 V, Other input open
VI = 2.4 V, Other input open
VI = –4 V, Other input open
VI = 5 V, Other input open
VI = 0 V, Other input open
VI = 2.4 V, Other input open
VI = –4 V, Other input open
VI = 5 V, Other input open
VID = 100 mV, VIC = –4 V or 5 V
VID = 200 mV, VIC = –4 V or 5 V
VA or VB = 0 V or 2.4 V, VCC = 0 V
VA or VB = –4 or 5 V, VCC = 0 V
VA or VB = 0 V or 2.4 V, VCC = 0 V
VA or VB = –4 V or 5 V, VCC = 0 V
VIH = 2 V
±20
±20
±75
±40
±40
±40
±150
±80
±3
SN65LVDS
µA
Input current
(A or B inputs)
II
SN65LVDT
µA
SN65LVDS
SN65LVDT
µA
Differential input current
(IIA– IIB)
IID
1.55
2.22
±20
±50
±30
±100
10
mA
SN65LVDS
SN65LVDT
Power-off input current
(A or B inputs)
II(OFF)
µA
IIH
IIL
High-level input current (enables)
Low-level input current (enables)
High-impedance output current
µA
µA
µA
pF
VIL = 0.8 V
10
IOZ
CI
–10
10
Input capacitance, A or B input to GND
VI = 0.4 sin (4E6πt) + 0.5 V
5
(1) All typical values are at 25°C and with a 3.3 V supply.
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SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 3
MIN
2.5
TYP(1)
MAX UNIT
tPLH(1)
tPHL(1)
td1
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Delay time, failsafe deactivate time
4
4
6
6
ns
ns
ns
µs
ps
ps
ns
ns
ns
ns
ns
ns
ns
2.5
9
CL = 10 pF, See Figure 3
and Figure 6
td2
Delay time, failsafe activate time
0.3
1.5
tsk(p)
tsk(o)
tsk(pp)
tr
Pulse skew (|tPHL(1) - tPLH(1)|)
200
150
Output skew(2)
Part-to-part skew(3)
See Figure 3
See Figure 4
1
Output signal rise time
0.8
0.8
5.5
4.4
3.8
7
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tPZL
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance -to-high-level output
Propagation delay time, high-impedance-to-low-level output
9
9
9
9
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all receivers of a single device with all of their inputs driven
together.
(3) tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
PARAMETER MEASUREMENT INFORMATION
I
IA
A
B
V
O
Y
V
ID
V
IA
I
IB
(V + V )/2
V
O
IA
IB
V
IC
V
IB
Figure 1. Voltage and Current Definitions
6
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SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION (continued)
1000 Ω
100 Ω
†
100 Ω
V
ID
1000 Ω
V
O
10 pF,
+
V
IC
2 Places
–
10 pF
†
Remove for testing LVDT device.
V
IT1
0 V
V
ID
–100 mV
V
O
100 mV
0 V
V
ID
V
IT2
V
O
NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns.
Figure 2. VIT1 and VIT2 Input Voltage Threshold Test Circuit and Definitions
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SN65LVDS34, SN65LVDT34
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SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION (continued)
V
ID
V
IA
V
O
C
L
= 10 pF
V
IB
V
V
1.4 V
IA
1 V
IB
0.4 V
V
ID
0 V
−0.4 V
t
t
PLH
PHL
V
OH
80%
20%
80%
20%
1.4 V
V
O
V
OL
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulsewidth = 10 ±0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the
D.U.T.
Figure 3. Timing Test Circuit and Waveforms
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SN65LVDS34, SN65LVDT34
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SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION (continued)
B
1.2 V
500 Ω
A
10 pF
±
V
O
Inputs
G
V
TEST
G
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse
r
f
repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns . C includes instrumentation and fixture
L
capacitance within 0,06 mm of the D.U.T.
2.5 V
V
TEST
A
1 V
2 V
1.4 V
0.8 V
G
G
2 V
1.4 V
0.8 V
t
t
PLZ
PLZ
t
t
PZL
PZL
2.5 V
1.4 V
OL
OL
Y
V
V
+0.5 V
V
TEST
0
1.4 V
A
G
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
t
PHZ
G
t
PHZ
t
t
PZH
PZH
V
V
1.4 V
0
OH
OH
–0.5 V
Y
Figure 4. Enable/Disable Time Test Circuit and Waveforms
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SN65LVDS34, SN65LVDT34
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SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
Table 1. Receiver Minimum and Maximum VIT3
Input Threshold Test Voltages
APPLIED VOLTAGES(1)
RESULTANT INPUTS
VIA (mV)
–4000
–4000
4900
VIB (mV)
–3900
–3968
5000
VID (mV)
–100
–32
VIC (mV)
–3950
–3984
4950
Output
L
H
L
–100
–32
4968
5000
4984
H
(1) These voltages are applied for a minimum of 1.5 µs.
V
V
IA
–100 mV @ 250 KHz
IB
V
O
a) No Failsafe
V
IA
–32 mV @ 250 KHz
V
IB
V
O
Failsafe Asserted
b) Failsafe Asserted
Figure 5. VIT3 Failsafe Threshold Test
1.4 V
1 V
0.4 V
>1.5 µs
0 V
–0.2 V
–0.4 V
t
d1
t
d2
V
OH
1.4 V
V
OL
Figure 6. Waveforms for Failsafe Activate and Deactivate
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SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT CURRENT
5
4
3
V
T
A
= 3.3 V
= 25°C
V
CC
= 3.3 V
CC
T = 25°C
A
4
3
2
1
2
1
0
0
0
10
20
30
40
−40
−30
−20
−10
0
I
− Low-Level Output Current − mA
I
OH
− High-Level Output Current − mA
OL
Figure 7.
Figure 8.
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5
5
4.5
4
4.5
4
V
= 3 V
CC
V
= 3 V
CC
V
CC
= 3.3 V
V
CC
= 3.3 V
V
CC
= 3.6 V
V
CC
= 3.6 V
3.5
3
3.5
3
−50
0
50
100
−50
0
50
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 9.
Figure 10.
11
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SN65LVDS34, SN65LVDT34
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SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
FREQUENCY
140
120
V
= 3.3 V
100
80
CC
V
CC
= 3.6 V
60
V
CC
= 3 V
40
20
0
0
100
150
200
f − Switching Frequency − MHz
Figure 11.
APPLICATION INFORMATION
0.01 µF
≈3.6 V
16
V
CC
5 V
1
2
1B
0.1 µF
(see Note A)
1N645
(2 places)
100 Ω
1A
15
14
4B
4A
3
4
5
6
100 Ω
(see Note B)
1Y
G
V
CC
13
12
11
4Y
G
2Y
2A
See Note C
3Y
100 Ω
7
8
10
9
3A
3B
2B
100 Ω
GND
A. Place a 0.1-µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with
±10%.
C. Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 12. Operation With 5-V Supply
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SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
APPLICATION INFORMATION (continued)
RELATED INFORMATION
IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for
more information.
For more application guidelines, see the following documents:
•
•
•
•
•
•
Low-Voltage Differential Signalling Design Notes (SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
Reducing EMI With LVDS (SLLA030)
Slew Rate Control of LVDS Circuits (SLLA034)
Using an LVDS Receiver With RS-422 Data (SLLA031)
Evaluating the LVDS EVM (SLLA033)
ACTIVE FAILSAFE FEATURE
A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current
LVDS failsafe solutions require either external components with subsequent reductions in signal quality or
integrated solutions with limited application. This family of receivers has a new integrated failsafe that solves the
limitations seen in present solutions. A detailed theory of operation is presented in application note The Active
Failsafe Feature of the SN65LVDS32B, (SLLA082A).
The following figure shows one receiver channel with active failsafe. It consists of a main receiver that can
respond to a high-speed input differential signal. Also connected to the input pair are two failsafe receivers that
form a window comparator. The window comparator has a much slower response than the main receiver and it
detects when the input differential falls below 80 mV. A 600-ns failsafe timer filters the window comparator
outputs. When failsafe is asserted, the failsafe logic drives the main receiver output to logic high.
Output
Buffer
Main Receiver
+
_
A
B
R
Failsafe
Timer
Reset
A > B + 80 mV
+
_
Failsafe
B > A + 80 mV
+
_
Window Comparator
Figure 13. Receiver With Active Failsafe
ECL/PECL-TO-LVTTL CONVERSION WITH TI's LVDS RECEIVER
The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer of
choice for system designers. Designers know of the established technology and that it is capable of high-speed
data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like
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SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
APPLICATION INFORMATION (continued)
LVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be a design
option, designers have been able to take advantage of LVDS by implementing a small resistor divider network at
the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode LVDS receiver
(no divider network required) which can be connected directly to an ECL driver with only the termination bias
voltage required for ECL termination (VCC–2 V).
Figure 14 and Figure 15 show the use of an LV/PECL driver driving 5 meters of CAT-5 cable and being received
by TI's wide common-mode receiver and the resulting eye-pattern. The values for R3 are required in order to
provide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the
characteristic load impedance of 50 Ω. The R2 resistor is a small value and is intended to minimize any possible
common-mode current reflections.
V
V
CC
CC
R1 = 50 Ω
R2 = 50 Ω
I
I
CC
CC
V
B
5 Meters
of CAT-5
LV/PECL
LVDS
V
B
R3
R3
R1
R1
V
EE
R2
R3 = 240 Ω
Figure 14. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver
Figure 15. LV/PECL to Remote SN65LVDS33 at 500 Mbps Receiver Output (CH1)
TEST CONDITIONS
•
•
•
VCC = 3.3 V
TA = 25°C (ambient temperature)
All four channels switching simultaneously with NRZ data. Scope is pulse-triggered simultaneously with NRZ
data.
14
Submit Documentation Feedback
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
www.ti.com
SLLS490B–MARCH 2001–REVISED NOVEMBER 2004
APPLICATION INFORMATION (continued)
EQUIPMENT
•
•
•
Tektronix PS25216 programmable power supply
Tektronix HFS 9003 stimulus system
Tektronix TDS 784D 4-channel digital phosphor oscilloscope – DPO
Tektronix PS25216
Programmable
Power Supply
Tektronix HFS 9003
Stimulus System
Trigger
Tektronix TDS 784D 4-Channel
Digital Phosphor Oscilloscope
– DPO
Bench Test Board
Figure 16. Equipment Setup
100 Mbit/s
200 Mbit/s
Figure 17. Typical Eye Pattern SN65LVDS33
15
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
PACKAGING INFORMATION
Orderable Device
SN65LVDS33D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
8
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS33DG4
SN65LVDS33DR
SN65LVDS33DRG4
SN65LVDS33PW
SN65LVDS33PWG4
SN65LVDS33PWR
SN65LVDS33PWRG4
SN65LVDS34D
SOIC
SOIC
D
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS34DG4
SN65LVDS34DR
SN65LVDS34DRG4
SN65LVDT33D
SOIC
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
16
16
16
16
16
16
16
16
8
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDT33DG4
SN65LVDT33DR
SN65LVDT33DRG4
SN65LVDT33PW
SN65LVDT33PWG4
SN65LVDT33PWR
SN65LVDT33PWRG4
SN65LVDT34D
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDT34DG4
SN65LVDT34DR
SN65LVDT34DRG4
SOIC
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
(mm)
0
SN65LVDS33DR
SN65LVDS33PWR
SN65LVDS34DR
SN65LVDT33DR
SN65LVDT33PWR
SN65LVDT34DR
D
PW
D
16
16
8
SITE 27
SITE 60
SITE 60
SITE 60
SITE 60
SITE 60
6.5
6.67
6.4
10.3
5.4
2.1
1.6
2.1
2.1
1.6
2.1
8
8
8
8
8
8
16
12
12
16
12
12
Q1
Q1
Q1
Q1
Q1
Q1
12
12
16
12
12
5.2
D
16
16
8
6.5
10.3
5.4
PW
D
6.67
6.4
5.2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN65LVDS33DR
SN65LVDS33PWR
SN65LVDS34DR
SN65LVDT33DR
SN65LVDT33PWR
SN65LVDT34DR
D
PW
D
16
16
8
SITE 27
SITE 60
SITE 60
SITE 60
SITE 60
SITE 60
342.9
346.0
346.0
346.0
346.0
346.0
336.6
346.0
346.0
346.0
346.0
346.0
28.58
29.0
29.0
33.0
29.0
29.0
D
16
16
8
PW
D
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
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amplifier.ti.com
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Copyright © 2007, Texas Instruments Incorporated
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