SN65LVDS386DGGRG4 [TI]
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS; 高速差动线路接收器
| 型号： | SN65LVDS386DGGRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED DIFFERENTIAL LINE RECEIVERS |
| 文件： | 总21页 (文件大小：416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G–SEPTEMBER 1999–REVISED NOVEMBER 2004
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
FEATURES
’LVDS388A, ’LVDT388A
’LVDS386, ’LVDT386
DGG PACKAGE
(TOP VIEW)
•
Four- ('390), Eight- ('388A), or Sixteen- ('386)
DBT PACKAGE
(TOP VIEW)
Line Receivers Meet or Exceed the
Requirements of ANSI TIA/EIA-644 Standard
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
A1A
A1B
A2A
A2B
AGND
B1A
B1B
B2A
B2B
AGND
C1A
C1B
C2A
C2B
AGND
D1A
D1B
D2A
D2B
GND
•
•
•
Integrated 110-Ω Line Termination Resistors
on LVDT Products
Designed for Signaling Rates (1) Up To
630 Mbps
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A1A
A1B
A2A
A2B
A3A
A3B
A4A
A4B
B1A
B1B
B2A
B2B
B3A
B3B
B4A
B4B
C1A
C1B
C2A
C2B
C3A
C3B
C4A
C4B
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
GND
2
V
CC
2
V
CC
3
ENA
A1Y
A2Y
ENB
B1Y
B2Y
3
V
CC
4
4
GND
ENA
A1Y
A2Y
A3Y
A4Y
ENB
B1Y
B2Y
B3Y
B4Y
GND
5
5
SN65 Version's Bus-Terminal ESD Exceeds
15 kV
6
6
7
7
•
•
•
Operates From a Single 3.3-V Supply
8
8
Typical Propagation Delay Time of 2.6 ns
9
DGND
9
10
11
12
13
14
15
16
17
18
19
Output Skew 100 ps (Typ) Part-To-Part Skew
Is Less Than 1 ns
DV
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CC
DGND
C1Y
C2Y
ENC
D1Y
D2Y
END
•
•
•
•
LVTTL Levels Are 5-V Tolerant
Open-Circuit Fail Safe
Flow-Through Pinout
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
V
V
CC
CC
V
CC
GND
C1Y
C2Y
C3Y
C4Y
ENC
D1Y
D2Y
D3Y
D4Y
END
GND
DESCRIPTION
GND
This family of four-, eight-, or sixteen-, differential line
receivers (with optional integrated termination) im-
plements the electrical characteristics of low-voltage
differential signaling (LVDS). This signaling technique
lowers the output voltage levels of 5-V differential
standard levels (such as EIA/TIA-422B) to reduce the
power, increase the switching speeds, and allow
operation with a 3-V supply rail. Any of the eight or
sixteen differential receivers provides a valid logical
output state with a ±100-mV differential input voltage
within the input common-mode voltage range. The
input common-mode voltage range allows 1 V of
ground potential difference between two LVDS
nodes. Additionally, the high-speed switching of
LVDS signals almost always requires the use of a line
impedance matching resistor at the receiving end of
the cable or transmission media. The LVDT products
eliminate this external resistor by integrating it with
the receiver.
See application section for V
and GND description.
CC
’LVDS390, ’LVDT390
D OR PW PACKAGE
(TOP VIEW)
1A
1B
2A
2B
3A
3B
4A
4B
EN1,2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
1Y
2Y
V
CC
V
CC
GND
3Y
V
CC
GND
10 4Y
EN3,4
9
(1) Signaling Rate, 1/t, where t is the minimum unit interval and is
expressed in the units bits/s (bits per second)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G–SEPTEMBER 1999–REVISED NOVEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. The large number of receivers integrated into the same substrate along with the
low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for
synchronous parallel data transfers. When used with its companion, 8- or 16-channel driver, the SN65LVDS389
or SN65LVDS387, over 300 million data transfers per second in single-edge clocked systems are possible with
little power. (Note: The ultimate rate and distance of data transfer depends on the attenuation characteristics of
the media, the noise coupling to the environment, and other system characteristics.)
AVAILABLE OPTIONS
TEMPERATURE
RANGE
NUMBER OF
RECEIVERS
PART NUMBER
SN65LVDS386DGG
BUS-PIN ESD
SYMBOLIZATION
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
16
16
16
16
8
15 kV
15 kV
4 kV
LVDS386
LVDT386
SN65LVDT386DGG
SN75LVDS386DGG
SN75LVDT386DGG
SN65LVDS388ADBT
SN65LVDT388ADBT
SN75LVDS388ADBT
SN75LVDT388ADBT
SN65LVDS390D
75LVDS386
75LVDT386
LVDS388A
LVDT388A
75LVDS388A
75LVDT388A
LVDS390
0°C to 70°C
4 kV
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
15 kV
15 kV
4 kV
8
8
0°C to 70°C
8
4 kV
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
4
15 kV
15 kV
15 kV
15 kV
4 kV
SN65LVDS390PW
SN65LVDT390D
4
LVDS390
4
LVDT390
SN65LVDT390PW
SN75LVDS390D
4
LVDT390
4
75LVDS390
DS390
SN75LVDS390PW
SN75LVDT390D
0°C to 70°C
4
4 kV
0°C to 70°C
4
4 kV
75LVDT390
DG390
SN75LVDT390PW
0°C to 70°C
4
4 kV
2
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G–SEPTEMBER 1999–REVISED NOVEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
’LVDx388A
’LVDx386
’LVDx390
’LVDT386 ONLY
’LVDT390 ONLY
’LVDT388A ONLY
1A
1A
1Y
1Y
1A
1B
2A
1B
EN
1Y
2Y
1B
EN
2A
2A
2Y
3Y
4Y
2Y
3Y
4Y
2B
EN
3A
2B
2B
3A
(1/4 of ’LVDx388A shown)
3B
4A
4B
3B
EN
4A
4B
(1/4 of ’LVDx386 shown)
(’LVDx390 shown)
FUNCTION TABLE
SNx5LVD386/388A/390 and SNx5LVDT386/388A/390
DIFFERENTIAL INPUT(1)
ENABLES(1)
OUTPUT(1)
A-B
EN
H
Y
H
?
V
ID≥ 100 mV
–100 mV < VID≤ 100 mV
H
VID≤ -100 mV
H
L
X
L
Z
H
Open
H
(1) H = high level, L = low level, X = irrelevant, Z = high impedance
(off), ? = indeterminate
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
V
CC
V
CC
300 kΩ
300 kΩ
400 Ω
5 Ω
EN
7 V
Y Output
A Input
B Input
7 V
300 kΩ
7 V
7 V
110 Ω
’LVDT Devices Only
3
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G–SEPTEMBER 1999–REVISED NOVEMBER 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)
(1)
UNITS
(2)
VCC
VI
Supply voltage range
Voltage range:
–0.5 V to 4 V
–0.5 V to 6 V
Enables or Y
A or B
–0.5 V to 4 V
IO
Output current
Y
±12 mA
|VID
|
Differential input voltage magnitude
SN65LVDT' or SN75LVDT' only
SN65' (A, B, and GND)
SN75' (A, B, and GND)
1 V
(3)
Electrostatic discharge: see
Class 3, A:15 kV, B: 400 V
Class 2, A:4 kV, B: 400 V
See Dissipation Rating Table
–65°C to 150°C
260°C
Continuous power dissipation
Storage temperature range
Tstg
Lead temperature 1,6 mm (1/16 in) from case
for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
TA≤ 25°C
D
950 mW
1071 mW
2094 mW
774 mW
7.6 mW/°C
8.5 mW/°C
16.7 mW/°C
6.2 mW/°C
608 mW
688 mW
1342 mW
496 mW
494 mW
556 mW
1089 mW
402 mW
DBT
DGG
PW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.
RECOMMENDED OPERATING CONDITIONS
MIN
3
NOM
MAX
UNIT
VCC
VIH
VIL
IO
Supply voltage
3.3
3.6
V
V
High-level input voltage
Low-level input voltage
Output current
2
0.8
8
V
Y
– 8
0.1
mA
V
|VID
|
Magnitude of differential input voltage
0.6
|V
|
|V
|
ID
ID
2.4 *
VIC, see Figure 4
Common-mode input voltage
Operating free-air temperature
V
2
2
VCC – 0.8
SN75'
SN65'
0
70
85
°C
°C
TA
–40
4
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G–SEPTEMBER 1999–REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
VIT+
VIT–
VOH
VOL
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
High-level output voltage
100
mV
mV
V
See Figure 1 and
Table 1
–100
2.4
IOH= –8 mA
IOL = 8 mA
3
0.2
50
22
8
Low-level output voltage
0.4
70
40
18
3
V
'LVDx386
'LVDx388A Enabled, No load
'LVDx390
ICC
Supply current
mA
'LVDx386
'LVDx388A Disabled
'LVDx390
3
1.5
–20
VI = 0 V
'LVDS
–13
–3
VI = 2.4 V
–1.2
–2.4
VI = 0 V, other input
II
Input current (A or B inputs)
µA
–40
open
'LVDT
VI = 2.4 V, other input
open
VIA = 0 V, VIB = 0.1 V,
'LVDS
IID
IID
Differential input current |IIA - IIB|
Differential input current (IIA - IIB)
±2
µA
VIA= 2.4 V, VIB = 2.3 V
VIA = 0.2 V, VIB = 0 V,
'LVDT
1.5
2.2
mA
VIA= 2.4 V, VIB = 2.2 V
II(OFF) Power-off input current (A or B inputs)
II(OFF) Power-off input current (A or B inputs)
'LVDS
'LVDT
VCC = 0 V, VI = 2.4 V
VCC = 0 V, VI = 2.4 V
VIH = 2 V
12
±20
±40
10
µA
µA
µA
µA
IIH
IIL
High-level input current (enables)
Low-level input current (enables)
VIL = 0.8 V
10
VO = 0 V
±1
IOZ
High-impedance output current
µA
VO= 3.6 V
10
CIN
Z(t)
Input capacitance, A or B input to GND
Termination impedance
VID = 0.4 sin 2.5E09 t V
VID = 0.4 sin 2.5E09 t V
5
pF
88
132
Ω
(1) All typical values are at 25°C and with a 3.3-V supply.
5
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G–SEPTEMBER 1999–REVISED NOVEMBER 2004
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Output signal rise time
1
1
2.6
2.5
4
4
ns
ns
ps
ps
ps
ps
ns
ns
ns
ns
ns
500
500
800
800
150
100
1200
1200
600
400
1
tf
Output signal fall time
See Figure 2
tsk(p)
tsk(o)
tsk(pp)
tPZH
tPZL
tPHZ
tPLZ
Pulse skew (|tPHL - tPLH|)
Output skew(2)
Part-to-part skew(3)
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
7
7
7
7
15
15
See Figure 3
15
15
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected
together.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in
this data sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits.
PARAMETER MEASUREMENT INFORMATION
A
V
) V
R
IA
IB
V
ID
2
V
IA
B
V
O
V
IC
V
IB
Figure 1. Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
APPLIED VOLTAGES
VIA
1.25 V
1.15 V
2.4 V
2.3 V
0.1 V
0 V
VIB
VID
VIC
1.15 V
1.25 V
2.3 V
2.4 V
0 V
100 mV
–100 mV
100 mV
–100 mV
100 mV
–100 mV
600 mV
–600 mV
600 mV
–600 mV
600 mV
–600 mV
1.2 V
1.2 V
2.35 V
2.35 V
0.05 V
0.05 V
1.2 V
1.2 V
2.1 V
2.1 V
0.3 V
0.3 V
0.1 V
0.9 V
1.5 V
1.8 V
2.4 V
0 V
1.5 V
0.9 V
2.4 V
1.8 V
0.6 V
0 V
0.6 V
6
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G–SEPTEMBER 1999–REVISED NOVEMBER 2004
V
ID
V
IA
C
L
V
O
10 pF
V
IB
V
V
1.4 V
1 V
IA
IB
0.4 V
0 V
V
ID
–0.4 V
t
t
PHL
PLH
V
V
O
OH
80%
20%
1.5 V
V
OL
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 2. Timing Test Circuit and Wave Forms
7
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G–SEPTEMBER 1999–REVISED NOVEMBER 2004
B
1.2 V
500 Ω
A
C
10 pF
+
–
L
V
O
V
TEST
Inputs
EN
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
2.5 V
V
TEST
A
1 V
2 V
EN
1.4 V
0.8 V
t
t
PZL
PLZ
2.5 V
1.4 V
Y
V
OL
+0.5 V
V
OL
0 V
V
TEST
A
1.4 V
2 V
EN
1.4 V
0.8 V
t
t
PZH
PHZ
V
OH
V
OH
–0.5 V
Y
1.4 V
0 V
Figure 3. Enable/Disable Time Test Circuit and Wave Forms
8
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G–SEPTEMBER 1999–REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
LVDx390
SUPPLY CURRENT
vs
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
SWITCHING FREQUENCY
140
120
100
80
2.5
2.0
1.5
1.0
0.5
Max at V > 3.15 V
CC
Max at V = 3 V
CC
V
CC
= 3.6 V
V
CC
= 3 V
60
V
= 3.3 V
CC
40
20
Minimum
0.3
0
0.0
0.0
0
50
100
150
200
250
300
350
0.1
0.2
0.4
0.5
0.6
f − Switching Frequency − MHz
|V | − Differential Input Voltage − V
ID
Figure 4.
Figure 5.
LVDx388A
SUPPLY CURRENT
vs
LVDx386
SUPPLY CURRENT
vs
SWITCHING FREQUENCY
SWITCHING FREQUENCY
350
300
250
200
150
100
50
600
500
400
300
200
100
0
V
= 3.6 V
CC
V
= 3.6 V
CC
V
= 3 V
CC
V
= 3 V
CC
V
= 3.3 V
CC
V
= 3.3 V
CC
0
0
0
50
100
150
200
250
300
50
100
150
200
250
300
f − Switching Frequency − MHz
f − Switching Frequency − MHz
Figure 6.
Figure 7.
9
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G–SEPTEMBER 1999–REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS (continued)
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−70
−60
−50
−40
−30
−20
−10
0
0
10
20
30
40
50
60
70
80
I
− High-Level Output Current − mA
I
− Low-Level Output Current − mA
OH
OL
Figure 8.
Figure 9.
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
V
= 3 V
CC
V
= 3.6 V
CC
V
= 3 V
V
= 3.6 V
CC
CC
V
CC
= 3.3 V
V
CC
= 3.3 V
−50
−30
−10
10
30
50
70
90
−50
−30
−10
10
30
50
70
90
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 10.
Figure 11.
10
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G–SEPTEMBER 1999–REVISED NOVEMBER 2004
APPLICATION INFORMATION
Balanced Interconnect
Host
Target
Power
Power
T
Host
Target
DBn
DBn
Controller
Controller
T
T
T
DBn–1
DBn–2
DBn–3
DBn–1
DBn–2
DBn–3
T
T
T
T
DB2
DB1
DB2
DB1
DB0
DB0
TX Clock
RX Clock
LVDx368, LVDx388
LVDx388A, or LVDx390
LVDS Drivers
Indicates twisting of the
conductors.
Indicates the line termination
circuit.
T
Figure 12. Typical Application Schematic
ANALOG AND DIGITAL GROUNDS/POWER SUPPLIES
Although it is not necessary to separate out the analog/digital supplies and grounds on the SN65LVDS/T388A
and SN75LVDS/T388A, the pinout provides the user that option. To help minimize or perhaps eliminate switching
noise being coupled between the two supplies, the user could lay out separate supply and ground planes for the
designated pinout.
Most applications probably have all grounds connected together and all power supplies connected together. This
configuration was used while characterizing and setting the data-sheet parameters.
FAIL SAFE
One of the most common problems with differential signaling applications is how the system responds when no
differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that
its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV,
and within its recommended input common-mode voltage range. TI's LVDS receiver is different in how it handles
the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
pulls each line of the signal pair to near VCC through 300-kΩ resistors, as shown in Figure 13. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level, regardless of the differential input voltage.
11
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G–SEPTEMBER 1999–REVISED NOVEMBER 2004
APPLICATION INFORMATION (continued)
V
CC
300 kΩ
300 kΩ
A
Rt = 100 Ω (Typ)
Y
B
V
IT
≈ 2.3 V
Figure 13. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver is valid with less than a 100-mV differential input
voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it
is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat
the pullup currents from the receiver and the fail-safe feature.
12
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
PACKAGING INFORMATION
Orderable Device
SN65LVDS386DGG
SN65LVDS386DGGG4
SN65LVDS386DGGR
SN65LVDS386DGGRG4
SN65LVDS388ADBT
SN65LVDS388ADBTG4
SN65LVDS388ADBTR
SN65LVDS388ADBTRG4
SN65LVDS390D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
64
64
64
64
38
38
38
38
16
16
16
16
16
16
16
16
64
64
64
64
38
38
38
38
16
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TSSOP
TSSOP
TSSOP
SM8
DGG
DGG
DGG
DBT
DBT
DBT
DBT
D
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS390DG4
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS390DR
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS390DRG4
SN65LVDS390PW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
SM8
PW
PW
PW
PW
DGG
DGG
DGG
DGG
DBT
DBT
DBT
DBT
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS390PWG4
SN65LVDS390PWR
SN65LVDS390PWRG4
SN65LVDT386DGG
SN65LVDT386DGGG4
SN65LVDT386DGGR
SN65LVDT386DGGRG4
SN65LVDT388ADBT
SN65LVDT388ADBTG4
SN65LVDT388ADBTR
SN65LVDT388ADBTRG4
SN65LVDT390D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
Orderable Device
SN65LVDT390DG4
SN65LVDT390DR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
64
64
64
64
38
38
38
38
16
16
16
16
16
16
16
16
64
64
64
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDT390DRG4
SN65LVDT390PW
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
SM8
PW
PW
PW
PW
DGG
DGG
DGG
DGG
DBT
DBT
DBT
DBT
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDT390PWG4
SN65LVDT390PWR
SN65LVDT390PWRG4
SN75LVDS386DGG
SN75LVDS386DGGG4
SN75LVDS386DGGR
SN75LVDS386DGGRG4
SN75LVDS388ADBT
SN75LVDS388ADBTG4
SN75LVDS388ADBTR
SN75LVDS388ADBTRG4
SN75LVDS390D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75LVDS390DG4
SN75LVDS390DR
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75LVDS390DRG4
SN75LVDS390PW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
DGG
DGG
DGG
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75LVDS390PWG4
SN75LVDS390PWR
SN75LVDS390PWRG4
SN75LVDT386DGG
SN75LVDT386DGGG4
SN75LVDT386DGGR
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
Orderable Device
SN75LVDT386DGGRG4
SN75LVDT388ADBT
SN75LVDT388ADBTG4
SN75LVDT388ADBTR
SN75LVDT388ADBTRG4
SN75LVDT390D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
64
38
38
38
38
16
16
16
16
16
16
16
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
SM8
DBT
DBT
DBT
DBT
D
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75LVDT390DR
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75LVDT390DRG4
SN75LVDT390PW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75LVDT390PWG4
SN75LVDT390PWR
SN75LVDT390PWRG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
to Customer on an annual basis.
Addendum-Page 4
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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