SN65LVDS388DBTRG4 [TI]
OCTAL LINE RECEIVER, PDSO38, 0.50 MM PITCH, GREEN, PLASTIC, TSSOP-38;
| 型号： | SN65LVDS388DBTRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL LINE RECEIVER, PDSO38, 0.50 MM PITCH, GREEN, PLASTIC, TSSOP-38 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总16页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
Eight Line Receivers Meet or Exceed the
Requirements of ANSI TIA/EIA-644
Standard
NOT RECOMMENDED FOR NEW DESIGNS
For Replacement Use ’LVDx388A
Integrated 110-Ω Line Termination
Resistors on LVDT Products
’LVDS388, ’LVDT388
DBT PACKAGE
(TOP VIEW)
†
Designed for Signaling Rates Up To
630 Mbps
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
A1A
A1B
A2A
A2B
NC
B1A
B1B
B2A
B2B
NC
C1A
C1B
C2A
C2B
NC
D1A
D1B
D2A
D2B
GND
SN65 Version’s Bus-Terminal ESD Exceeds
15 kV
2
V
CC
3
ENA
A1Y
A2Y
ENB
B1Y
B2Y
GND
Operates From a Single 3.3-V Supply
Propagation Delay Time of 2.6 ns (Typ)
4
5
6
Output Skew 100 ps (Typ)
Part-To-Part Skew Is Less Than 1 ns
7
8
LVTTL Levels Are 5-V Tolerant
Open-Circuit Fail Safe
9
10
11
12
13
14
15
16
17
18
19
V
CC
Flow-Through Pin Out
GND
C1Y
C2Y
ENC
D1Y
D2Y
END
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
description
The ‘LVDS388 and ‘LVDT388 (T designates
integrated termination) are eight differential line
receivers that implement the electrical character-
istics of low-voltage differential signaling (LVDS).
Thissignalingtechniquelowerstheoutputvoltage
levels of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a 3-V
supply rail. Any of the eight differential receivers
will provide a valid logical output state with a
+100-mV differential input voltage within the input
common-mode voltage range. The input
common-mode voltage range allows 1 V of
ground potential difference between two LVDS
nodes. Additionally, the high-speed switching of
LVDS signals always require the use of a line
impedance matching resistor at the receiving end
of the cable or transmission media. The LVDT
product eliminates this external resistor by
integrating it with the receiver.
V
CC
GND
logic diagram (positive logic)
’LVDx388
’LVDT388 ONLY
1A
1Y
1B
EN
2A
2Y
2B
(1/4 of ’LVDx388 shown)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
description (continued)
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. The large number of drivers integrated into the same substrate along with the
low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for
synchronous parallel data transfers. When used with its companion, 8-channel driver, the SN65LVDS389 over
150 million data transfers per second in single-edge clocked systems are possible with very little power. Note:
The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media,
the noise coupling to the environment, and other system characteristics.
The SN65LVDS388 and SN65LVDT388 is characterized for operation from –40°C to 85°C. The SN75LVDS388
and SN75LVDT388 is characterized for operation from 0°C to 70°C.
AVAILABLE OPTIONS
TEMPERATURE
RANGE
NUMBER OF
RECEIVERS
PART NUMBER
BUS-PIN ESD
SN65LVDS388DBT
SN65LVDT388DBT
SN75LVDS388DBT
SN75LVDT388DBT
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
8
8
8
8
15 kV
15 kV
4 kV
0°C to 70°C
4 kV
Function Table
SNx5LVD388 and SNx5LVDT388
DIFFERENTIAL INPUT
ENABLES
OUTPUT
A-B
EN
H
Y
H
?
V
ID
≥ 100 mV
-100 mV < V ≤ 100 mV
ID
H
V
ID
≤ -100 mV
X
H
L
L
Z
H
Open
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
equivalent input and output schematic diagrams
V
CC
V
CC
V
CC
300 kΩ
300 kΩ
400 Ω
5 Ω
EN
7 V
Y Output
A Input
B Input
7 V
300 kΩ
7 V
7 V
110 Ω
’LVDT Devices Only
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
CC
Voltage range:
Enables or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Electrostatic discharge: (see Note 2)
SN65’ (A, B, and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:15 kV, B: 700 V
SN75’ (A, B, and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2, A:4 kV, B: 400 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
‡
DERATING FACTOR
T
= 70°C
T = 85°C
A
POWER RATING
A
PACKAGE
T ≤ 25°C
A
ABOVE T = 25°C
POWER RATING
A
DBT
1071 mW
8.5 mW/°C
688 mW
556 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.
recommended operating conditions
MIN NOM
MAX
UNIT
Supply voltage, V
CC
3
2
3.3
3.6
V
V
V
V
High-level input voltage, V
IH
Enables
Enables
Low-level input voltage, V
IL
Magnitude of differential input voltage, V
0.8
0.6
0.1
|
ID
|V
|V
|
ID
ID
2.4
2
Common-mode input voltage, V (see Figure 4)
IC
V
2
V
CC
– 0.8
70
SN75’
SN65’
0
°C
°C
Operating free-air temperature, T
A
–40
85
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
electrical characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
mV
mV
V
V
IT+
V
IT–
V
OH
V
OL
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
High-level output voltage
100
See Figure 1 and Table 1
–100
I
I
= –8 mA
2.4
3
OH
Low-level output voltage
= 8 mA
0.2
50
0.4
70
V
OL
Enabled,
Disabled
No load
mA
mA
I
Supply current
CC
3
V = 0 V
–13
–3
–20
I
’LVDS
V = 2.4 V
I
–1.2
–2.4
I
I
Input current (A or B inputs)
µA
V = 0 V, other input open
I
–40
’LVDT
V = 2.4 V, other input open
I
V
V
= 0 V,
= 2.4 V,
V
V
= 0.1 V,
= 2.3 V
IA
IA
IB
IB
I
I
Differential input current |I – I
|
‘LVDS
‘LVDT
±2
µA
ID
IA IB
V
IA
V
IA
= 0.2 V,
= 2.4 V,
V
IB
V
IB
= 0 V,
= 2.2 V
Differential input current (I – I
)
1.5
2.2
mA
ID
IA IB
I
I
I
I
Power-off input current (A or B inputs)
Power-off input current (A or B inputs)
High-level input current (enables)
Low-level input current (enables)
‘LVDS
‘LVDT
V
V
V
V
V
V
V
V
= 0 V,
= 0 V,
V = 2.4 V
12
±20
±40
10
µA
µA
µA
µA
I(OFF)
I(OFF)
IH
CC
I
V = 2.4 V
I
CC
= 2 V
= 0.8 V
= 0 V
IH
IL
O
10
IL
±1
I
High-impedance output current
µA
OZ
= 3.6 V
10
O
C
Input capacitance, A or B input to GND
Termination impedance
= 0.4 sin 2.5E09 t V
= 0.4 sin 2.5E09 t V
5
pF
IN
ID
ID
Z
†
88
132
Ω
(t)
All typical values are at 25°C and with a 3.3-V supply.
switching characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Output signal rise time
TEST CONDITIONS
MIN TYP
MAX
4
UNIT
ns
t
t
t
t
t
1
1
2.6
2.5
PLH
PHL
r
4
ns
500
500
800
800
150
1200
1200
600
ps
Output signal fall time
ps
See Figure 2
f
Pulse skew (|t
– t
PHL PLH
|)
ps
sk(p)
‡
t
Output skew
Part-to-part skew
100
400
1
ps
ns
sk(o)
§
t
sk(pp)
t
t
t
t
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
7
7
7
7
15
15
15
15
ns
ns
ns
ns
PZH
PZL
PHZ
PLZ
See Figure 3
†
‡
§
All typical values are at 25°C and with a 3.3-V supply.
t
t
is the magnitude of the time difference between the t
or t
of all drivers of a single device with all of their inputs connected together.
sk(o)
PLH
PHL
isthemagnitudeofthedifferenceinpropagationdelaytimesbetweenanyspecifiedterminalsofanytwodevicescharacterizedinthisdata
sk(pp)
sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
A
V
V
R
IA
IB
V
ID
2
V
IA
B
V
O
V
IC
V
IB
Figure 1. Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
APPLIED VOLTAGES
V
IA
V
IB
V
ID
V
IC
1.25 V
1.15 V
2.4 V
2.3 V
0.1 V
0 V
1.15 V
1.25 V
2.3 V
2.4 V
0 V
100 mV
–100 mV
100 mV
–100 mV
100 mV
–100 mV
600 mV
–600 mV
600 mV
–600 mV
600 mV
–600 mV
1.2 V
1.2 V
2.35 V
2.35 V
0.05 V
0.05 V
1.2 V
1.2 V
2.1 V
2.1 V
0.3 V
0.3 V
0.1 V
0.9 V
1.5 V
1.8 V
2.4 V
0 V
1.5 V
0.9 V
2.4 V
1.8 V
0.6 V
0 V
0.6 V
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
V
ID
V
IA
C
L
V
O
10 pF
V
IB
V
V
1.4 V
1 V
IA
IB
0.4 V
0 V
V
ID
–0.4 V
t
t
PHL
PLH
V
V
O
OH
80%
20%
1.5 V
V
OL
t
f
t
r
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse
r
f
width = 10 ± 0.2 ns. C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
Figure 2. Timing Test Circuit and Wave Forms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
B
1.2 V
500 Ω
A
C
10 pF
+
–
L
V
O
V
TEST
Inputs
EN
NOTE A: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulse width = 500 ± 10 ns. C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
2.5 V
V
TEST
A
1 V
2 V
EN
1.4 V
0.8 V
t
t
PZL
PLZ
2.5 V
1.4 V
Y
V
OL
+0.5 V
V
OL
0 V
V
TEST
A
1.4 V
2 V
EN
1.4 V
0.8 V
t
t
PZH
PHZ
V
OH
V
OH
–0.5 V
Y
1.4 V
0 V
Figure 3. Enable/Disable Time Test Circuit and Wave Forms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
TYPICAL CHARACTERISTICS
LVDx388
SUPPLY CURRENT
vs
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
SWITCHING FREQUENCY
2.5
2.0
1.5
1.0
0.5
0
200
180
160
140
120
100
80
Max at V
= 3 V
> 3.15 V
CC
Max at V
CC
V
= 3.6 V
CC
V
CC
= 3 V
V
CC
= 3.3 V
60
40
Minimum
0.3
20
0
0
0.1
0.2
0.4
0.5
0.6
0
20 40 60 80 100 120 140 160 180 200
|V | – Differential Input Voltage – V
ID
f – Switching Frequency – MHz
Figure 4
Figure 5
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–70
–60
–50
–40
–30
–20
–10
0
0
10
20
30
40
50
60
70
80
I
– High-Level Output Current – mA
OH
I
– Low-Level Output Current – mA
OL
Figure 6
Figure 7
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
TYPICAL CHARACTERISTICS
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
V
= 3 V
CC
V
= 3.6 V
CC
V
= 3 V
V
= 3.6 V
CC
CC
V
CC
= 3.3 V
V
= 3.3 V
30
CC
–50
–30
–10
10
30
50
70
90
–50
–30
–10
10
50
70
90
Ta – Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 8
Figure 9
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
APPLICATION INFORMATION
Balanced Interconnect
Host
Target
Power
Power
T
Host
DBn
Target
DBn
Controller
Controller
T
T
T
DBn–1
DBn–2
DBn–3
DBn–1
DBn–2
DBn–3
T
T
T
T
DB2
DB1
DB2
DB1
DB0
DB0
TX Clock
RX Clock
LVDx386, LVDx388,
LVDx388A, or LVDx390
LVDS Drivers
Indicates twisting of the
conductors.
Indicates the line termination
circuit.
T
Figure 10. Typical Application Schematic
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and
100 mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how
it handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
will pull each line of the signal pair to near V
through 300-kΩ resistors as shown in Figure 10. The fail-safe
CC
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
V
CC
300 kΩ
300 kΩ
A
Rt = 100 Ω (Typ)
Y
B
V
IT
≈ 2.3 V
Figure 11. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
MECHANICAL DATA
DBT (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,27
M
0,50
30
0,08
0,17
16
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
15
0°–8°
0,75
0,50
A
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
28
30
38
44
50
DIM
7,90
7,70
7,90
7,70
9,80
9,60
11,10
10,90
12,60
12,40
A MAX
A MIN
4073252/D 09/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-153
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2008
PACKAGING INFORMATION
Orderable Device
SN65LVDS388DBT
SN65LVDS388DBTR
SN65LVDT388DBT
SN65LVDT388DBTR
SN75LVDS388DBT
SN75LVDS388DBTR
SN75LVDT388DBT
SN75LVDT388DBTR
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
NRND
TSSOP
DBT
38
38
38
38
38
38
38
38
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
NRND
TSSOP
DBT
DBT
DBT
DBT
DBT
DBT
DBT
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OBSOLETE TSSOP
OBSOLETE TSSOP
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
NRND
NRND
TSSOP
TSSOP
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OBSOLETE TSSOP
OBSOLETE TSSOP
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN65LVDS388DBTR
SN65LVDT388DBTR
SN75LVDS388DBTR
SN75LVDT388DBTR
TSSOP
TSSOP
TSSOP
TSSOP
DBT
DBT
DBT
DBT
38
38
38
38
0
0
0
0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
6.9
6.9
6.9
6.9
10.2
10.2
10.2
10.2
1.8
1.8
1.8
1.8
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65LVDS388DBTR
SN65LVDT388DBTR
SN75LVDS388DBTR
SN75LVDT388DBTR
TSSOP
TSSOP
TSSOP
TSSOP
DBT
DBT
DBT
DBT
38
38
38
38
0
0
0
0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
33.0
33.0
33.0
33.0
Pack Materials-Page 2
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