SN65LVDS822RGZR [TI]
Flatlink™ 低电压差分信号 (LVDS) 接收器 | RGZ | 48 | -40 to 85;
| 型号： | SN65LVDS822RGZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Flatlink™ 低电压差分信号 (LVDS) 接收器 | RGZ | 48 | -40 to 85 |
| 文件： | 总36页 (文件大小：2747K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN65LVDS822
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
SN65LVDS822 Flatlink™ LVDS 接收器
1 特性
3 说明
1
•
•
4:27 LVDS 到 CMOS 解串器
SN65LVDS822 是一种高级 Flatlink™ 低压差分信号
(LVDS) 接收器，采用现代化 CMOS 工艺。 该器件具
有几个独特的功能，其中包括 3 个可选 CMOS 输出转
换率，1.8V 至 3.3V 的 CMOS 输出电压支持，一个引
脚分配交换选项，集成差分端接（可配置），一个自动
低功耗模式和 4:27 和 2:27 解串化模式。 它与诸如
SN75LVDS83B、SN65LVDS93A 的 TI FlatLink™ 发
送器以及符合 TIA/EIA 644-A 标准的标准工业用 LVDS
发送器兼容。
对于 160 × 120 至 1024 × 600 范围内的分辨率，
像素时钟范围为 4MHz 至 54MHz
•
具有 14x 采样的特殊 2:27 模式允许只使用 2 条数
据信道
•
•
具有 3 路可选 CMOS 转换率的极低电磁干扰 (EMI)
支持单个 3.3V 电源；VDDIO 允许 1.8V 至 3.3V 电
压范围，可提供灵活的面板支持
•
•
时钟输出为上升或下降边沿
针对灵活印刷电路板 (PCB) 布局布线的总线交换特
性
SN65LVDS822 特有一个自动低功耗待机模式，当
LVDS 时钟被禁用时激活。 此器件在将低压施加到引
脚 SHTDN# 上时进入一个平均低功耗关断模式。
•
•
集成型可切换输入端接
所有输入引脚是故障安全的；±3kV 人体模型
(HBM) 静电放电 (ESD) 保护
SN65LVDS822 采用 48 引脚 7mm x 7mm 塑料四方扁
平无引线 (QFN) 封装，封装的焊球间距为 0.5mm，并
且可在 –40°C 至 85°C 的工业环境温度范围内使用。
•
•
7mm x 7mm 48 引脚超薄四方扁平无引线
(VQFN)，0.5mm 间距
与 TIA/EIA-644-A 发送器兼容
器件信息(1)
2 应用范围
部件号
封装
封装尺寸（标称值）
•
•
•
打印机
SN65LVDS822
VQFN (48)
7.00mm x 7.00mm
具有一个 LCD 的装置
数码照相机
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
SoC
LVDS
Serializer
Video
Source
CMOS
RGB
LVDS
Can be discrete
SN75LVDS83B
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLLSEE8
SN65LVDS822
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明（继续） ........................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ..................................... 7
7.2 Handling Ratings....................................................... 7
7.3 Recommended Operating Conditions ...................... 8
7.4 Thermal Information.................................................. 9
7.5 DC Electrical Characteristics .................................. 10
7.6 Power Supply Characteristics ................................ 10
7.7 Switching Characteristics........................................ 11
7.8 Typical Characteristics............................................ 16
Parameter Measurement Information ................ 17
8.1 Test Patterns........................................................... 17
9
Detailed Description ............................................ 19
9.1 Overview ................................................................. 19
9.2 Functional Block Diagram ....................................... 19
9.3 Feature Description................................................. 20
9.4 Device Functional Modes........................................ 21
10 Application and Implementation........................ 22
10.1 Application Information.......................................... 22
10.2 Typical Application ................................................ 24
11 Power Supply Recommendations ..................... 26
11.1 Decoupling Capacitor Recommendations............. 26
12 Layout................................................................... 26
12.1 Layout Guidelines ................................................. 26
12.2 Layout Example .................................................... 27
13 器件和文档支持 ..................................................... 28
13.1 商标....................................................................... 28
13.2 静电放电警告......................................................... 28
13.3 术语表 ................................................................... 28
14 机械封装和可订购信息 .......................................... 28
8
4 修订历史记录
Changes from Revision A (October 2013) to Revision B
Page
•
已添加 引脚配置和功能部分，处理额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，
布局部分，器件和文档支持部分以及机械、封装和可订购信息部分........................................................................................ 1
2
版权 © 2013–2014, Texas Instruments Incorporated
SN65LVDS822
www.ti.com.cn
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
5 说明（继续）
在标准 7x 模式下支持 4MHz 至 54MHz 的时钟频率范围，可与数据速率在 28Mbps 至 378Mbps 之间的 LVDS 数
据一同使用。 对于 56Mbps 至 378Mbps 的 LVDS 的数据速率，此 14x 模式支持 4MHz 至 27MHz 的频率。
LVDS 时钟频率始终与 CMOS 输出时钟频率相匹配。 为了实现正常运行，在时钟线路上监视直流共模电压。 此器
件的设计可支持 1/16 VGA (160 × 120) 至 1024 × 600 范围内的分辨率，每秒 60 帧，24 位彩色。
SN65LVDS822 特有一个自动低功耗待机模式，当 LVDS 时钟被禁用时激活。 此器件在将低压施加到引脚
SHTDN# 上时进入平均低功耗关断模式。 在这两个低功耗模式中，所有 CMOS 输出驱动为低电平。 所有输入引
脚具有故障安全保护功能，此功能在电源电压为高值且稳定前，可防止器件损坏。
SN65LVDS822 采用 48 引脚 7mm x 7mm 塑料四方扁平无引线 (QFN) 封装，封装的焊球间距为 0.5mm，并且可
在 –40°C 至 85°C 的工业环境温度范围内使用。
Copyright © 2013–2014, Texas Instruments Incorporated
3
SN65LVDS822
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
6 Pin Configuration and Functions
RGZ PACKAGE
(TOP VIEW)
SWAP Pin = Low or Floating
48
47
46
45
44
43
42
41
40
39
38
37
D15
D14
D13
D12
D24
VDDIO
D23
D11
D10
1
2
3
4
5
6
7
8
9
36 MODE14
35 SLEW
34 A3P
33 A3N
32 CLKP
31 CLKN
30 A2P
29 A2N
28 A1P
27 A1N
26 A0P
25 A0N
GND
D9 10
D8 11
D7 12
13
14
15
16
17
18
19
20
21
22
23
24
4
Copyright © 2013–2014, Texas Instruments Incorporated
SN65LVDS822
www.ti.com.cn
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
RGZ PACKAGE
(TOP VIEW)
SWAP Pin = High
48
47
46
45
44
43
42
41
40
39
38
37
D22
D6
1
2
3
4
5
6
7
8
9
36 MODE14
35 SLEW
34 A3P
33 A3N
32 CLKP
31 CLKN
30 A2P
29 A2N
28 A1P
27 A1N
26 A0P
25 A0N
D7
D8
D9
VDDIO
D10
D11
D23
GND
D24 10
D12 11
D13 12
13
14
15
16
17
18
19
20
21
22
23
24
Copyright © 2013–2014, Texas Instruments Incorporated
5
SN65LVDS822
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
26, 25
28, 27
30, 29
34, 33
32, 31
(SWAP = L / H)
22 / 38
21 / 39
20 / 40
19 / 42
18 / 46
16 / 47
13 / 2
A0P, A0N
A1P, A1N
A2P, A2N
A3P, A3N
CLKP, CLKN
LVDS Data Lane 0
LVDS Data Lane 1
LVDS Data Lane 2
LVDS Data Lane 3
LVDS Clock
LVDS Input
D0
D1
D2
D3
D4
D5
D6
D7
12 / 3
D8
11 / 4
D9
10 / 5
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
CLKOUT
9 / 7
8 / 8
4 / 11
CMOS Output
Data bus output
3 / 12
2 / 13
1 / 14
48 / 15
47 / 16
40 / 20
39 / 21
38 / 22
15 / 48
14 / 1
7 / 9
5 / 10
46 / 18
42 / 19
41
Clock output for the data bus
6
Copyright © 2013–2014, Texas Instruments Incorporated
SN65LVDS822
www.ti.com.cn
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Selects the CMOS output pinout, and also controls differential input termination.
Low – Default pinout, RID connected
SWAP
45
Floating – Default pinout, RID disconnected (requires external termination)
High – Swapped pinout, RID connected
Sets the number of LVDS serial bits per lane per clock period.
Low – 7 bits (see 图 16)
MODE14
36
High – 14 bits; only lanes A0 and A2 are used (see 图 17)
CLKOUT polarity
CMOS Input
Low – D[26:0] is valid during the CLKOUT falling edge
Floating – Reserved; do not use
CLKPOL
SHTDN#
SLEW
23
37
35
High – D[26:0] is valid during the CLKOUT rising edge
Shutdown Mode; Active-Low
Sets the CMOS output slew rate
Low – Slowest rise/fall time
Floating – Medium rise/fall time
High – Fastest rise/fall time
VDD
24, 44
Main power supply; 3.3 V
VDDIO
GND
6, 17, 43
Power Supply
Power supply for CMOS outputs; 1.8 V to 3.3 V
Reference Ground
Thermal Pad
7 Specifications
7.1 Absolute Maximum Ratings(1)
MIN
–0.3
–0.5
MAX
UNIT
Supply voltage range(2), VDD , VDDIO
4
4
V
Voltage range at
any input terminal
When VDDIO > 0 V
V
Voltage range at
When VDDIO ≤ 0 V
–0.5
VDDIO + 0.7
125
any output terminal
Maximum junction temperature, TJ
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminals
7.2 Handling Ratings
MIN
–65
–3
MAX
150
3
UNIT
Tstg
Storage temperature range
Electrostatic discharge
°C
Human body model(1) (all pins)
Charged device model(2) (all pins)
V(ESD)
V
–1.5
1.5
(1) In accordance with JEDEC Standard 22, Test Method A114-B
(2) In accordance with JEDEC Standard 22, Test Method C101
Copyright © 2013–2014, Texas Instruments Incorporated
7
SN65LVDS822
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
7.3 Recommended Operating Conditions
TEST CONDITIONS
MIN
3
TYP
MAX
3.6
3.6
100
50
UNIT
V
VDD
Main power supply
3.3
VDDIO
Power supply for CMOS outputs
1.65
V
fNOISE < 1 MHz
fNOISE > 1 MHz
Power supply noise
(peak-to-peak)
VNOISE
mV
TA
TC
Operating free-air temperature
Case temperature
–40
85
°C
°C
98
LVDS CLOCK (CLKP, CLKN)
MODE14 = Low
MODE14 = High
Standby Mode
MODE14 = Low
MODE14 = High
4
4
54
27
fCLK
LVDS clock frequency
LVDS clock duty cycle
MHz
0.5
57%
50%
tDC
LVDS INPUTS (A0P, A0N, A1P, A1N, A2P, A2N, A3P, A3N, CLKP, CLKN)
|VID
|
Input differential voltage(1)
|VAxP – VAxN| and |VCLKP-VCLKN
|
90
–10%
|VID|/2
–100
600
10%
mV
Input differential voltage variation
between lanes
Input common mode voltage(1)
ΔVID
VCM
2.4 - |VID|/2
100
V
Input common mode voltage
variation between lanes
ΔVCM
mV
fCLK = 4 MHz to 14 MHz
fCLK = 14 MHz to 22 MHz
fCLK = 22 MHz to 30 MHz
fCLK = 30 MHz to 54 MHz
fCLK = 4 MHz to 7 MHz
fCLK = 7 MHz to 11 MHz
fCLK = 11 MHz to 15 MHz
fCLK = 15 MHz to 27 MHz
3
2
MODE14 = Low
MODE14 = High
1.5
1
tR/F(VID)
LVDS VID rise/fall time(2)
ns
3
2
1.5
1
CMOS OUTPUTS (D[26:0], CLKOUT)
CL Capacitive load on the outputs
10
pF
(1) See 图 1.
(2) See 图 6. Defined from 20% to 80% of the differential voltage transition. Faster edge rates are generally preferred, as they provide more
timing margin.
8
版权 © 2013–2014, Texas Instruments Incorporated
SN65LVDS822
www.ti.com.cn
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
7.4 Thermal Information
SN65LVDS822
THERMAL METRIC(1)
RGZ
48 PINS
30.1
18.1
6.9
UNIT
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
°C/W
ψJT
0.2
ψJB
6.9
θJCbot
0.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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SN65LVDS822
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
7.5 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
80
TYP(1)
MAX
UNIT
LVDS INPUTS (A0P, A0N, A1P, A1N, A2P, A2N, A3P, A3N, CLKP, CLKN)
RID
CID
RPU
Differential input termination resistance(1)
SWAP = Low or High
132
Ω
Differential input capacitance
Measured across differential pairs
Measured from each input to VDD
1
pF
kΩ
Pull-up resistor for standby detection
90
VDD = 3.6 V; RID disconnected; One P/N
terminal is swept from 0 V to 2.4 V while
the other is 1.2 V
|II|
Input leakage current
70
µA
CMOS INPUTS (SWAP, MODE14, CLKPOL, SHTDN#, SLEW)
CIN
VIK
VIH
VIL
Input capacitance for CMOS inputs
Input clamp voltage
2
pF
V
II = -18 mA
–1.2
High-level input voltage
Low-level input voltage
0.8 x VDD
V
0.2 x VDD
V
3-STATE CMOS INPUTS (SWAP, CLKPOL, SLEW)
VF
IIH
IIL
Floating voltage
VIN = High impedance
VIN = 3.6 V
VDD/2
V
High-level input current (through pull-down)
Low-level input current (through pull-up)
36
20
µA
µA
VIN = GND, VDD = 3.6 V
-36
0
2-STATE CMOS INPUTS (MODE14, SHTDN#)
IIH
IIL
High-level input current (through pull-down)
Low-level input current
VIN = 3.6 V
VIN = GND
µA
µA
CMOS OUTPUTS (D[26:0], CLKOUT)
SLEW = Low; IOH = -250 µA
SLEW = Floating; IOH = -500 µA
SLEW = High; IOH = -1.33 mA
SLEW = Low; IOL = 250 µA
SLEW = Floating; IOL = 500 µA
SLEW = High; IOL = 1.33 mA
0.8 x VDDIO
VDDIO
VDDIO
VDDIO
0.5
VOH
High-level output voltage
Low-level output voltage
0.8 x VDDIO
V
V
0.8 x VDDIO
0
0
0
VOL
0.5
0.5
(1) When VDD = 0 V, the connection of RID is unknown.
7.6 Power Supply Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)(2)
TYP
MAX(1)
UNIT
Grayscale pattern; outputs terminated with 10 pF;
MODE14 = Low, VDD = 3.3 V, VDDIO = 1.8 V
SLEW = Low; fCLK = 10 MHz
24.6
mA
SLEW = Low; fCLK = 10 MHz
SLEW = Float; fCLK = 20 MHz
SLEW = High; fCLK = 54 MHz
SLEW = Float; fCLK = 20 MHz
SLEW = High; fCLK = 54 MHz
25.7
30.9
51.5
48.2
Grayscale pattern; outputs terminated with 10pF;
MODE14 = Low, VDD = VDDIO = 3.3 V
mA
Total average supply
current of VDD and VDDIO
IDD
59
1010 pattern; outputs terminated with 10 pF;
MODE14 = Low, VDD = VDDIO = 3.6 V
mA
mA
µA
101.7
4
124
fCLK < 500 kHz;
VCM-CLKP/N ≤ 0.80 x VDD
7
LVDS inputs are open; CMOS
inputs held static; Outputs
terminated with 10 pF
Standby Mode
VCM-CLKP/N > 0.95 x VDD
SHTDN# = Low
75
4
130
20
Shutdown Mode
Grayscale pattern; outputs terminated with 10 pF;
MODE14 = Low, VDD = 3.3 V, VDDIO = 1.8 V
SLEW = Low; fCLK = 10 MHz
SLEW = High; fCLK = 54 MHz
83
PD
Power Dissipation
mW
1010 pattern; outputs terminated with 10 pF;
MODE14 = Low, VDD = VDDIO = 3.6 V
366
446
(1) Grayscale and 1010 test patterns are described by 图 5 to 图 6 and 表 1 to 表 2.
(2) Standby Mode can be entered in two ways: fCLK = zero to 500 kHz, or a high VCM on the LVDS clock. If the LVDS transmitter device
disables its clock driver to a high-impedance state, the SN65LVDS822’s integrated RPU will pull VCM high for the lower-power Standby
state.
10
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SN65LVDS822
www.ti.com.cn
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
7.7 Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
INPUT TO OUTPUT RESPONSE TIME
Propagation delay of
data
tPD
Measured from CLK input to CLKOUT
2.4/fCLK
s
Enable time, exiting
Shutdown
From Shutdown Mode, time from SHTDN# pulled High
to valid output data (see 图 9)
tPWRUP
2
2
ms
ms
µs
Enable time, exiting
Standby
From Standby Mode, time from when CLK input starts
switching to valid output data
tWAKE
Disable time, entering
Shutdown
From Active Mode, time from SHTDN# pulled Low
until all outputs are static-Low
tPWRDN
11
3
Disable time, entering
From Active Mode, time from CLK input stopping until
all outputs are static-Low
tSTANDBY
Standby
µs
fBW
PLL bandwidth(1)
Tested from CLK input to CLKOUT
6% x fCLK
Hz
LVDS INPUTS (A0P, A0N, A1P, A1N, A2P, A2N, A3P, A3N, CLKP, CLKN)
MODE14 = Low
1/(14 x fCLK) – 620E-12
1/(28 x fCLK) – 620E-12
Receiver input skew
tRSKM
s
(3) (4)
margin(2)
MODE14 = High
LVDS data setup time
required before internal
clock edge
tR/F(VID) = 600 ps
VID = 90 mV
See 图 2
tSU1
620
620
ps
LVDS data hold time
required after internal
clock edge
tH1
ps
CMOS OUTPUTS (D[26:0], CLKOUT)
CLKPOL = Low
CLKPOL = High
43%
57%
50%
15
MODE14 = Low
MODE14 = High
tDCYC
Duty cycle of CLKOUT
SLEW = Low
10
5
20
10
3
CMOS output rise and
fall time (20% to 80%)
tR/F
CL = 10 pF
SLEW = Floating
SLEW = High
SLEW = Low
7.5
ns
1.3
2.1
0.38/fCLK – 2.2E-9
0.38/fCLK – 1.2E-9
0.38/fCLK – 0.7E-9
0.45/fCLK – 2.5E-9
0.45/fCLK – 1.5E-9
0.45/fCLK – 1E-9
0.52/fCLK – 18.2E-9
0.52/fCLK – 9.2E-9
0.52/fCLK – 3.7E-9
0.45/fCLK – 18.5E-9
0.45/fCLK – 9.5E-9
0.45/fCLK – 4E-9
MODE14 = Low; CL = 10 pF
MODE14 = High; CL = 10 pF
MODE14 = Low; CL = 10 pF
MODE14 = High; CL = 10 pF
SLEW = Floating
SLEW = High
SLEW = Low
Setup time available for
the downstream
receiver(5)
tSU2
s
SLEW = Floating
SLEW = High
SLEW = Low
SLEW = Floating
SLEW = High
SLEW = Low
Hold time available for
the downstream
receiver(5)
tH2
s
SLEW = Floating
SLEW = High
(1) The PLL bandwidth describes the typical highest modulation frequency that can be tracked. If the LVDS transmitter device generates a
spread spectrum, the LVDS clock and data must stay synchronized throughout modulation. The SN65LVDS822 will track and pass
through modulation, and the downstream CMOS receiver must be able to track it.
(2) Receiver Input Skew Margin (tRSKM) is the timing margin available for transmitter output pulse position (tPPOS), interconnect skew, and
interconnect inter-symbol interference. tRSKM represents the reminder of the serial bit time not taken up by the receiver strobe
uncertainty. The tRSKM assumes a bit error rate better than 10-12
.
(3) tRSKM is indirectly proportional to: internal setup and hold time uncertainty, ISI, duty cycle distortion from the front end receiver, skew
mismatch between LVDS clock and data, and PLL cycle-to-cycle jitter.
(4) LVDS input timing defined here is based on a simulated statistical analysis across process, voltage, and temperature ranges.
(5) See 图 3 and 图 4.
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11
SN65LVDS822
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
图 1. FlatLink™ Input Voltage Definitions
12
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SN65LVDS822
www.ti.com.cn
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
LVDS CLK
Internal 7x CLK
LVDS Data
CLKM
(1 ) 1
14 fCLK
Internal
clock edge
CLKP
AxP
tRSKM
tSU1
tH1
tRSKM
图 2. LVDS Input Timing (MODE14 = Low)
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13
SN65LVDS822
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
CLKOUT
20%
tSU2
tH2
80%
80%
20%
D[26:0]
20%
图 3. CMOS Output Timing (CLKPOL = Low)
80%
CLKOUT
tSU2
tH2
80%
20%
80%
20%
D[26:0]
图 4. CMOS Output Timing (CLKPOL = High)
14
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SN65LVDS822
www.ti.com.cn
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
LVDS CLK
LVDS Data
SHTDN#
tPWRUP
Low
Invalid
Valid
D[26:0]
图 5. Time to Exit Shutdown Mode
Positive V
ID
tF(VID)
tR(VID)
80%
VID = 0V
20%
Negative VID
图 6. LVDS Rise/Fall Time (Differential Voltage)
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15
SN65LVDS822
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
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7.8 Typical Characteristics
space
Input: channel 2 (green), Output: channel 1 (yellow)
图 7. Output Rise & Fall times - SLEW = High
图 8. Total Output Delay
16
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SN65LVDS822
www.ti.com.cn
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
8 Parameter Measurement Information
SN65LVDS822
CMOS
Driver
+
VO
-
CL = 10pF
图 9. CMOS Output Test Circuit
8.1 Test Patterns
CLKOUT
D0/D8/D16
D1/D9/D17
D2/D10/D18
D3/D11/D19
D4-7/D12-15/D20-23
D24-26
图 10. Grayscale Pattern (CLKPOL = Low); Used for Typical Power Data
表 1. Grayscale Pattern Data;
Repeats Every 16 Words
Word
1
D[26:0]
0x7000000
0x7080808
0x7040404
0x70C0C0C
0x7020202
0x70A0A0A
0x7060606
0x70E0E0E
0x7010101
0x7090909
0x7050505
0x70D0D0D
0x7030303
0x70B0B0B
0x7070707
0x70F0F0F
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
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SN65LVDS822
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
CLKOUT
Even Dx
Odd Dx
图 11. 1010 Pattern (CLKPOL = Low); Used for Maximum Power Data
表 2. 1010 Pattern Data;
Repeats Every 2 Words
Word
D[26:0]
1
2
0x2AAAAAA
0x5555555
18
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SN65LVDS822
www.ti.com.cn
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
9 Detailed Description
9.1 Overview
The SN65LVDS822 implements five low-voltage differential signal (LVDS) line receivers: 4 data lanes and 1
clock lane. The clock is internally multiplied by 7 or 14 (depending on pin MODE14), and used for sampling
LVDS data. The device operates in either 4-lane 7x mode, or 2-lane 14x mode. Each input lane contains a shift
register that converts serial data to parallel. 27 total bits per clock period are deserialized and presented on the
CMOS output bus, along with a clock that uses either rising- or falling-edge alignment.
9.2 Functional Block Diagram
A0P
RID
A0N
SWAP
MODE14
CLKPOL
SHTDN#
SLEW
A1P
A1N
RID
RID
RID
RID
Serial
to
D0
Control
Logic
Parallel
Conversion
A2P
A2N
D26
CLKOUT
A3P
A3N
VDD
7x or 14x
VDDIO
GND
1x
PLL
Multiplier
CLKP
CLKN
Standby
Detector
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SN65LVDS822
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9.3 Feature Description
9.3.1 Unused LVDS Data Lanes
When MODE14 = Low and fewer than 4 data lanes are used, or when MODE14 = High and only 1 data lane is
used, it’s recommended that the unused lanes are biased with a constant differential voltage. This prevents high-
frequency noise from toggling the unused receiver, which injects noise into the device. This is not a hard
requirement, but it’s standard best-practice, and the amount of noise varies system-to-system.
Two implementations are shown below, depending on whether the internal termination RID is connected. A
reasonable choice for R1 and R2 is 5kΩ, which produce a nominal VID of 34 mV and 0.3 mA of static current.
Smaller resistors increase VID and noise floor margin, as well as static current.
SN65LVDS822
SN65LVDS822
VDD
VDD
RPU
RPU
RPU
RPU
R1
R2
AxP
AxN
AxP
AxN
GND
GND
VDD
RID
图 12. Bias When RID is Connected
9.3.2 Tying CMOS Inputs With Resistors
图 13. Bias When RID is Disconnected
The IIH/IIL specifications indicate that 2-state CMOS input pins have an internal pull-down that’s a minimum size
of 180 kΩ, and 3-state CMOS input pins have an internal pull-up and pull-down that are a minimum size of
100 kΩ.
VDD
PU
PD
PD
图 14. 2-State CMOS Input
图 15. 3-State CMOS Input
CMOS inputs may be directly connected to VDD or GND, or tied through a resistor. Using a resistor creates a
voltage divider network, so it’s important to use a small enough resistor to satisfy VIH/VIL at the pin, and to have
voltage margin for system noise. When using a resistor, 5 kΩ or smaller is recommended. Of course, 3-state
inputs may be left unconnected to select their floating pin state.
20
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SN65LVDS822
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ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
9.4 Device Functional Modes
9.4.1 Active Modes
9.4.1.1 4-Lanes 7-Bit Mode
Previous
Current cycle
Next
CLK
D1
D8
D0
D7
D6
D5
D4
D3
D2
D9
D1
D8
D0
D7
D6
A0
A1
A2
A3
D13 D12 D11 D10
D13
D15 D14 D20 D19 D18 D17 D16 D15 D14 D20
D22 D21 RSV D26 D25 D24 D23 D22 D21 RSV
图 16. Data Bits Within the LVDS Stream (MODE14 = Low)
9.4.1.2 2-Lanes 14-Bit Mode
Previous
Current cycle
Next
CLK
D1
D0
D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D13
A0
A2
D15 D14 RSV D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 RSV
图 17. Data Bits Within the LVDS Stream (MODE14 = High)
9.4.2 Low-Power Modes
9.4.2.1 Standby Mode
In order to decrease the power consumption, the SN65LVDS822 automatically enters to standby when the LVDS
clock is inactive.
9.4.2.2 Shutdown Mode
This is the lower-power mode, and the SN65LVDS822 enters to this mode only when the SHTDN# terminal is
tied to low.
注
In both low-power modes, all CMOS outputs drive low. All input pins have failsafe
protection that prevents damage from occurring before power supply voltages are high
and stable.
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SN65LVDS822
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www.ti.com.cn
10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Color Bit Mapping
The SN65LVDS822 is a simple deserializer that ignores bit representation in the LVDS stream. The CMOS
output pin order was chosen so that if the color mapping within the LVDS stream matches the common VESA
standard, the parallel output bus of red/green/blue fans out sequentially, which matches the order that many LCD
panels require. Some LCD panels require a reversed order; for those, set pin “SWAP” high to reverse the output
bus and simplify PCB routing. 图 19 shows the application setup when SWAP is in different statuses.
Any color bit mapping is supported, by correctly connecting the output to the panel. However, bit “RSV” is
ignored and unavailable for use.
CLK +/-
G0
B1
R5
B0
VS
B7
R4
G5
HS
B6
R3
G4
B5
G7
R2
G3
B4
G6
R1
G2
B3
R7
R0
G1
B2
R6
RX0 +/-
RX1 +/-
RX2 +/-
RX3 +/-
DE
RSV
图 18. Common VESA Color Bit Mapping
22
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SN65LVDS822
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ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
Application Information (接下页)
LVDS822
Graphic Controller
24BIT
18BIT
12BIT
38
22
RED0
RED0
RED0
D0
D1
D2
D3
A0P
39
40
42
46
21
20
19
RED1
RED1
RED1
RED2
RED3
RED2
RED3
RED2
RED3
A0N
A1P
18
16
15
RED4
RED4
NA
D4
D5
47
48
RED5
RED5
NA
RED6
NA
NA
D21
D22
D6
1
2
14
13
RED7
NA
NA
A1N
A2P
GREEN0
GREEN1
GREEN2
GREEN3
GREEN4
GREEN5
GREEN6
GREEN0
GREEN1
GREEN2
GREEN3
GREEN4
GREEN5
NA
GREEN0
GREEN1
GREEN2
GREEN3
RSD
3
12
11
10
9
D7
4
5
D8
D9
A2N
A3P
7
D10
D11
D23
D24
D12
D13
D14
D15
8
8
RSD
9
7
NA
10
11
12
13
14
15
16
18
5
GREEN7
BLUE0
BLUE1
NA
NA
4
BLUE0
BLUE1
BLUE0
BLUE1
A3N
CLKP
CLKN
3
2
1
BLUE2
BLUE3
BLUE2
BLUE3
BLUE2
BLUE3
48
D16
D17
BLUE4
BLUE5
BLUE6
BLUE7
BLUE4
BLUE5
NA
NA
NA
NA
NA
47
46
42
40
D25
19
20
D26
NA
D18
H-SYNC
V-SYNC
H-SYNC
V-SYNC
H-SYNC
V-SYNC
21
22
39
38
D19
D20
DISPLAY ENABLE
CLOCK
DISPLAY ENABLE
CLOCK
DISPLAY ENABLE
CLOCK
41
41
CLKOUT
NOTE: NA t not applicable, these unused inputs should be left open
图 19. Pin Assignments With SWAP
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SN65LVDS822
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
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10.2 Typical Application
图 20. Typical Application
10.2.1 Design Requirements
DESIGN PARAMETERS
VALUE
3 - 3.6 V
1.65 - 3.6 V
4 - 54 MHz
80 - 132 Ω
2 or 4
VDD Main Power Supply
VDDIO Power Supply for CMOS Outputs
Input LVDS Clock Frequency
RID Differential Input Termination Resistance
LVDS Input Channels
Output Load Capacitance
1 pF
10.2.2 Detailed Design Procedure
10.2.2.1 Power Supply
The implementation operates from the power provided by two banana jack connectors (P1 and P3) common
ground. The VDD pin (P1) is connected to the main power supply to the SN65LVDS822 device and must be 3.3
V (±10%). The VDDIO pin (P3) is connected to the power supply of the SN65LVDS822 CMOS outputs and must
be in the range of 1.8 to 3.3 V.
10.2.2.2 CMOS Output Bus Connector
Color Bit Mapping shows the CMOS output and bit mapping. Because some LCD panels require a reversed
order, the SN65LVDS822 device is capable of reversing the output bus and simplifying PCB routing. When the
pin is tied to high, the CMOS outputs are in normal order, otherwise the CMOS outputs are in reverse order.
10.2.2.3 Power-Up Sequence
The SN75LVDS822 does not require a specific power up sequence.
It is permitted to power up IOVCC while VCC remains powered down and connected to GND. The input level of
the SHTDN during this time does not matter as only the input stage is powered up while all other device blocks
are still powered down. It is also permitted to power up all 3.3V power domains while IOVCC is still powered
down to GND. The device will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH,
regardless of their true input voltage level. Hence, connecting SHTDN to GND will still be interpreted as a logic
HIGH; the LVDS output stage will turn on. The power consumption in this condition is significantly higher than
standby mode, but still lower than normal mode. The user experience can be impacted by the way a system
powers up and powers down an LCD screen. The following sequence is recommended:
Power up sequence (SN75LVDS83B SHTDN input initially low):
1. Ramp up LCD power and SN65LVDS822 (maybe 0.5ms to 10ms) but keep backlight turned off.
24
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SN65LVDS822
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ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
2. Wait for additional 0-200ms to ensure display noise won’t occur.
3. Enable video source output; start sending black video data.
4. Toggle LVDS83B shutdown to SHTDN = VIH.
5. Toggle LVDS822 shutdown to SHTDN = VIH.
6. Send > 1 ms of black video data; this allows the LVDS83B to be phase locked, and the display to show black
data first.
7. Start sending true image data.
8. Enable backlight.
Power Down sequence (SN75LVDS83B SHTDN input initially high):
1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for > 2 frame times.
3. Set SN75LVDS83B input SHTDN = GND; wait for 250 ns.
4. Set SN75LVDS822 input SHTDN = GND; wait for 250 ns.
5. Disable the video output of the video source.
6. Remove power from the LCD panel for lowest system power.
10.2.3 Application Curve
图 21. Total Current Consumption (VDD & VDDIO)
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SN65LVDS822
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
11 Power Supply Recommendations
11.1 Decoupling Capacitor Recommendations
To minimize the power supply noise floor, provide good decoupling near the SN65LVDS822 power pins. It is
recommended to place one 0.01-μF ceramic capacitor at each power pin, and two 0.1-μF ceramic capacitors on
each power node. The distance between the SN65LVDS822 and capacitors should be minimized to reduce loop
inductance and provide optimal noise filtering. Placing the capacitor underneath the SN65LVDS822 on the
bottom of the PCB is often a good choice. A 100-pF ceramic capacitor can be put at each power pin to optimize
the EMI performance.
12 Layout
12.1 Layout Guidelines
Use 45 degree bends (chamfered corners), instead of right-angle (90°) bends. Right-angle bends increase the
effective trace width, which changes the differential trace impedance creating large discontinuities. A 45o bends
is seen as a smaller discontinuity.
Place passive components within the signal path, such as source-matching resistors or ac-coupling capacitors,
next to each other. Routing as in case a) creates wider trace spacing than in b), the resulting discontinuity,
however, is limited to a far narrower area.
When routing traces next to a via or between an array of vias, make sure that the via clearance section does not
interrupt the path of the return current on the ground plane below.
Avoid metal layers and traces underneath or between the pads off the DisplayPort connectors for better
impedance matching. Otherwise they will cause the differential impedance to drop below 75 Ω and fail the board
during TDR testing.
Use solid power and ground planes for 100 Ω impedance control and minimum power noise.
For a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all
ground terminals directly to this plane. For 100 Ω differential impedance, use the smallest trace spacing possible,
which is usually specified by the PCB vendor.
Keep the trace length as short as possible to minimize attenuation.
Place bulk capacitors (i.e. 10 μF) close to power sources, such as voltage regulators or where the power is
supplied to the PCB.
26
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SN65LVDS822
www.ti.com.cn
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
12.2 Layout Example
图 22. Layout Example
图 23. Footprint Example
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27
SN65LVDS822
ZHCSBQ4B –SEPTEMBER 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
13 器件和文档支持
13.1 商标
Flatlink is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
14 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
28
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65LVDS822RGZR
ACTIVE
VQFN
RGZ
48
2500 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
LVDS822
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Mar-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LVDS822RGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Mar-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGZ 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
SN65LVDS822RGZR
2500
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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