SN65LVDS93BIDGGRQ1 [TI]
10MHz - 85MHz 汽车类 28 位平板显示器链路 LVDS | DGG | 56 | -40 to 85;
| 型号： | SN65LVDS93BIDGGRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10MHz - 85MHz 汽车类 28 位平板显示器链路 LVDS | DGG | 56 | -40 to 85 驱动 光电二极管 接口集成电路 驱动器 显示器 |
| 文件： | 总35页 (文件大小：1926K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN65LVDS93B-Q1
ZHCSHV1A –MARCH 2018–REVISED MAY 2018
SN65LVDS93B-Q1 10MHz - 85MHz 汽车级 28 位平板显示链路 LVDS
SerDes 发变送器
1 特性
发送数据时，数据位 D0 至 D27 会在输入时钟信号
(CLKIN) 边沿逐个载入寄存器。可通过时钟选择
(CLKSEL) 引脚来选择时钟的上升沿或下降沿。CLKIN
的频率会进行 7 倍倍频，然后用于以串行方式分 7 位
时间片上传数据寄存器。接着会将 4 个串行数据流和
锁相时钟 (CLKOUT) 输出至 LVDS 输出驱动器。
CLKOUT 的频率与输入时钟 (CLKIN) 相同。
1
•
符合面向汽车应用的 AEC-Q100 标准， 具有
–
–
温度等级 3：-40°C 至 85°C
人体放电模型 (HBM) 静电放电 (ESD) 分类等级
3
–
组件充电模式 (CDM) ESD 分类等级 C6
•
低压差分信号 (LVDS) 显示系列接口，可直接连接
具有集成 LVDS 的 LCD 显示面板
SN65LVDS93B-Q1 无需外部组件，只需很少控制，甚
至无需控制。发送器输入端的数据总线与接收器输出端
的相同，数据传输对于用户而言是透明的。用户唯一能
够干预的是选择时钟上升沿（向 CLKSEL 输入高电
平）或下降沿（向 CLKSEL 输入低电平），以及能够
使用关断/清零 (SHTDN) 引脚。SHTDN 是一个低电平
有效输入，可禁用时钟并关断 LVDS 输出驱动器，从
而降低功耗。该信号为低电平时，可将所有内部寄存器
置为低电平。
•
•
封装：14mm x 6.1mm 薄型小外形尺寸 (TSSOP)
1.8V 至 3.3V 耐压数据输入，可直接连接低功耗、
低压应用和图形处理器
•
传输速率高达 85Mpps（百万像素/秒）；像素时钟
频率范围 10MHz 至 85MHz；最高支持 2.38Gbps
数据速率
•
•
•
适合 HVGA 到高清 (HD) 范围内的显示分辨率，并
且电磁干扰 (EMI) 较低
通过 3.3V 单电源供电运行，75MHz 频率下的功耗
为 170mW（典型值）
SN65LVDS93B-Q1 的额定工作环境温度范围为 –40°C
至 85°C。
28 个数据通道 + 时钟输入低压晶体管-晶体管逻辑
(TTL)，4 个数据通道 + 时钟输出低压差分
•
•
•
•
禁用时的功耗不到 1mW
器件信息(1)
可选上升或下降时钟沿触发输入
支持扩频时钟 (SSC)
器件型号
封装
封装尺寸（标称值）
SN65LVDS93B-Q1
TSSOP (56)
14.00mm x 6.10mm
支持从 RGB 888 转换至 LVDS I
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
2 应用范围
简化原理图
•
•
•
汽车导航显示屏
R[0:7]
汽车仪表组显示屏
汽车中心堆栈显示屏
TFT LCD Display
G[0:7]
Y0:3M
Y0:3P
B[0:7]
Application
Processor
With
LVCMOS/RGB
Output
RGB to LVDS
Bridge
3 说明
SN65LVDS93B-Q1
HSYNC
VSYNC
CLKOUTM/P
SN65LVDS93B-Q1 变送器在单个集成电路中融合了 4
个 7 位并行负载串行输出移位寄存器、1 个 7X 时钟合
成器以及 5 个低电压差动信号 (LVDS) 线路驱动器。
借助这些功能，可通过 5 个平衡对导体将 28 位单端
LVTTL 数据同步发送至兼容接收器，如
EN
CLK
24 bit TCON
DS90CR286A-Q1 和具有集成 LVDS 接收器的 LCD
面板。
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSF42
SN65LVDS93B-Q1
ZHCSHV1A –MARCH 2018–REVISED MAY 2018
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 16
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements................................................ 6
6.7 Switching Characteristics.......................................... 8
6.8 Typical Characteristics.............................................. 9
Parameter Measurement Information .................. 9
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
9
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 24
12 器件和文档支持 ..................................................... 26
12.1 商标....................................................................... 26
12.2 静电放电警告......................................................... 26
12.3 接收文档更新通知 ................................................. 26
12.4 社区资源................................................................ 26
12.5 术语表 ................................................................... 26
13 机械、封装和可订购信息....................................... 26
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (March 2018) to Revision A
Page
•
将器件状态从预告信息 更改为生产数据.................................................................................................................................. 1
2
Copyright © 2018, Texas Instruments Incorporated
SN65LVDS93B-Q1
www.ti.com.cn
ZHCSHV1A –MARCH 2018–REVISED MAY 2018
5 Pin Configuration and Functions
DGG Package
56-PIN (TSSOP)
(Top View)
IOVCC
D5
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
D4
2
D3
D6
3
D2
D7
4
GND
D1
GND
D8
5
6
D0
D9
7
D27
D10
VCC
D11
D12
D13
GND
D14
D15
D16
CLKSEL
D17
D18
D19
GND
D20
D21
D22
D23
IOVCC
D24
D25
8
GND
Y0M
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Y0P
Y1M
Y1P
LVDSVCC
GND
Y2M
Y2P
CLKOUTM
CLKOUTP
Y3M,Y3P
Y3P
GND
GND
PLLVCC
GND
SHTDN
CLKIN
D26
GND
Not to scale
Copyright © 2018, Texas Instruments Incorporated
3
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ZHCSHV1A –MARCH 2018–REVISED MAY 2018
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Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
CMOS IN with
pulldn
CLKIN
31
Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL.
CLKOUTP
CLKOUTM
39
40
Differential LVDS pixel clock output.
Output is high-impedance when SHTDN is pulled low (de-asserted).
LVDS Out
CMOS IN with
pulldn
Selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input clock
trigger (CLKSEL = VIL).
CLKSEL
17
2, 3, 4, 6
7, 8, 10, 11
12, 14, 15 , 16
18, 19, 20, 22
23, 24, 25, 27
28, 30, 50
D5, D6, D7, D8
Data inputs; supports 1.8 V to 3.3 V input voltage selectable by VDD supply. To connect a
graphic source successfully to a display, the bit assignment of D[27:0] is critical (and not
necessarily intuitive).
For input bit assignment see to for details.
Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16,
D17, D23, and D27 to GND.
D9, D10, D11, D12
D13, D14, D15, D16
D17, D18, D19, D20
D21, D22, D23, D24
D25, D26, D27
CMOS IN with
pulldn
51, 52, 54, 55,
56
D0, D1, D2, D3, D4
5, 13, 21, 29, 33,
35, 36, 43, 49,
53
GND
Power Supply(1) Supply ground for VCC, IOVCC, LVDSVCC, and PLLVCC.
IOVCC
1, 26
44
Power Supply(1) I/O supply reference voltage (1.8 V up to 3.3 V matching the GPU data output signal swing)
Power Supply(1) 3.3 V LVDS output analog supply
Power Supply(1) 3.3 V PLL analog supply
LVDSVCC
PLLVCC
34
CMOS IN with
pulldn
Device shut down; pull low (de-assert) to shut down the device (low power, resets all
registers) and high (assert) for normal operation.
SHTDN
32
VCC
Y0P
Y0M
Y1P
Y1M
Y2P
Y2M
Y3P
9
Power Supply(1) 3.3 V digital supply voltage
47
48
45
45
41
42
37
Differential LVDS data outputs.
LVDS Out
Outputs are high-impedance when SHTDN is pulled low (de-asserted)
Differential LVDS Data outputs.
LVDS Out
Output is high-impedance when SHTDN is pulled low (de-asserted).
Note: if the application only requires 18-bit color, this output can be left open.
Y3M
38
(1) For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals
directly to this plane.
4
Copyright © 2018, Texas Instruments Incorporated
SN65LVDS93B-Q1
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ZHCSHV1A –MARCH 2018–REVISED MAY 2018
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.5
–0.5
–0.5
MAX
4
UNIT
Supply voltage range, VCC, IOVCC, LVDSVCC, PLLVCC(2)
Voltage range at any output terminal
Voltage range at any input terminal
Continuous power dissipation
V
V
V
VCC + 0.5
IOVCC + 0.5
See Thermal Information
–65 150
Storage temperature, Tstg
°C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) All voltages are with respect to the GND terminals.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. e.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
3
NOM
MAX
3.6
3.6
3.6
3.6
0.1
UNIT
Supply voltage, VCC
3.3
3.3
LVDS output Supply voltage, LVDSVCC
PLL analog supply voltage, PLLVCC
IO input reference supply voltage, IOVCC
Power supply noise on any VCC terminal
3
3
3.3
V
1.62
1.8 / 2.5 / 3.3
IOVCC = 1.8 V
IOVCC = 2.5 V
IOVCC = 3.3 V
IOVCC = 1.8 V
IOVCC = 2.5 V
IOVCC = 3.3 V
IOVCC/2 + 0.3 V
IOVCC/2 + 0.4 V
IOVCC/2 + 0.5 V
High-level input voltage, VIH
Low-level input voltage, VIL
V
V
IOVCC/2 - 0.3 V
IOVCC/2 - 0.4 V
IOVCC/2 - 0.5 V
Differential load impedance, ZL
Operating free-air temperature, TA
Virtual junction temperature, TJ
90
132
85
Ω
–40
°C
°C
105
6.4 Thermal Information
SN65LVDS93B-Q1
THERMAL METRIC(1)
DGG (TSSOP)
56 PINS
63.4
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
15.9
32.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.4
ψJB
32.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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ZHCSHV1A –MARCH 2018–REVISED MAY 2018
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Thermal Information (continued)
SN65LVDS93B-Q1
DGG (TSSOP)
56 PINS
THERMAL METRIC(1)
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
V
VT
Input voltage threshold
IOVCC/2
Differential steady-state output voltage
magnitude
mV
|VOD
|
250
450
35
RL = 100Ω, See 图 5
Change in the steady-state differential
output voltage magnitude between
opposite binary states
Δ|VOD
|
1
mV
Steady-state common-mode output
voltage
VOC(SS)
VOC(PP)
1.125
1.375
35
V
See 图 5
tR/F (Dx, CLKin) = 1ns
Peak-to-peak common-mode output
voltage
mV
IIH
IIL
High-level input current
Low-level input current
VIH = IOVCC
VIL = 0 V
25
±10
±24
±12
±20
μA
μA
VOY = 0 V
mA
mA
μA
IOS
Short-circuit output current
VOD = 0 V
IOZ
High-impedance state output current
VO = 0 V to VCC
IOVCC = 1.8 V
IOVCC = 3.3 V
200
100
Input pull-down integrated resistor on all
inputs (Dx, CLKSEL, SHTDN, CLKIN)
Rpdn
kΩ
μA
disabled, all inputs at GND;
SHTDN = VIL
IQ
Quiescent current (average)
10
100
SHTDN = VIH, RL = 100Ω (5 places),
grayscale pattern (图 6)
VCC = 3.3 V, fCLK = 75 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC)
51.9
0.4
I(IOVCC) with IOVCC = 3.3 V
I(IOVCC) with IOVCC = 1.8 V
mA
mA
0.1
SHTDN = VIH, RL = 100Ω (5 places), worst-
case pattern (图 7),
VCC = 3.6 V, fCLK = 75 MHz
ICC
Supply current (average)
I(VCC) + I(PLLVCC) + I(LVDSVCC)
I(IOVCC) with IOVCC = 3.3 V
I(IOVCC) with IOVCC = 1.8 V
63.7
1.3
0.5
SHTDN = VIH, RL = 100Ω (5 places), worst-
case pattern (图 7),
fCLK = 85 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC)
I(IOVCC) with IOVCC = 3.6 V
I(IOVCC) with IOVCC = 1.8 V
75.1
1.5
0.6
2
mA
pF
CI
Input capacitance
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Timing Requirements
PARAMETER
MIN
MAX
UNIT
Input clock period, tc
7.4
100
8%
ns
with modulation frequency 30 kHz
with modulation frequency 50 kHz
Input clock modulation
6%
High-level input clock pulse width duration, tw
Input signal transition time, tt
0.4 tc
0.6 tc
3
ns
ns
6
Copyright © 2018, Texas Instruments Incorporated
SN65LVDS93B-Q1
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ZHCSHV1A –MARCH 2018–REVISED MAY 2018
Timing Requirements (continued)
PARAMETER
MIN
2
MAX
UNIT
ns
Data set up time, D0 through D27 before CLKIN (See 图 4)
Data hold time, D0 through D27 after CLKIN
0.8
ns
Dn
CLKIN
or
CLKIN
CLKOUT
Previous cycle
Next
Current cycle
Y0
Y1
Y2
Y3
D7+1
D0-1
D8-1
D7
D18
D26
D23
D6
D15
D25
D17
D4
D14
D24
D16
D3
D13
D22
D11
D2
D1
D9
D0
D8
D12
D21
D10
D18+1
D26+1
D23+1
D19-1
D27-1
D20
D5
D19
D27
图 1. Typical SN65LVDS93B-Q1 Load and Shift Sequences
LVDSVCC
IOVCC
5W
YnP or
YnM
D or
SHTDN
50W
10kW
7V
7V
300kW
图 2. Equivalent Input and Output Schematic Diagrams
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ZHCSHV1A –MARCH 2018–REVISED MAY 2018
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6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Delay time, CLKOUT↑ after Yn valid
(serial bit position 0, equal D1, D9,
D20, D5)
t0
t1
t2
t3
t4
t5
-0.1
0
0.1
7 tc + 0.1
7 tc + 0.1
7 tc + 0.1
7 tc + 0.1
7 tc + 0.1
7 tc + 0.1
ns
Delay time, CLKOUT↑ after Yn valid
(serial bit position 1, equal D0, D8,
D19, D27)
1
2
3
4
5
6
1
2
3
4
5
6
/
/
/
/
/
/
7 tc - 0.1
7 tc - 0.1
7 tc - 0.1
7 tc - 0.1
7 tc - 0.1
7 tc - 0.1
/
/
/
/
/
/
ns
ns
ns
ns
ns
Delay time, CLKOUT↑ after Yn valid
(serial bit position 2, equal D7, D18,
D26. D23)
Delay time, CLKOUT↑ after Yn valid
(serial bit position 3; equal D6, D15,
D25, D17)
See 图 8, tC = 10ns,
|Input clock jitter| < 25ps
(2)
Delay time, CLKOUT↑ after Yn valid
(serial bit position 4, equal D4, D14,
D24, D16)
Delay time, CLKOUT↑ after Yn valid
(serial bit position 5, equal D3, D13,
D22, D11)
Delay time, CLKOUT↑ after Yn valid
(serial bit position 6, equal D2, D12,
D21, D10)
t6
ns
ns
tc(o)
Output clock period
tc
tC = 10ns; clean reference clock, see
图 9
±35
tC = 10ns with 0.05UI added noise
modulated at 3MHz, see 图 9
±44
±35
(3)
Δtc(o)
Output clock cycle-to-cycle jitter
ps
tC = 7.4ns; clean reference clock,
see 图 9
tC = 7.4ns with 0.05UI added noise
modulated at 3MHz, see 图 9
±42
High-level output clock pulse
duration
4
tw
/
7 tc
ns
ps
µs
ns
Differential output voltage transition
time (tr or tf)
tr/f
ten
tdis
See 图 5
225
10
500
Enable time, SHTDN↑ to phase lock
(Yn valid)
f(clk) = 85MHz, See 图 10
f(clk) = 85MHz, See 图 11
Disable time, SHTDN↓ to off-state
(CLKOUT high-impedance)
12
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed
over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.
8
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SN65LVDS93B-Q1
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ZHCSHV1A –MARCH 2018–REVISED MAY 2018
6.8 Typical Characteristics
80
70
60
50
V
= 3.6 V
CC
40
V
= 3 V
CC
30
20
V
= 3.3 V
CC
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
- Clock Frequency - MHz
f
clk
Total Device Current (Using Grayscale pattern) Over Pixel Clock Frequency
图 3. Average Grayscale ICC vs Clock Frequency
7 Parameter Measurement Information
tsu
thold
Dn
CLKIN
All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns.
CLKSEL = 0 V.
图 4. Set Up and Hold Time Definition
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ZHCSHV1A –MARCH 2018–REVISED MAY 2018
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49.9W ꢀ1 ꢁ( ꢂPLCS
Yꢂ
V
OD
V
YM
OL
ꢀ001
801
V
ODꢁHS
0V
V
ODꢁPS
(01
01
t
t
r
f
V
OLꢁꢂꢂS
V
V
OLꢁCCS
OLꢁCCS
0V
图 5. Test Load and Voltage Definitions for LVDS Outputs
CLKIN
D0,8,16
D1,9,17
D2,10,18
D3,11,19
D4-7,12-15,20-23
D24-27
The 16 grayscale test pattern test device power consumption for a typical display pattern.
图 6. 16 Grayscale Test Pattern
T
CLKIN
EVEN Dn
ODD Dn
The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.
图 7. Worst-Case Power Test Pattern
10
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ZHCSHV1A –MARCH 2018–REVISED MAY 2018
t7
CLKIN
CLKOUT
t6
t5
t4
t3
t2
t1
t0
Yn
VOD(H)
0.00V
~2.5V
1.40V
~0.5V
CLKOUT
or Yn
CLKIN
VOD(L)
t7
t0-6
CLKOUT is shown with CLKSEL at high-level.
CLKIN polarity depends on CLKSEL input level.
图 8. SN65LVDS93B-Q1 Timing Definitions
Device
Under
Test
+
Reference
VCO
+
Modulation
v(t) = A sin(2 pf
t)
mod
HP8656B Signal
Generator,
0.1 MHz-990 MHz
HP8665A Synthesized
Signal Generator,
0.1 MHz-4200 MHz
Device Under
Test
DTS2070C
Digital
TimeScope
Input
RF Output
CLKIN
CLKOUT
RF Output
Modulation Input
图 9. Output Clock Jitter Test Set Up
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CLKIN
Dn
ten
SHTDN
Yn
Invalid
Valid
图 10. Enable Time Waveforms
CLKIN
tdis
SHTDN
CLKOUT
图 11. Disable Time Waveforms
12
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SN65LVDS93B-Q1
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ZHCSHV1A –MARCH 2018–REVISED MAY 2018
8 Detailed Description
8.1 Overview
The SN65LVDS93B-Q1 takes in three (or four) data words each containing seven single-ended data bits and
converts this to an LVDS serial output. Each serial output runs at seven times that of the parallel data rate. The
deserializer (receiver) device operates in the reverse manner. The three (or four) LVDS serial inputs are
transformed back to the original seven-bit parallel single-ended data. Additional TI solutions are available in 21:3
or 28:4 SerDes ratios.
•
The 21-bit devices are designed for 6-bit RGB video for a total of 18 bits in addition to three extra bits for
horizontal synchronization, vertical synchronization, and data enable.
•
The 28-bit devices are intended for 8-bit RGB video applications. Again, the extra four bits are for horizontal
synchronization, vertical synchronization, data enable, and the remaining is the reserved bit. These 28-bit
devices can also be used in 6-bit and 4-bit RGB applications as shown in the subsequent system diagrams.
8.2 Functional Block Diagram
Parallel-Load 7-bit
Shift Register
D0, D1, D2, D3,
D4, D6, D7
7
7
7
7
Y0P
Y0M
A,B,...G
SHIFT/LOAD
>CLK
Parallel-Load 7-bit
Shift Register
D8, D9, D12, D13,
D14, D15, D18
Y1P
Y1M
A,B,...G
SHIFT/LOAD
>CLK
Parallel-Load 7-bit
ShiftRegister
D19, D20, D21, D22,
D24, D25, D26
Y2P
Y2M
A,B,...G
SHIFT/LOAD
>CLK
Parallel-Load 7-bit
Shift Register
D5, D10, D11, D16,
D17, D23, D27
Y3P
Y3M
A,B,...G
SHIFT/LOAD
>CLK
Control Logic
SHTDN
7X Clock/PLL
7XCLK
CLKOUTP
CLKOUTM
>CLK
CLKIN
CLKINH
CLKSEL
RISING/FALLING EDGE
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8.3 Feature Description
8.3.1 TTL Input Data
The data inputs to the transmitter come from the graphics processor and consist of up to 24 bits of video
information, a horizontal synchronization bit, a vertical synchronization bit, an enable bit, and a spare bit. The
data can be loaded into the registers upon either the rising or falling edge of the input clock selectable by the
CLKSEL pin. Data inputs are 1.8 V to 3.3 V tolerant for the SN65LVDS93B-Q1 and can connect directly to low-
power, low-voltage application and graphic processors. The bit mapping is listed in 表 1.
表 1. Pixel Bit Ordering
RED
R0
R1
R2
R3
R4
R5
R6
R7
GREEN
G0
BLUE
B0
LSB
G1
B1
G2
B2
4-bit MSB
6-bit MSB
G3
B3
G4
B4
G5
B5
G6
B6
8-bit MSB
G7
B7
8.3.2 LVDS Output Data
The pixel data assignment is listed in 表 2 for 24-bit, 18-bit, and 12-bit color hosts.
表 2. Pixel Data Assignment
8-BIT
6-BIT
4-BIT
SERIAL
CHANNEL
DATA BITS
NON-LINEAR STEP LINEAR STEP
FORMAT-1
FORMAT-2
FORMAT-3
SIZE
SIZE
VCC
GND
R0
D0
D1
R0
R1
R2
R3
R2
R3
R0
R1
R2
R3
D2
R2
R4
R4
R2
R0
Y0
Y1
Y2
D3
R3
R5
R5
R3
R1
R1
D4
R4
R6
R6
R4
R2
R2
D6
R5
R7
R7
R5
R3
R3
D7
G0
G2
G2
G0
G2
VCC
GND
G0
D8
G1
G3
G3
G1
G3
D9
G2
G4
G4
G2
G0
D12
D13
D14
D15
D18
D19
D20
D21
D22
D24
D25
D26
G3
G5
G5
G3
G1
G1
G4
G6
G6
G4
G2
G2
G5
G7
G7
G5
G3
G3
B0
B2
B2
B0
B2
VCC
GND
B0
B1
B3
B3
B1
B3
B2
B4
B4
B2
B0
B3
B5
B5
B3
B1
B1
B4
B6
B6
B4
B2
B2
B5
B7
B7
B5
B3
B3
HSYNC
VSYNC
ENABLE
HSYNC
VSYNC
ENABLE
HSYNC
VSYNC
ENABLE
HSYNC
VSYNC
ENABLE
HSYNC
VSYNC
ENABLE
HSYNC
VSYNC
ENABLE
14
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表 2. Pixel Data Assignment (接下页)
8-BIT
6-BIT
4-BIT
SERIAL
CHANNEL
DATA BITS
NON-LINEAR STEP LINEAR STEP
FORMAT-1
FORMAT-2
FORMAT-3
SIZE
GND
GND
GND
GND
GND
GND
GND
CLK
SIZE
GND
GND
GND
GND
GND
GND
GND
CLK
D27
D5
R6
R7
R0
R1
GND
GND
GND
GND
GND
GND
GND
CLK
GND
GND
GND
GND
GND
GND
GND
CLK
D10
D11
D16
D17
D23
CLKIN
G6
G0
Y3
G7
G1
B6
B0
B7
B1
RSVD
CLK
RSVD
CLK
CLKOUT
8.4 Device Functional Modes
8.4.1 Input Clock Edge
The transmission of data bits D0 through D27 occurs as each are loaded into registers upon the edge of the
CLKIN signal, where the rising or falling edge of the clock may be selected via CLKSEL. The selection of a clock
rising edge occurs by inputting a high level to CLKSEL, which is achieved by populating pull-up resistor to pull
CLKSEL=high. Inputting a low level to select a clock falling edge is achieved by directly connecting CLKSEL to
GND.
8.4.2 Low Power Mode
The SN65LVDS93B-Q1 can be put in low-power consumption mode by active-low input SHTDN#. Connecting
pin SHTDN# to GND will inhibit the clock and shut off the LVDS output drivers for lower power consumption. A
low-level on this signal clears all internal registers to a low-level. Populate a pull-up to VCC on SHTDN# to
enable the device for normal operation.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This section describes the power up sequence, provides information on device connectivity to various GPU and
LCD display panels, and offers a PCB routing example.
9.2 Typical Application
J1
U1H
J2
sma_surface
C3
GND1
C5
GND2
D3
GND3
F5
J3
GND4
sma_surface
G3
H3
J5
A1
B1
F2
U1A
GND5
D1
D2
GND6
CLKM
CLKP
GND7
J4
PLLGND
LVDSGND1
LVDSGND2
sma_surface
H2
H1
Y0P
Y0M
G2
G1
J5
sma_surface
Y1P
Y1M
SN65LVDS93B
E1
E2
Y2P
Y2M
J6
sma_surface
IOVCC
C2
C1
Y3P
Y3M
R4
R5
R6
R7
R8
R9
R10
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
J7
sma_surface
JMP1
SN65LVDS93B
U1B
J2
D0
D1
D2
D3
D4
D6
D7
D0
K1
D1
K2
1
2
J8
sma_surface
D2
J3
D3
K3
D4
J4
J9
D6
K5
D7
sma_surface
14
Header 7x2
SN65LVDS93B
J10
sma_surface
IOVCC
R11
4.7k
R12
4.7k
R13
4.7k
R14
4.7k
R15
4.7k
R16
4.7k
R17
4.7k
sma_surface
JMP2
U1C
K6
D8
D8
J6
D9
1
2
D9
IOVCC
IOVCC
G5
D12
D13
D14
D15
D18
D12
G6
D13
F6
D14
E5
D15
D5
D18
14
R1
R2
Header 7x2
4.7k
SN65LVDS93B
IOVCC
R18
4.7k
R19
4.7k
R20
4.7k
R21
4.7k
R22
4.7k
R23
4.7k
R24
4.7k
JMP6
U1G
JMP3
B3
SHTDN
U1D
SHTDN
1
3
2
4
D4
CLKSEL
C6
D19
D19
D20
D21
D22
D24
D25
D26
CLKSEL
1
2
B6
D20
Header 2x2
B5
D21
A6
D22
SN65LVDS93B
A4
D24
B4
D25
A3
D26
14
U1J
E3
NC1
Header 7x2
E4
NC2
SN65LVDS93B
F3
NC3
F4
NC4
IOVCC
R25
4.7k
R26
4.7k
R27
4.7k
R28
4.7k
R29
4.7k
R30
4.7k
R31
4.7k
SN65LVDS93B
JMP4
U1E
K4
D5
D5
VCC
IOVCC
1
2
H4
D10
H6
D10
D11
D16
D17
D23
D27
U1I
D11
E6
D16
G4
B2
F1
VCC
PLLVCC
D6
D17
A5
D23
LVDSVCC
J1
D27
14
H5
C4
IOVCC1
IOVCC2
Header 7x2
SN65LVDS93B
SN65LVDS93B
VCC
VCC
VCC
IOVCC
C31
1uF
C32
0.1uF
C33
0.01uF
C34
1uF
C35
0.1uF
C36
0.01uF
C40
1uF
C41
C42
C37
1uF
C38
C39
0.1uF
0.01uF
0.1uF
0.01uF
PLACE UNDER LVDS93B-Q1
(bottom pcb side)
图 12. Schematic Example
16
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ZHCSHV1A –MARCH 2018–REVISED MAY 2018
Typical Application (接下页)
9.2.1 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
VCC
VCCIO
CLKIN
3.3 V
1.8 V
Falling edge
High
SHTDN#
Format
18-bit GPU to 24-bit LCD
9.2.2 Detailed Design Procedure
9.2.2.1 Power Up Sequence
The SN65LVDS93B-Q1 does not require a specific power up sequence.
It is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to
GND. The input level of the SHTDN during this time does not matter as only the input stage is powered up while
all other device blocks are still powered down.
It is also permitted to power up all 3.3V power domains while IOVCC is still powered down to GND. The device
will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH, regardless of their true
input voltage level. Hence, connecting SHTDN to GND will still be interpreted as a logic HIGH; the LVDS output
stage will turn on. The power consumption in this condition is significantly higher than standby mode, but still
lower than normal mode.
The user experience can be impacted by the way a system powers up and powers down an LCD screen. The
following sequence is recommended:
Power up sequence (SN65LVDS93B-Q1 SHTDN input initially low):
A. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off.
B. Wait for additional 0-200ms to ensure display noise won’t occur.
C. Enable video source output; start sending black video data.
D. Toggle SN65LVDS93B-Q1 shutdown to SHTDN = VIH.
E. Send >1ms of black video data; this allows the SN65LVDS93B-Q1 to be phase locked, and the display to
show black data first.
F. Start sending true image data.
G. Enable backlight.
Power Down sequence (SN65LVDS93B-Q1 SHTDN input initially high):
A. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
B. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for >2 frame times.
C. Set SN65LVDS93B-Q1 input SHTDN = GND; wait for 250ns.
D. Disable the video output of the video source.
E. Remove power from the LCD panel for lowest system power.
9.2.2.2 Signal Connectivity
While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the
industry has aligned over the years on a certain data format (bit order). 图 13 through 图 15 show how each
signal should be connected from the graphic source through the SN65LVDS93B-Q1 input, output and LVDS LCD
panel input. Detailed notes are provided with each figure.
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24-bpc GPU
SN65LVDS93B-Q1
FORMAT1 FORMAT2 (See Note A)
R0(LSB)
R1
R2
D0
D1
D27
D5
D2
D3
D4
D6
D27
D5
D7
D8
D0
D1
D2
D3
R3
R4
R5
R6
Y0M
Y0P
100
100
to column
driver
D4
R7(MSB)
G0(LSB)
G1
D6
Y1M
Y1P
D10
D11
D7
FPC
Cable
LVDS
timing
Controller
G2
G3
D9
Y2M
Y2P
100
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
D8
G4
D9
(8bpc, 24bpp)
G5
G6
D12
D13
D14
D16
D17
D15
D18
D19
D20
D21
D22
D24
D25
D26
D23
Y3M
Y3P
100
to row driver
G7(MSB)
B0(LSB)
B1
CLKOUTM
CLKOUTP
100
B2
B3
B4
B5
24-bpp LCD Display
B6
B7(MSB)
HSYNC
VSYNC
ENABLE
RSVD (Note C)
CLK
CLKIN CLKIN
4.8k
3.3V
C2
3.3V
C3
1.8V or 2.5V
or 3.3V
C1
Rpullup
Rpulldown
(See Note B)
Main Board
Note A. FORMAT: The majority of 24-bit LCD display panels require the two most significant bits (2 MSB ) of each
color to be transferred over the 4th serial data output Y3. A few 24-bit LCD display panels require the two LSBs of
each color to be transmitted over the Y3 output. The system designer needs to verify which format is expected by
checking the LCD display data sheet.
•
Format 1: use with displays expecting the 2 MSB to be transmitted over the 4th data channel Y3. This is the
dominate data format for LCD panels.
•
Format 2: use with displays expecting the 2 LSB to be transmitted over the 4th data channel.
Note B. Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
•
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Note C. If RSVD is not driven to a valid logic level, then an external connection to GND is recommended.
Note D. RSVD must be driven to a valid logic level. All unused SN65LVDS93B-Q1 inputs must be tied to a valid logic
level.
图 13. 24-Bit Color Host to 24-Bit LCD Panel Application
18
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SN65LVDS93B-Q1
www.ti.com.cn
ZHCSHV1A –MARCH 2018–REVISED MAY 2018
18-bpp GPU
SN65LVDS93B-Q1
R0(LSB)
R1
R2
D0
D1
D2
R3
R4
D3
D4
D6
Y0M
Y0P
100
R5(MSB)
to column
driver
D27
D5
D7
D8
Y1M
Y1P
100
G0(LSB)
G1
G2
FPC
Cable
D9
Y2M
Y2P
LVDS
100
timing
Controller
(6-bpc, 18-bpp)
G3
G4
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
G5(MSB)
CLKOUTM
CLKOUTP
100
to row driver
B0(LSB)
B1
B2
B3
B4
B5(MSB)
18-bpp LCD Display
Y3M
Y3P
(See Note A)
HSYNC
VSYNC
ENABLE
RSVD
CLK
3.3V
C2
3.3V
C3
4.8k
1.8V or 2.5V
or 3.3V
C1
Rpullup
Rpulldown
(See Note B)
Main Board
Note A. Leave output Y3 NC.
Note B.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
•
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
图 14. 18-Bit Color Host to 18-Bit Color LCD Panel Display Application
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24-bpp GPU
SN65LVDS93B-Q1
R0 and R1: NC
(See Note B)
R2
D0
R3
R4
D1
D2
R5
R6
D3
D4
D6
Y0M
Y0P
100
100
R7(MSB)
to column
driver
D27
D5
D7
D8
G0 and G1: NC
(See Note B)
Y1M
Y1P
G2
G3
FPC
Cable
G4
G5
G6
D9
Y2M
Y2P
LVDS
timing
Controller
100
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
(6-bpc, 18-bpp)
G7(MSB)
CLKOUTM
CLKOUTP
100
to row driver
B0 and B1: NC
(See Note B)
B2
B3
B4
B5
B6
B7(MSB)
18-bpp LCD Display
B0 and B1: NC
(See Note B)
Y3M
Y3P
(See Note A)
HSYNC
VSYNC
ENABLE
RSVD
CLK
4.8k
3.3V
C2
3.3V
C3
1.8V or 2.5V
or 3.3V
C1
Rpullup
Rpulldown
(See Note C)
Main Board
Note A. Leave output Y3 NC.
Note B. R0, R1, G0, G1, B0, B1: For improved image quality, the GPU should dither the 24-bit output pixel down
to18-bit per pixel.
NoteC.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
•
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
图 15. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application
20
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SN65LVDS93B-Q1
www.ti.com.cn
ZHCSHV1A –MARCH 2018–REVISED MAY 2018
9.2.2.3 PCB Routing
图 16 shows a possible breakout of the data input and output signals on two layers of a printed circuit board.
D27
D5
D10
D11
D16
D17
D23
Y0M
Y0P
D19
D20
D21
D22
D24
D25
D26
Y1M
Y1P
Y2M
Y2P
D8
D9
CLKINM
CLKINP
D12
D13
D14
D15
D18
Y3M
Y3P
D0
D1
D2
D3
D4
D6
D7
图 16. Printed Circuit Board Routing Example (See 图 12 for the Schematic)
9.2.3 Application Curve
250
200
150
100
50
0
1
4
7
10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64
Pixel Samples
图 17. 18b GPU to 24b LCD
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21
SN65LVDS93B-Q1
ZHCSHV1A –MARCH 2018–REVISED MAY 2018
www.ti.com.cn
10 Power Supply Recommendations
Power supply PLL, IO, and LVDS pins must be uncoupled from each.
11 Layout
11.1 Layout Guidelines
11.1.1 Board Stackup
There is no fundamental information about how many layers should be used and how the board stackup should
look. Again, the easiest way the get good results is to use the design from the EVMs of Texas Instruments. The
magazine Elektronik Praxis has published an article with an analysis of different board stackups. These are listed
in 表 3. Generally, the use of microstrip traces needs at least two layers, whereas one of them must be a GND
plane. Better is the use of a four-layer PCB, with a GND and a VCC plane and two signal layers. If the circuit is
complex and signals must be routed as stripline, because of propagation delay and/or characteristic impedance,
a six-layer stackup should be used.
表 3. Possible Board Stackup on a Four-Layer PCB
MODEL 1
SIG
MODEL 2
SIG
MODEL 3
SIG
MODEL 4
GND
SIG
Layer 1
Layer 2
SIG
GND
GND
Layer 3
VCC
VCC
SIG
VCC
SIG
Layer 4
GND
SIG
VCC
Decoupling
EMC
Good
Bad
Good
Bad
Bad
Bad
Bad
Bad
Signal Integrity
Self Disturbance
Bad
Bad
Good
Satisfaction
Bad
Satisfaction
Satisfaction
High
11.1.2 Power and Ground Planes
A complete ground plane in high-speed design is essential. Additionally, a complete power plane is
recommended as well. In a complex system, several regulated voltages can be present. The best solution is for
every voltage to have its own layer and its own ground plane. But this would result in a huge number of layers
just for ground and supply voltages. What are the alternatives? Split the ground planes and the power planes? In
a mixed-signal design, e.g., using data converters, the manufacturer often recommends splitting the analog
ground and the digital ground to avoid noise coupling between the digital part and the sensitive analog part. Take
care when using split ground planes because:
•
•
Split ground planes act as slot antennas and radiate.
A routed trace over a gap creates large loop areas, because the return current cannot flow beside the signal,
and the signal can induce noise into the nonrelated reference plane (图 18).
•
With a proper signal routing, crosstalk also can arise in the return current path due to discontinuities in the
ground plane. Always take care of the return current (图 19).
For 图 19, do not route a signal referenced to digital ground over analog ground and vice versa. The return
current cannot take the direct way along the signal trace and so a loop area occurs. Furthermore, the signal
induces noise, due to crosstalk (dotted red line) into the analog ground plane.
22
版权 © 2018, Texas Instruments Incorporated
SN65LVDS93B-Q1
www.ti.com.cn
ZHCSHV1A –MARCH 2018–REVISED MAY 2018
图 18. Loop Area and Crosstalk Due to Poor Signal Routing and Ground Splitting
图 19. Crosstalk Induced by the Return Current Path
11.1.3 Traces, Vias, and Other PCB Components
A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner, and the
characteristic impedance changes. This impedance change causes reflections.
•
•
•
Avoid right-angle bends in a trace and try to route them at least with two 45° corners. To minimize any
impedance change, the best routing would be a round bend (see 图 20).
Separate high-speed signals (e.g., clock signals) from low-speed signals and digital from analog signals;
again, placement is important.
To minimize crosstalk not only between two signals on one layer but also between adjacent layers, route
them with 90° to each other.
版权 © 2018, Texas Instruments Incorporated
23
SN65LVDS93B-Q1
ZHCSHV1A –MARCH 2018–REVISED MAY 2018
www.ti.com.cn
图 20. Poor and Good Right Angle Bends
11.2 Layout Example
图 21. EVM Top Layer – TSSOP Package
24
版权 © 2018, Texas Instruments Incorporated
SN65LVDS93B-Q1
www.ti.com.cn
ZHCSHV1A –MARCH 2018–REVISED MAY 2018
Layout Example (接下页)
图 22. EVM VCC Layer – TSSOP Package
版权 © 2018, Texas Instruments Incorporated
25
SN65LVDS93B-Q1
ZHCSHV1A –MARCH 2018–REVISED MAY 2018
www.ti.com.cn
12 器件和文档支持
12.1 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
26
版权 © 2018, Texas Instruments Incorporated
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2018 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65LVDS93BIDGGRQ1
SN65LVDS93BIDGGTQ1
ACTIVE
ACTIVE
TSSOP
TSSOP
DGG
DGG
56
56
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
LVDS93BQ
LVDS93BQ
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LVDS93BIDGGRQ1 TSSOP
SN65LVDS93BIDGGTQ1 TSSOP
DGG
DGG
56
56
2000
250
330.0
330.0
24.4
24.4
8.6
8.6
15.6
15.6
1.8
1.8
12.0
12.0
24.0
24.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65LVDS93BIDGGRQ1
SN65LVDS93BIDGGTQ1
TSSOP
TSSOP
DGG
DGG
56
56
2000
250
367.0
367.0
367.0
367.0
45.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGG0056A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
2
0
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
54X 0.5
56
1
14.1
13.9
NOTE 3
2X
13.5
28
B
29
0.27
0.17
6.2
6.0
56X
1.2 MAX
0.08
C A
B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05)
TYP
SYMM
28
29
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222167/A 07/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05) TYP
SYMM
28
29
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
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