SN65LVDT101 [TI]
DIFFERENTIAL TRANSLATOR/REPEATER; 微分翻译/中继器
| 型号： | SN65LVDT101 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DIFFERENTIAL TRANSLATOR/REPEATER |
| 文件： | 总20页 (文件大小：668K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
DIFFERENTIAL TRANSLATOR/REPEATER
FEATURES
DESCRIPTION
•
•
•
•
•
Designed for Signaling Rates (1) ≥ 2 Gbps
Total Jitter < 65 ps
The SN65LVDS100, SN65LVDT100, SN65LVDS101,
and SN65LVDT101 are a high-speed differential re-
ceiver and driver connected as a repeater. The
receiver accepts low-voltage differential signaling
(LVDS), positive-emitter-coupled logic (PECL), or cur-
rent-mode logic (CML) input signals at rates up to 2
Gbps and repeats it as either an LVDS or PECL
output signal. The signal path through the device is
differential for low radiated emissions and minimal
added jitter.
Low-Power Alternative for the MC100EP16
Low 100 ps (Max) Part-To-Part Skew
25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Common-Mode Range
•
Inputs Electrically Compatible With LVPECL,
CML, and LVDS Signal Levels
•
•
•
3.3-V Supply Operation
The
outputs
of
the
SN65LVDS100
and
LVDT Integrates 110-Ω Terminating Resistor
Offered in SOIC and MSOP
SN65LVDT100 are LVDS levels as defined by
TIA/EIA-644-A. The outputs of the SN65LVDS101
and SN65LVDT101 are compatible with 3.3-V PECL
levels. Both drive differential transmission lines with
nominally 100-Ω characteristic impedance.
APPLICATIONS
•
•
•
•
•
622 MHz Central Office Clock Distribution
High-Speed Network Routing
Wireless Basestations
Low Jitter Clock Repeater
Serdes LVPECL Output to FPGA LVDS
Input Translator
The SN65LVDT100 and SN65LVDT101 include a
110-Ω differential line termination resistor for less
board space, fewer components, and the shortest
stub length possible. They do not include the VBB
voltage reference found in the SN65LVDS100 and
SN65LVDS101. VBB provides a voltage reference of
typically 1.35 V below VCC for use in receiving
single-ended input signals and is particularly useful
with single-ended 3.3-V PECL inputs. When not used,
VBB should be unconnected or open.
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
All devices are characterized for operation from
–40°C to 85°C.
FUNCTIONAL DIAGRAM
EYE PATTERN
SN65LVDS100 and SN65LVDS101
8
2
4
2 Gbps
- 1 PRBS
V
V
BB
CC
23
2
A
7
6
Y
V
= 3.3 V
CC
V
= 200 mV
ID
Z
V
IC
= 1.2 V
3
B
Vert.Scale= 200 mV/div
SN65LVDT100 and SN65LVDT101
1 GHz
2
A
7
Y
Z
110 Ω
6
3
B
Horizontal Scale= 200 ps/div
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRO-
Copyright © 2002–2004, Texas Instruments Incorporated
DUCTION DATA information current as of publication date. Prod-
ucts conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
OUTPUT
LVDS
TERMINATION RESISTOR
VBB
Yes
Yes
No
PART NUMBER(1)
PART MARKING
DL100
AZK
PACKAGE
SOIC
No
No
SN65LVDS100D
LVDS
SN65LVDS100DGK
SN65LVDT100D
MSOP
SOIC
LVDS
Yes
Yes
No
DE100
AZL
LVDS
No
SN65LVDT100DGK
SN65LVDS101D
MSOP
SOIC
LVPECL
LVPECL
LVPECL
LVPECL
Yes
Yes
No
DL101
AZM
No
SN65LVDS101DGK
SN65LVDT101D
MSOP
SOIC
Yes
Yes
DE101
BAF
No
SN65LVDT101DGK
MSOP
(1) Add the suffix R for taped and reeled carrier (i.e. SN65LVDS100DR).
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range unless otherwise noted
UNIT
VCC
IBB
VI
Supply voltage range(2)
VBB Output current
–0.5 V to 4 V
±0.5 mA
Voltage range, (A, B, Y, Z)
0 V to 4.3 V
VO
VID
Differential voltage, |VA– VB| ('LVDT100 and 'LVDT101 only)
1 V
±5 kV
A, B, Y, Z, and GND
Human Body Model(3)
ESD
All pins
All pins
±2 kV
Charged-Device Model(4)
±1500 V
PD
Continuous power dissipation
See Dissipation Rating Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.7.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
POWER DISSIPATION RATINGS
T
A ≤ 25°C
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
DGK
D
377 mW
3.8 mW/°C
4.8 mW/°C
151 mW
192 mW
481 mW
(1) This is the inverse of the junction-to-ambient thermal resistance with no air flow installed on the JESD51-3 low effective thermal
conductivity test board for leadless surface mount packages.
2
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
Supply voltage, VCC
3
0.1
3.3
3.6
1
V
V
V
'LVDS100 or 'LVDS101
'LVDT100 or 'LVDT101
Magnitude of differential input voltage |VID
|
0.1
0.8
4
Input voltage (any combination of common-mode or input signals), VI
VBB output current, IO(VBB)
0
–400(1)
12 µA
Operating free-air temperature, TA
–40
85 °C
(1) The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise specified)
(1)
PARAMETER
TEST CONDITIONS
No load or input
MIN
TYP
MAX UNIT
Supply current, 'LVDx100
Supply current, 'LVDx101
Device power dissipation, 'LVDx100
25
50
30
ICC
mA
61
RL = 50 Ω to 1 V, No input
RL = 100 Ω, No input
110
PD
mW
142
Y and Z to VCC - 2 V through 50 Ω,
No input
Device power dissipation, 'LVDx101
116
Reference voltage output, 'LVDS100 or
'LVDS101
VBB
IO = –400 µA or 12 µA
VCC–1.4 VCC–1.35 VCC–1.3
mV
SN65LVDS100 and SN65LVDS101 INPUT CHARACTERISTICS (see Figure 1)
Positive-going differential input voltage
threshold
VIT+
100
See Figure 1 and Table 1
mV
Negative-going differential input voltage
threshold
VIT-
–100
VI = 0 V or 2.4 V,
Second input at 1.2 V
–20
–20
20
33
20
µA
µA
II
Input current
VI = 4 V, Second input at 1.2 V
VCC = 1.5 V, VI = 0 V or 2.4 V,
Second input at 1.2 V
II(OFF)
Power off input current
µA
VCC= 1.5 V, VI = 4 V,
Second input at 1.2 V
33
6
IIO
Ci
Input offset current (|IIA - IIB|)
VIA = VIB, 0≤ VIA ≤ 4 V
–6
µA
pF
Small-signall input capacitance to GND
VI = 1.2 V
0.6
SN65LVDT100 and SN65LVDT101 INPUT CHARACTERISTICS (see Figure 1)
Positive-going differential input voltage
threshold
VIT+
100
See Figure 1 and Table 1
mV
µA
µA
Negative-going differential input voltage
threshold
VIT-
–100
–40
VI = 0 V or 2.4 V, Other input open
VI = 4 V, Other input open
40
66
II
Input current
VCC = 1.5 V, VI = 0 V or 2.4 V,
Other input open
–40
40
66
II(OFF)
Power off input current
VCC= 1.5 V, VI = 4 V, Other input
open
VID = 300 mV or 500 mV, VIC = 0 V
or 2.4 V
90
90
110
132
132
R(T)
Ci
Differential input resistance
Ω
VCC= 0 V, VID = 300 mV or 500 mV,
VIC = 0 V or 2.4 V
110
0.6
Small-signall differential input capacitance
VI = 1.2 V
pF
(1) Typical values are with a 3.3-V supply voltage and room temperature
3
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise specified)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SN65LVDS100 and SN65LVDT100 OUTPUT CHARACTERISTICS (see Figure 1)
|VOD
|
Differential output voltage magnitude
247
–50
340
454
See Figure 2
See Figure 3
mV
50
Change in differential output voltage magni-
tude between logic states
∆|VOD
|
VOC(SS)
Steady-state common-mode output voltage
1.125
–50
1.375
50
V
Change in steady-state common-mode output
voltage between logic states
∆VOC(SS)
mV
VOC(PP)
IOS
Peak-to-peak common-mode output voltage
Short-circuit output current
50
150
24
mV
mA
mA
VO(Y) or VO(Z) = 0 V
VOD = 0 V
–24
–12
IOS(D)
Differential short-circuit output current
12
SN65LVDS101 and SN65LVDT101 OUTPUT CHARACTERISTICS (see Figure 1)
50 Ω to VCC– 2 V, See Figure 4
VCC = 3.3 V, 50-Ω load to 2.3 V
50 Ω to VCC - 2 V, See Figure 4
VCC = 3.3 V, 50-Ω load to 2.3 V
50-Ω load to VCC– 2 V, SeeFigure 4
VCC–1.25 VCC–1.02 VCC–0.9
2055 2280 2405
VCC–1.83 VCC–1.61 VCC–1.53
V
VOH
High-level output voltage
mV
V
VOL
Low-level output voltage
1475
475
1690
575
1775
750
mV
mV
|VOD
|
Differential output voltage magnitude
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
'LVDx100
300
400
300
400
470
630
470
630
800
900
800
900
220
220
50
Propagation delay time,
low-to-high-level output
tPLH
ps
ps
'LVDx101
'LVDx100
Propagation delay time,
high-to-low-level output
tPHL
'LVDx100 See Figure 5
tr
tf
Differential output signal rise time (20%–80%)
ps
ps
ps
ps
ps
ps
Differential output signal fall time (20%–80%)
(2)
tsk(p) Pulse skew (|tPHL– tPLH|)
tsk(pp) Part-to-part skew(3)
tjit(per) RMS period jitter(4)
5
VID = 0.2 V, See Figure 5
100
3.7
23
1
6
1 GHz 50% duty cycle square wave input,
VID = 200 mV, VIC = 1.2 V, See Figure 6
tjit(cc) Peak cycle-to-cycle jitter(5)
2 GHz PRBS, 223–1 run length, VID = 200 mV,
VIC = 1.2 V, See Figure 6
2 GHz PRBS, 27–1 run length, VID = 200 mV,
VIC = 1.2 V, See Figure 6
tjit(pp) Peak-to-peak jitter
28
17
65
48
ps
ps
tjit(det) Peak-to-peak deterministic jitter(6)
(1) All typical values are at 25°C and with a 3.3 V supply.
(2) tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.
(3) tsk(pp) is the magnitude of the time difference in propagation delay time between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(4) Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 1000,000 cycles.
(5) Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles, over a random sample of 1,000 adjacent cycle
pairs.
(6) Deterministic jitter is the sum of pattern-dependent jitter and pulse-width distortion.
4
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION
I
IA
A
B
Y
Z
I
O
V
BB
V
ID
V
OD
V
IA
V
O(Y)
V
IC
+
V
+V
IA IB
V
OC
V
V
IB
V
O(Z)
BB
-
I
IB
2
Figure 1. Voltage and Current Definitions
Table 1. Receiver Input Voltage Threshold Test
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
APPLIED VOLTAGES
OUTPUT(1)
VIA
VIB
VID
VIC
1.25 V
1.15 V
4.0 V
3.9 V
0.1 V
0.0 V
1.7 V
0.7 V
4.0 V
3.0 V
1.0 V
0.0 V
1.15 V
1.25 V
3.9 V
4. 0 V
0.0 V
0.1 V
0.7 V
1.7 V
3.0 V
4.0 V
0.0 V
1.0 V
100 mV
1.2 V
1.2 V
3.95 V
3.95 V
0.05 V
0.05 V
1.2 V
1.2 V
3.5 V
3.5 V
0.5 V
0.5 V
H
L
–100 mV
100 mV
H
L
–100 mV
100 mV
H
L
–100 mV
1000 mV
–1000 mV
1000 mV
–1000 mV
1000 mV
–1000 mV
H
L
H
L
H
L
(1) H = high level, L = low level
3.74 kΩ
Y
+
0 V ≤ V
≤ 2.4 V
V
OD
100 Ω
(test)
_
Z
3.74 kΩ
Figure 2. SN65LVDx100 Differential Output Voltage (VOD) Test Circuit
A
1.4 V
1.0 V
49.9 Ω ±1%
A
B
Y
B
V
ID
V
V
OC(SS)
OC(PP)
V
OC
Z
1 pF
V
49.9 Ω ±1%
OC
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the SN65LVDx100 Driver Common-Mode Output Voltage
5
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
V
OY
+
OD
-
50 Ω
50 Ω
V
V
OZ
+
-
V
CC
- 2V
Figure 4. Typical Termination for LVPECL Output Driver (65LVDx101)
V
1.4 V
1 V
A
B
IA
Y
V
OD
1 pF
100 Ω
V
ID
V
IB
ID
V
IA
Z
V
IB
0.4 V
0 V
V
-0.4 V
50 Ω
50 Ω
t
t
PLH
PHL
V
OD
100%
0 V
OR
80%
V
OD
20%
0%
+
-
V
CC
- 2V
t
f
t
r
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. Measurement equipment provides a bandwidth of 5 GHz minimum.
Figure 5. Timing Test Circuit and Waveforms
IDEAL OUTPUT
CLOCK INPUT
0 V
0 V
1/fo
1/fo
Period Jitter
Cycle to Cycle Jitter
ACTUAL OUTPUT
0 V
ACTUAL OUTPUT
0 V
t
t
t
c(n)
c(n+1)
c(n)
t
= |t
- t
|
t
= |t
- 1/fo|
jit(cc)
c(n) c(n+1)
jit(per)
c(n)
PRBS INPUT
0 V
PRBS OUTPUT
0 V
t
jit(pp)
Figure 6. Driver Jitter Measurement Waveforms
6
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
Power Supply 1
+
3.3V
-
+
Power Supply 2
1.22V
-
J3
DUT
J2
EVM
GND
J1
VCC
GND
J4
J5
J6
J7
100 W
50 W
50 W
Agilent
E4862B
DUT
Matched
Cables
Matched
Cables
Pattern
Generator
(Note A)
SMA to SMA
SMA to SMA
Tektronix
TDS6604
EVM
Oscilloscope
(Note B)
A. Source jitter is subtracted from the measured values.
B. TDS JIT3 jitter analysis software installed
Figure 7. Jitter Setup Connections for SN65LVDS100 and SN65LVDS101
PIN ASSIGNMENTS
SN65LVDS100 and SN65LVDS101
D AND DGK PACKAGE
(TOP VIEW)
SN65LVDT100 and SN65LVDT101
D AND DGK PACKAGE
(TOP VIEW)
NC
A
VCC
Y
NC
A
VCC
Y
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
B
Z
B
Z
VBB
GND
NC
GND
NC = Not Connected
FUNCTION TABLE
DIFFERENTIAL INPUT
OUTPUTS(1)
VID= VA– VB
Y
H
?
Z
V
ID ≥ 100 mV
L
?
–100 mV < VID < 100 mV
V
ID ≤ – 100 mV
L
H
?
Open
?
(1) H = high level, L = low level, ? = indeterminate
7
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
INPUT
V
CC
V
CC
B
A
110 W
(SN65LVDT only)
V
CC
V
CC
215 m A
215 m A
7 V
7 V
350 m A
350 m A
OUTPUT
(SN65LVDS100 and SN65LVDT100)
OUTPUT
(SN65LVDS101 and SN65LVDT101)
V
CC
V
CC
R
R
Y
R
R
V
CC
Y
Z
7 V
Z
7 V
7 V
7 V
8
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREQUENCY
FREQUENCY
55
60
700
LVDS101= Loaded
LVDS101 = Loaded
LVDS101
600
50
V
= 3.3 V
CC
= 25°C
45
35
T
A
V
V
= 1.2 V
= 200 mV
V
V
= 3.3 V
IC
CC
= 1.2 V
500
40
30
IC
ID
V
= 200 mV
ID
f = 750 MHz
LVDS100
400
LVDS100
LVDS100
V
= 3.3 V
CC
= 25°C
25
15
T
A
20
10
300
200
V
V
= 1.2 V
= 200 mV
IC
ID
0
200
400
600
800 1000 1200
-40
-20
0
20
40
60
80 100
0
200
400
600
800
1000 1200
Frequency - MHz
f - Frequency - MHz
T
A
- Free-Air Temperature - °C
Figure 8.
Figure 9.
Figure 10.
SN65LVDS100
SN65LVDS101
SN65LVDS100
PROPAGATION DELAY TIME
vs
PROPAGATION DELAY TIME
vs
PROPAGATION DELAY TIME
vs
COMMON-MODE INPUT VOLTAGE
COMMON-MODE INPUT VOLTAGE
FREE-AIR TEMPERATURE
600
550
500
450
400
550
750
700
650
600
550
500
450
V = 3.3 V
CC
V
T
= 3.3 V
V
T
= 3.3 V
CC
= 25°C
CC
= 25°C
V
= 200 mV
ID
A
A
f = 150 MHz
V
= 200 mV
V
= 200 mV
ID
f = 150 MHz
ID
f = 150 MHz
t
PHL
t
PLH
500
450
400
350
t
PHL
t
PLH
t
PLH
t
PHL
350
300
-40 -20
0
20
40
60
80
100
0
1
2
3
4
5
0
1
2
3
4
5
V
- Common-Mode Input Voltage - V
T
A
- Free-Air Temperature - °C
IC
V
- Common-Mode Input Voltage - V
IC
Figure 11.
Figure 12.
Figure 13.
SN65LVDS101
SN65LVDS100
SN65LVDS100
PROPAGATION DELAY TIME
vs
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
vs
vs
FREE-AIR TEMPERATURE
FREQUENCY
DATA RATE
30
25
20
15
10
60
50
40
30
20
750
V
V
= 3.3 V
= 200 mV
V
T
V
= 3.3 V
= 25°C
= 400 mV
CC
V
= 3.3 V
CC
= 25°C
OC
ID
T
V
A
A
700
650
600
550
f = 150 MHz
= 400 mV
IC
IC
23
2 -1
Input = PRBS
Input = Clock
t
PLH
t
PHL
V
= 0.3 V
V
= 0.3 V
ID
V
ID
V
= 0.5 V
ID
V
= 0.8 V
ID
10
0
500
450
5
0
V
= 0.8 V
ID
= 0.5 V
ID
-40
-20
0
20
40
60
80
100
300
800
1300
1800
2300
200
400
600
800
1000
T
A
- Free-Air Temperature - °C
Data Rate - Mbps
f - Frequency - MHz
Figure 14.
Figure 15.
Figure 16.
9
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
SN65LVDS101
PEAK-TO-PEAK JITTER
vs
SN65LVDS101
PEAK-TO-PEAK JITTER
vs
SN65LVDS100
PEAK-TO-PEAK JITTER
vs
FREQUENCY
DATA RATE
FREQUENCY
60
50
40
30
20
10
0
30
25
20
30
25
20
15
10
V
= 3.3 V
V
T
V
= 3.3 V
CC
= 25°C
V
T
V
= 3.3 V
= 25°C
= 400 mV
CC
= 25°C
CC
T
A
A
A
V
= 1.2 V
= 400 mV
IC
Input = Clock
IC
Input = Clock
IC
23
2 -1
Input = PRBS
= 0.8 V
V
= 0.5 V
ID
V
ID
15
10
V
= 0.8 V
V
= 0.8 V
ID
ID
V
= 0.5 V
ID
V
= 0.3 V
ID
V
= 0.3 V
ID
5
0
5
0
V
= 0.3 V
1800
ID
V
= 0.5 V
800
ID
200
400
600
1000
2300
1000
300
800
1300
2300
1000
2300
200
400
600
800
1000
f - Frequency - MHz
Data Rate - Mbps
f - Frequency - MHz
Figure 17.
Figure 18.
Figure 19.
SN65LVDS100
PEAK-TO-PEAK JITTER
SN65LVDS101
PEAK-TO-PEAK JITTER
SN65LVDS101
PEAK-TO-PEAK JITTER
vs
vs
vs
DATA RATE
FREQUENCY
DATA RATE
30
25
20
15
10
60
50
40
30
20
10
0
60
50
40
30
20
V
T
= 3.3 V
= 25°C
= 1.2 V
V
T
= 3.3 V
= 25°C
= 1.2 V
V
T
= 3.3 V
CC
CC
CC
= 25°C
A
A
A
V
V
IC
V
IC
= 1.2 V
IC
23
2 -1
23
2 -1
Input = PRBS
Input = PRBS
Input = Clock
V
= 0.3 V
V
= 0.8 V
ID
ID
V
= 0.8 V
= 0.5 V
ID
V
= 0.5 V
ID
V
ID
V
= 0.8 V
ID
V
= 0.3 V
ID
V
= 0.5 V
ID
10
0
5
0
V
= 0.3 V
ID
200
400
600
800
300
800
1300
1800
300
800
1300
1800
2300
Data Rate - Mbps
f - Frequency - MHz
Data Rate - Mbps
Figure 20.
Figure 21.
Figure 22.
SN65LVDS100
PEAK-TO-PEAK JITTER
vs
SN65LVDS100
PEAK-TO-PEAK JITTER
SN65LVDS101
PEAK-TO-PEAK JITTER
vs
vs
FREQUENCY
DATA RATE
FREQUENCY
60
30
30
25
V
T
V
= 3.3 V
CC
= 25°C
= 2.9 V
V
T
V
= 3.3 V
CC
= 25°C
= 2.9 V
V
T
= 3.3 V
CC
= 25°C
A
A
50
40
30
20
A
25
20
IC
Input = Clock
IC
Input = PRBS
V
= 2.9 V
IC
Input = Clock
23
V
2
-1
20
15
10
= 0.3 V
ID
15
10
V
= 0.8 V
ID
V
= 0.8 V
ID
V
= 0.5 V
ID
V
= 0.5 V
ID
V
= 0.8 V
ID
10
0
5
0
5
0
V
= 0.5 V
1300
ID
V
= 0.3 V
V
= 0.3 V
800
ID
ID
200
400
600
1000
300
800
1800
200
400
600
800
f - Frequency - MHz
f - Frequency - MHz
Data Rate - Mbps
Figure 23.
Figure 24.
Figure 25.
10
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
SN65LVDS101
PEAK-TO-PEAK JITTER
vs
SN65LVDS100
PEAK-TO-PEAK JITTER
vs
SN65LVDS100
DIFFERENTIAL OUTPUT VOLTAGE
vs
DATA RATE
FREE-AIR TEMPERATURE
FREQUENCY
400
350
300
250
60
50
40
50
40
30
20
80
70
60
50
V
V
V
= 3.3 V
CC
= 1.2 V
IC
= 200 mV
ID
Input = 2 Gbps 2 -1
V
= 0.3 V
ID
23
V
= 0.5 V
LVDS100
LVDS101
ID
V
V
= 3.3 V,
CC
= 1.2 V,
IC
200
150
100
50
30
40
30
20
10
|V | = 200 mV,
ID
T
= 25°C,
A
Input = Clock
20
10
0
V
= 0.8 V
ID
V
T
A
= 3.3 V
CC
= 25°C
10
0
V
= 2.9 V
IC
Added Random Jitter
500 1000 1500
23
2
Input = PRBS
-1
0
0
2500
1300
1800
2300
0
2000
300
800
-40
-20
0
20
40
60
80
100
T
A
- Free-Air Temperature - °C
Data Rate - Mbps
f - Frequency - MHz
Figure 26.
Figure 27.
Figure 28.
SN65LVDS100
PEAK-TO-PEAK JITTER
vs
SN65LVDS101
SN65LVDS101
PEAK-TO-PEAK JITTER
vs
DIFFERENTIAL OUTPUT VOLTAGE
vs
DATA RATE
FREQUENCY
DATA RATE
100
80
700
620
540
460
100
80
50
V
V
= 3.3 V,
CC
= 1.2 V,
V
V
= 3.3 V,
V
V
= 3.3 V,
CC
= 1.2 V,
CC
= 1.2 V,
IC
IC
IC
|V | = 200 mV,
ID
|V | = 200 mV,
|V | = 200 mV,
ID
ID
40
30
20
10
T
= 25°C,
A
T
= 25°C,
T = 25°C,
A
A
Input = Clock
23
Input = PRBS 2 -1
23
Input = PRBS 2 -1
60
40
60
40
20
0
380
300
20
0
Added Random Jitter
0
2000
0
400
800
1200
1600
0
1000
2000
3000
4000
0
1000
2000
3000
4000
5000
f - Frequency - MHz
Data Rate - Mbps
Data Rate - Mbps
Figure 29.
Figure 30.
Figure 31.
11
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
SN65LVDS100
SN65LVDS100
622 Mbps, 223– 1 PRBS
2 Gbps, 223– 1 PRBS
Horizontal Scale= 200 ps/div
LVPECL-to-LVDS
Horizontal Scale= 100 ps/div
LVPECL-to-LVDS
Figure 32.
Figure 33.
SN65LVDS101
SN65LVDS101
622 Mbps, 223– 1 PRBS
2 Gbps, 223– 1 PRBS
Horizontal Scale= 100 ps/div
LVDS-to-LVPECL
Horizontal Scale= 200 ps/div
LVDS-to-LVPECL
Figure 34.
Figure 35.
12
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
20
3.6 V, 85°C
3 V, 85°C
15
3.6 V, -40°C
V
IT+
10
5
3 V, -40°C
0
|V | = 250 mV,
OD
R
= 100 Ω,
L
3 V, -40°C
Nominal Process
-5
-10
V
IT-
3.6 V, -40°C
-15
3 V, 85°C
3.6 V, 85°C
-20
0
1
2
3
4
5
Common-Mode Input Voltage - V
NOTE: VIT is a steady-state parameter. The switching time is influenced by the input overdrive above this steady-state
threshold up to a differential input voltage magnitude of 100 mV.
Figure 36. SN65LVDS100 Simulated Input Voltage Threshold vs
Common-Mode Input Voltage, Supply Voltage, and Temperature
13
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
APPLICATION INFORMATION
The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 inputs will detect a 100-mV difference
between any two signals between 0 V and 4 V, This range will allow receipt of many different single-ended and
differential signals. Following are some of the more common connections.
V
CC
SN65LVDS100
ECL
100 W
50 W
50 W
V
EE
V -2 V
CC
Figure 37. PECL-to-LVDS Translation
LVDS
SN65LVDT101
3.3 v
PECL
LVDS
50 W
50 W
Figure 38. LVDS-to-3.3 V PECL Translation
5 V
ECL
SN65LVDS101
3.3 v
PECL
50 W
50 W
50 W
50 W
V
EE
3 V
Figure 39. 5-V PECL to 3.3-V PECL Translation
V
TT
50 W
50 W
SN65LVDS100 or
SN65LVDS101
CML
Figure 40. CML-to-LVDS or 3.3-V PECL Translation
14
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
APPLICATION INFORMATION (continued)
3.3 V
ECL
SN65LVDS100
Z = 50 W
0
100 W
LVDS
50 W
V
EE
V
BB
0.01 mF
22 kW
Figure 41. Single-Ended 3.3-V PECL-to-LVDS Translation
V
DD
V /600 mA*
DD
1 V < V < 4 V
DD
CMOS
SN65LVDS100
100 W
LVDS
0.01 mF
V /600 mA*
DD
* closest standard value
Figure 42. Single-Ended CMOS-to-LVDS Translation
V
DD
1 V < V < 4 V
DD
V /600 mA*
DD
CMOS
SN65LVDS101
3.3 v
PECL
50 W
50 W
0.01 mF
V /600 mA*
DD
* closest standard
value
Figure 43. Single-Ended CMOS-to-3.3-V PECL Translation
C
SN65LVDS100 or
SN65LVDS101
50 W
50 W
C
V
BB
0.01 mF
22 kW
Figure 44. Receipt of AC-Coupled Signals
15
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
APPLICATION INFORMATION (continued)
FAILSAFE CONSIDERATIONS
Failsafe, in regard to a line receiver, usually means that the output goes to a defined logical state with no input
signal. To keep added jitter to an absolute minimum, the SN65LVDS100 does not include this feature. It does
exhibit 25 mV of input voltage hysteresis to prevent oscillation and keep the output in the last state prior to
input-signal loss (assuming the differential noise in the system is less than the hysteresis).
Should failsafe be required, it may be added externally with a 1.6-kΩ pull-up resistor to the 3.3-V supply and a
1.6-kΩ pull-down resistor to ground as shown in Figure 45 The default output state is determined by which line is
pulled up or down and is the user's choice. The location of the 1.6-kΩ resistors is not critical. However the 100-Ω
resistor should be located at the end of the transmission line.
3.3 V
1.6 kΩ
100 Ω
1.6 kΩ
Figure 45. External Failsafe Circuit
Addition of this external failsafe will reduce the differential noise margin and add jitter to the output signal. The
roughly 100-mV steady-state voltage generated across the 100-Ω resistor adds (or subtracts) from the signal
generated by the upstream line driver. If the line driver's differential output is symmetrical about zero volts, then
the input at the receiver will appear asymmetrical with the external failsafe. Perhaps more important, is the extra
time it takes for the input signal to overcome the added failsafe offset voltage.
In Figure 46 and using an external failsafe, the high-level differential voltage at the input of the SN65LVDS100
reaches 340 mV and the low-level –400 mV indicating a 60-mV differential offset induced by the external failsafe
circuitry. The figure also reveals that the lowest peak-to-peak time jitter does not occur at zero-volt differential
(the nominal input threshold of the receiver) but at –60 mV, the failsafe offset.
The added jitter from external failsafe increases as the signal transition times are slowed by cable effects. When
a ten-meter CAT-5 UTP cable is introduced between the driver and receiver, the zero-crossing peak-to-peak jitter
at the receiver output adds 250 ps when the external failsafe is added with this specific test set up. If external
failsafe is used in conjunction with the SN65LVDS100, the noise margin and jitter effects should be budgeted.
16
SN65LVDS100, SN65LVDT100
SN65LVDS101, SN65LVDT101
www.ti.com
SLLS516C–AUGUST 2002–REVISED JUNE 2004
Figure 46. Receiver Input Eye Pattern With External Failsafe
17
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