SN65LVDT348PWR [TI]
暂无描述;
| 型号： | SN65LVDT348PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 暂无描述 |
| 文件： | 总20页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
QUAD HIGH-SPEED DIFFERENTIAL RECEIVERS
FEATURES
APPLICATIONS
D
D
D
Meets or Exceeds the Requirements of ANSI
TIA/EIA-644A Standard
D
Logic Level Translator
D
Point-to-Point Baseband Data Transmission
Over 100-Ω Media
1
Single-Channel Signaling Rates up to
560 Mbps
D
D
D
ECL/PECL-to-LVTTL Conversion
Wireless Base Stations
–4 V to 5 V Common-Mode Input Voltage
Range
Central Office or PABX Switches
D
Flow-Through Architecture
DESCRIPTION
D
Active Failsafe Assures a High-level Output
When an Input Signal Is not Present
The SN65LVDS348, SN65LVDT348, SN65LVDS352,
and SN65LVDT352 are high-speed, quadruple
differential receivers with a wide common-mode input
voltage range. This allows receipt of TIA/EIA-644
signals with up to 3-V of ground noise or a variety of
differential and single-ended logic levels. The ‘348 is in
a 16-pin package to match the industry-standard
footprint of the DS90LV048. The ‘352 adds two
D
SN65LVDS348 Provides a Wide
Common-Mode Range Replacement for the
SN65LVDS048A or the DS90LV048A
DATA TRANSFER RATE
vs
FREE-AIR TEMPERATURE
additional V
and GND pins in a 24-pin package to
CC
550
provide higher data transfer rates with multiple
receivers in operation. All offer a flow-through
architecture with all inputs on one side and outputs on
the other to ease board layout and reduce crosstalk
between receivers. LVDT versions of both integrate a
110-Ω line termination resistor.
SN65LVDS352PW
500
450
400
350
300
250
200
SN65LVDS348PW
Timer
LVDT Device
Only
15
2
–1 prbs NRZ, V = 0.4 V
ID
V
= 1.2 V, C = 5.5 pF, 40% Open Eye
IC
4 Receivers Switching, Input Jitter < 45 ps
L
–60 –40 –20
0
20
40
60
80
100
T
A
– Free-Air Temperature – °C
(One of Four Shown)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002 – 2003 Texas Instruments Incorporated
1
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
description (continued)
These receivers also provide 3x the standard’s minimum common-mode noise voltage tolerance. The –4 V to
5 V common-mode range allows usage in harsh operating environments or accepts LVPECL, PECL, LVECL,
ECL, CMOS, and LVCMOS levels without level shifting circuitry. See the Application Information Section for
more details on the ECL/PECL to LVDS interface.
Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input-voltage
hysteresis to improve noise rejection. The differential input thresholds are still no more than ±50 mV over the
full input common-mode voltage range.
The receiver inputs can withstand ±15 kV human-body model (HBM), with respect to ground, without damage.
This provides reliability in cabled and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent-pending) failsafe circuit that provides a high-level output approximately
600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted
lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault
conditions. This feature may also be used for Wired-Or bus signaling.
The SN65LVDT348 and SN65LVDT352 include an integrated termination resistor. This reduces board space
requirements and parts count by eliminating the need for a separate termination resistor. This can also improve
signal integrity at the receiver by reducing the stub length from the line termination to the receiver.
The intended application of these devices and signaling technique is for point-to-point baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media may be
printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent
upon the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS348, SN65LVDT348, SN65LVDS352 and SN65LVDT352 are characterized for operation from
–40°C to 85°C.
SN65LVDS348, SN65LVDT348
D or PW PACKAGE
(TOP VIEW)
SN65LVDS352, SN65LVDT352
PW PACKAGE
(TOP VIEW)
1
24
23
22
21
20
19
18
17
16
15
14
13
1A
1B
2A
NC
1Y
DGND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R
R
R
R
R
R
R
R
EN
IN1–
IN1+
IN2+
IN2–
IN3–
IN3+
IN4+
IN4–
2
R
R
V
OUT1
OUT2
CC
3
4
2B
V
CCD1
5
EN 1,2
2Y
NC
NC
3Y
GND
6
V
CCA
R
R
OUT3
OUT4
7
AGND
EN 3,4
3A
8
EN
9
V
CCD2
10
11
12
3B
4A
4B
DGND2
4Y
NC
NC – No internal connection
2
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
functional block diagrams (one of four receivers shown)
To Three Other Receivers
To One Other Receiver
352 Devices
348 Devices
EN
EN
EN
R
R
A
IN+
R
Y
OUT1
B
IN–
Timer
Timer
SN65LVDT348
Only
SN65LVDT352
Only
Window Comparator
PART NUMBER
Window Comparator
AVAILABLE OPTIONS
INTEGRATED
TERMINATION
PACKAGE
TYPE
PACKAGE
MARKING
†
SN65LVDS348D
SN65LVDT348D
SN65LVDS348PW
SN65LVDT348PW
SN65LVDS352PW
SN65LVDT352PW
SOIC
LVDS348
LVDT348
DL348
n
n
n
SOIC
TSSOP
TSSOP
TSSOP
TSSOP
DE348
DL352
DE352
†
Add the R suffix to the device type (e.g., SN65LVDS348DR) for taped and reeled carrier.
Function Tables
348 DEVICES
INPUTS
OUTPUTS
V
= V
– V
EN
H
EN
L or OPEN
L or OPEN
L or OPEN
L or OPEN
X
R
OUT
ID
RIN+
RIN–
V
≥ –32 mV
H
ID
–100 mV < V < –32 mV
H
?
L
ID
V
ID
≤ –100 mV
H
Open
H
H
Z
Z
L or OPEN
X
X
H
352 DEVICES
INPUTS
OUTPUTS
V
= V – V
IB
EN
Y
H
?
ID
IA
≥ –32 mV
V
H
ID
–100 mV < V < –32 mV
H
ID
V
ID
≤ –100 mV
X
H
L or OPEN
H
L
Z
H
Open
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
3
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
equivalent input and output schematic diagrams
V
CC
V
CC
6.5 kΩ
Attenuation
6.5 kΩ
1 pF
60 kΩ
Attenuation
Network
R
, A
IN+
R
, B
IN–
Network
200 kΩ
7 V
7 V
250 kΩ
7 V
7 V
3 pF
110 Ω
’LVDT Only
Attenuation
Network
V
CC
V
CC
100 Ω
37 Ω
EN, EN
R
Y
OUT,
7 V
300 kΩ
7 V
4
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range (see Note 1), V , V
, V
,
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
CC CCA CCD1 and CCD2
Voltage range: Enables, R
, or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
OUT
Differential input magnitude V
(LVDT only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V
ID
R
, R , A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to 6 V
IN+ IN–
Electrostatic discharge: Human body model (see Note 2): A, B, R , R
and GND . . . . . . . . . . . . . . . . ±15 kV
IN+
IN–
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 kV
Charged-device model (see Note 3): All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal (GND, AGND).
2. Tested in accordance with JEDEC Standard 22, Test Method A114-A.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
DISSIPATION RATING TABLE
‡
T
≤ 25°C
OPERATING FACTOR
T = 85°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
D16
950 mW
7.6 mW/°C
6.2 mW/°C
8.7 mW/°C
494 mW
PW16
PW24
774 mW
402 mW
1087 mW
565 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
recommended operating conditions
MIN NOM
MAX
3.6
5
UNIT
Supply voltage, V , V
, V
and V
3
2
3.3
V
V
V
CC CCA CCD1,
CCD2
High-level input voltage, V
IH
Enables
Enables
Low-level input voltage, V
0
0.8
0.8
3
IL
V
V
(LVDT348, 352)
(LVDS348, 352)
0.1
0.1
–4
–40
ID
Magnitude of differential input voltage
V
ID
Input voltage (any combination of common mode or input signals)
Operating free-air temperature, T
5
V
85
°C
A
5
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
electrical characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
Positive-going differential input voltage
threshold
V
50
ITH1
See Figure 1 and Figure 2
mV
Negative-going differential input voltage
threshold
V
V
V
–50
–32
ITH2
Differential input failsafe voltage threshold
Differential input voltage hysteresis,
See Figure 1 and Table 1
–100
mV
mV
ITH3
50
ID(HYS)
V
ITH1
– V
ITH2
V
V
High-level output voltage
Low-level output voltage
I
I
= –4 mA
2.4
V
V
OH
OH
= 4 mA
0.4
20
4
OL
OL
Enabled, EN at V
,
EN at 0 V, No load
16
1.1
16
LVDS348,
LVDT348
CC
mA
mA
Disabled, EN at 0 or EN at V
CC
I
Supply current
CC
Enabled, EN at V
CC
,
No load
20
4
LVDS352,
LVDT352
Disabled, EN at 0
1.1
V = –4 V,
Other input open
Other input 1.2 V
Other input open
Other input open
Other input open
Other input open
–75
–20
0
0
I
LVDS348,
LVDS352
0 V ≤ V ≤ 2.4 V,
0
µA
µA
I
V = 5 V,
I
40
0
Input current (RIN+, RIN–,
A or B inputs)
I
I
V = –4 V,
I
–150
–40
0
LVDT348,
LVDT352
0 V ≤ V ≤ 2.4 V,
0
I
V = 5 V,
I
80
V
= 1.5 V,
V = –4 V or 5 V,
I
CC
Other input open
–50
–20
–100
–40
–4
50
20
LVDS348,
LVDS352
µA
µA
V
= 1.5 V,
0 V ≤ V ≤ 2.4 V,
I
CC
Other input at 1.2 V
Power–off input current (RIN+,
RIN–, A or B inputs)
I
I
I(OFF)
V
= 1.5 V,
V = –4 V or 5 V,
I
CC
Other input open
100
40
LVDT348,
LVDT352
V
= 1.5 V,
V = 0 V or 2.4 V,
I
CC
Other input open
Differential input current
LVDS348,
LVDS352
V
V
= 100 mV,
V
V
= –3.9 V or 4.9 V
4
µA
ID
ID
IC
(I
– I
, or I – I )
IA IB
RIN+ RIN–
LVDT348,
= 0 V,
= 250 mV,
CC
ID
R
T
Differential input resistance
90
111
132
Ω
LVDT352 V = 0 V to 2.4 V
I
I
I
I
High-level input current
Enables
Enables
V
IH
V
IL
V
O
= 2 V
= 0.8 V
= 0 V
0
0
10
10
10
µA
µA
µA
IH
Low-level input current
IL
High-impedance output current
–10
OZ
Input capacitance, R
or A or B input to AGND
, R
input to GND
IN+ IN–
C
V = 0.4 sin (4E6πft) + 0.5 V
I
5
pF
IN
†
All typical values are at 25°C and with a 3.3-V supply.
6
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
switching characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Delay time, failsafe disable time
TEST CONDITIONS
MIN TYP
MAX
6
UNIT
ns
ns
ns
µs
ps
ps
ns
ns
ns
ps
ps
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
2.5
2.5
4
4
PLH
PHL
d1
6
9
Delay time, failsafe enable time
0.3
1.5
d2
C
= 10 pF,
L
Pulse skew (|t
– t
|)
200
150
sk(p)
sk(o)
sk(pp)
r
pHL1 pLH1
See Figure 3
‡
Output skew
§
Part-to-part skew
1
Output signal rise time
Output signal fall time
Output signal rise time
Output signal fall time
1.2
1
f
650
400
5
r
C = 1 pF,
L
See Figure 3
f
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
9
9
PHZ
PLZ
PZH
PZL
5
See Figure 4 and
Figure 5
8
12
12
8
†
‡
§
All typical values are at 25°C and with a 3.3-V supply.
t
t
isthemagnitudeofthetimedifferencebetweenthet ofallreceiversofasingledevicewithalloftheirinputsconnectedtogether.
or t
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
sk(o)
PHL PLH
sk(pp)
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
PARAMETER MEASUREMENT INFORMATION
I
IA
or I
RIN+
A or R
IN+
Y or R
OUT
V
ID
I
or I
ROUT
OY
B or R
IN–
V
IA
or V
RIN+
I
or I
RIN–
(V + V )/2 or
IB
IA
IB
+ V
V
IC
V
OY
or V
ROUT
(V
RIN+
V
or V
RIN–
RIN–)/2
IB
Figure 1. Voltage and Current Definitions
7
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
PARAMETER MEASUREMENT INFORMATION
1000 Ω
†
100 Ω
100 Ω
V
ID
1000 Ω
+
+
V
1
V
2
V
O
–
–
10 pF
10 pF
10 pF
+
–
V
IC
†
Remove for testing LVDT device.
NOTES: A. Input signal of 3 MHz, duty cycle of 50±0.2%, and transition time of < 1ns.
B. Fixture capacitance ±20%.
C. Resistors are metal film, 1% tolerance, and surface mount
V
ITH1
0 V
V
ID
–100 mV
V
O
100 mV
0 V
V
ID
V
ITH2
V
O
Figure 2. V
and V
, Input Voltage Threshold Test Circuit and Definitions
ITH2
ITH1
Table 1. Receiver Minimum and Maximum Failsafe Input Voltage
FAILSAFE THRESHOLD TEST VOLTAGES
†
APPLIED VOLTAGES
(mV) (mV)
RESULTANT INPUTS
(mV) (mV)
Output
V
IA
V
IB
V
V
IC
ID
–100
–4000
–4000
4900
–3900
–3968
5000
–3950
–3984
4950
L
H
L
–32
–100
–32
4968
5000
4984
H
†
Voltage applied for greater than 1.5 µs.
8
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
PARAMETER MEASUREMENT INFORMATION
A or R
IN+
Y or R
OUT
V
ID
V
IA
or V
RIN+
V
OY
or V
B or R
ROUT
IN–
C
L
V
IB
or V
RIN–
A or V
B or V
1.4 V
1 V
RIN+
RIN–
>1.5 µs
0.4 V
0 V
V
ID
–0.2 V
–0.4 V
t
t
t
d1
PHL
PLH
t
d2
V
OH
/2
V
OY
or V
ROUT
V
CC
V
OL
t
t
r
f
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, signaling rate = 250 kHz,
r
f
duty cycle = 50 ±2%, C includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T and is ±20%.
L
Figure 3. Timing Test Circuit and Waveforms
9
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
PARAMETER MEASUREMENT INFORMATION
R
R
IN–
R
OUT
500 Ω
1.2 V
IN+
+
EN
EN
V
TEST
V
_
ROUT
10 pF
Inputs
2.5 V
V
TEST
V
RIN+
1 V
2 V
1.4 V
EN
0.8 V
2 V
1.4 V
0.8 V
EN
t
t
PLZ
PZL
t
t
PLZ
PZL
2.5 V
1.4 V
VOL +0.5 V
VOL
V
ROUT
V
TEST
0 V
1.4 V
V
RIN+
2 V
1.4 V
EN
0.8 V
2 V
1.4 V
EN
0.8 V
t
t
PHZ
PZH
t
t
PHZ
PZH
VOH
VOH –0.5 V
1.4 V
0 V
V
ROUT
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, signaling rate = 500 kHz,
r
f
duty cycle = 50 ±2%, C includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T and is ±20%.
L
Figure 4. 348 Enable/Disable Time Test Circuit and Waveforms
10
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
PARAMETER MEASUREMENT INFORMATION
B
A
Y
500 Ω
1.2 V
Inputs
+
EN
V
TEST
V
O
_
10 pF
2.5 V
V
TEST
A
1 V
2 V
EN
1.4 V
0.8 V
t
t
PLZ
PZL
2.5 V
1.4 V
V
O
VOL +0.5 V
VOL
V
TEST
A
0 V
1.4 V
2 V
EN
1.4 V
0.8 V
t
t
PHZ
PZH
VOH
VOH –0.5 V
V
O
1.4 V
0 V
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, signaling rate = 500 kHz,
r
f
duty cycle = 50 ±2 %, C includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T and is ±20%.
L
Figure 5. 352 Enable/Disable Time Test Circuit and Waveforms
11
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
TYPICAL CHARACTERISTICS
HIGH-TO-LOW PROPAGATION DELAY
LOW-TO-HIGH PROPAGATION DELAY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5
4.5
4
5
See Figure 3
See Figure 3
V
CC
= 3 V
4.5
V
CC
= 3 V
V
CC
= 3.3 V
V
CC
= 3.3 V
4
3.5
3
V
CC
= 3.6 V
V
CC
= 3.6 V
3.5
3
–50
0
50
100
–50
0
50
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 6
Figure 7
LOW-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
40
30
0
T
V
= 25°C,
T
V
= 25°C,
A
A
= 3.3 V
= 3.3 V
CC
CC
–10
20
10
0
–20
–30
–40
0
1
2
3
4
5
0
1
2
3
4
V
OL
– Low-Level Output Voltage – V
V
OH
– High-Level Output Voltage – V
Figure 8
Figure 9
12
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
TYPICAL CHARACTERISTICS
DATA TRANSFER RATE
vs
FREE-AIR TEMPERATURE
RMS SUPPLY CURRENT
vs
SWITCHING FREQUENCY
500
450
400
350
300
110
90
15
4 Receivers Switching,
50% Duty Cycle,
2
–1 prbs NRZ,
= 1.2 V,
V
C
IC
L
V
= 3.6 V
CC
C
T
= 5.5 pF,
= 25°C
= 5.5 pF,
L
A
40% Open Eye,
4 Receivers Switching,
V
= 3.3 V,
CC
SN65LVDS348PW
V
CC
= 3.3 V
70
V
= 0.4 V
ID
V
= 3 V
CC
50
30
V
= 0.2 V
ID
V
ID
= 0.1 V
250
200
10
–60 –40 –20
0
20
40
60
80
100
0
50
100
150
200
250
300
T
A
– Free-Air Temperature – °C
f – Switching Frequency – MHz
Figure 11
Figure 10
23
23
2
–1 prbs NRZ, T = 25°C, C = 5.5 pF,
2
–1 prbs NRZ, T = 25°C, C = 5.5 pF,
A
L
A
L
4 Receivers Switching, V
CC
= 3.3 V
4 Receivers Switching, V
CC
= 3.3 V
Figure 13. SN65LVDS352 Eye
Pattern Running at 200 Mxfr/s
Figure 12. SN65LVDS348 Eye
Pattern Running at 200 Mxfr/s
13
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
APPLICATION INFORMATION
impedance matching and reflections
A termination mismatch can result in reflections that degrade the signal at the load. A low source impedance
causes the signal to alternate polarity at the load (oscillates) as shown in Figure 14. High source impedance
results in the signal accumulating monotonically to the final value (stair step) as shown in Figure 15. Both of
these modes result in a delay in valid signal and reduce the opening in the eye pattern. A 10% termination
mismatch results in a 5% reflection (ρ = Z – Z /Z + Z ), even a 1:3 mismatch absorbs half of the incoming
L
O
L
O
signal. This shows that termination is important in the more critical cases, however, in a general sense, a rather
large termination mismatch is not as critical when the differential output signal is much greater than the receiver
sensitivity.
TIME DOMAIN RESPONSE
TIME DOMAIN RESPONSE
0.25
0.2
0.25
0.2
Z
S
Z
O
Z
T
= 0 Ω
= 100 Ω
= 132 Ω
Z
S
Z
O
Z
T
= 0 Ω
= 100 Ω
= 90 Ω
V at Load
V at Load
V
I
V
I
0.15
0.1
0.15
0.1
0.05
0
0.05
0
0
5
10
15
20
25
0
5
10
15
20
25
t – Time – ns
t – Time – ns
Figure 14. Low-Source Impedance
Figure 15. High-Source Impedance
For example a 200-mV drive signal into a 100-Ω lossless transmission media with a termination resistor of 90 Ω
to 132 Ω results in ~227 mV to 189 mV into the receiver. This would typically be more than enough signal into
a receiver with a sensitivity of ±50 mV assuming no other disturbance or attenuation on the line. The other
factors, which reduce the signal margin, do affect this and therefore it is important to match the impedance as
closely as possible to allow more noise immunity at the receiver.
14
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
APPLICATION INFORMATION
active failsafe feature
A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current
LVDS failsafe solutions require either external components with subsequent reductions in signal quality or
integrated solutions with limited application. This family of receivers has a new integrated failsafe that solves
the limitations seen in present solutions. A detailed theory of operation is presented in application note The
Active Fail-Safe in TI’s LVDS Receivers, literature number SLLA082B.
The following figure shows one receiver channel with active failsafe. It consists of a main receiver that can
respond to a high-speed input differential signal. Also connected to the input pair are two failsafe receivers that
form a window comparator. The window comparator has a much slower response than the main receiver and
it detects when the input differential falls below 80 mV. A 600-ns failsafe timer filters the window comparator
outputs. When failsafe is asserted, the failsafe logic drives the main receiver output to logic high.
Output
Buffer
Main Receiver
+
_
A
B
R
Failsafe
Timer
Reset
A > B + 80 mV
+
_
Failsafe
B > A + 80 mV
+
_
Window Comparator
Figure 16. Receiver With Active Failsafe
15
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
APPLICATION INFORMATION
ECL/PECL-to-LVTTL conversion with TI’s LVDS receiver
The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer of
choice for system designers. Designers know that established technology is capable of high-speed data
transmission. In the past, system requirements often forced the selection of ECL. Now technologies like LVDS
provide designers with another alternative. While the total exchange of ECL for LVDS may not be a design
option, designers have been able to take advantage of LVDS by implementing a small resistor divider network
at the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode LVDSreceiver
(no divider network required) which can be connected directly to an ECL driver with only the termination bias
voltage required for ECL termination (V
– 2 V).
CC
Figure 17 shows the use of an LV/PECL driver driving 5 meters of CAT–5 cable and being received by TI’s wide
common-mode receiver and the resulting eye-pattern. The values for R3 are required in order to provide a
resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the
characteristic load impedance of 50 Ω. The R2 resistor is a small value intended to minimize common-mode
reflections.
V
V
CC
I
CC
I
R1 = 50 Ω
R2 = 50 Ω
CC
CC
V
B
5 Meters
of CAT-5
LV/PECL
LVDS
V
B
R3
R3
R1
R1
V
EE
R2
R3 = 240 Ω
Figure 17. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver
16
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
APPLICATION INFORMATION
device power and grounding
The SN65LVDS352 device provides separate power and ground pins for the analog input section and the two
digital output sections. All of the power pins and all of the ground pins of the device must be tied together at some
point in the system. Figure 18 shows one recommended scheme for power and ground to the device. This point
will be determined by the power and grounding distribution design, which can greatly affect system
performance.
Key points to remember when routing power and grounds in your system are:
D
D
D
D
The grounding system must provide a low impedance path back to the power source.
The signal return must be close to the signal path.
Ground noise occurs due to ground loops and common-mode noise pick-up.
Closely spaced power and ground planes reduce inductance and increase capacitance.
A good rule to remember when doing your power distribution and board layout is that the current always flows
in the lowest impedance path. At dc the lowest resistance is the lowest impedance, but at high frequencies the
lowest impedance is the lowest inductance path.
V
CC
V
CCD1
Bypass
†
Capacitor
DGND1
V
CCA
Bypass
†
Capacitor
AGND
V
CCD2
Bypass
†
Capacitor
DGND2
†
Bypass capacitors used for data sheet electrical testing were low ESR ceramic, surface mount, 0.01 µF ±10%. For a more accurate
determination of these values refer to the application note, The Bypass Capacitor in High-Speed Environments, literature number
SCBA007A.
Figure 18. Recommended Power and Ground Connection
17
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
0.010 (0,25)
8
5
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.069 (1,75) MAX
0.004 (0,10)
0.004 (0,10)
PINS **
8
14
16
DIM
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/E 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
18
www.ti.com
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–ā8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
19
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明