SN65MLVD040RGZT_技术文档

SN65MLVD040

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SLLS902 –FEBRUARY 2010

4-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS

Check for Samples: SN65MLVD040

1

FEATURES

APPLICATIONS

•

Parallel Multipoint Data and Clock

Transmission Via Backplanes and Cables

Low-Power High-Speed Short-Reach

Alternative to TIA/EIA-485

2

•

Low-Voltage Differential 30-Ω to 55-Ω Line

Drivers and Receivers for Signaling Rates⁽¹⁾Up

to 250 Mbps; Clock Frequencies Up to

125 MHz

•

Cellular Base Stations

Central-Office Switches

Network Switches and Routers⁽¹⁾

•

Meets or Exceeds the M-LVDS Standard

TIA/EIA-899 for Multipoint Data Interchange

Controlled Driver Output Voltage Transition

Times for Improved Signal Quality

LOGIC DIAGRAM (POSITIVE LOGIC)

SN65MLVD040

–1 V to 3.4 V Common-Mode Voltage Range

Allows Data Transfer With 2 V of Ground Noise

Channel 1

1DE

1A

Bus Pins High Impedance When Driver

Disabled or V_CC≤ 1.5 V

1D

1B

1FSEN

Independent Enables for each Driver and

Receiver

1R

1RE

PDN

Enhanced ESD Protection: 7 kV HBM on all

Pins

2DE - 4E

3

•

48 pin 7 X 7 QFN (RGZ)

2D - 4D

3

M-LVDS Bus Power Up/Down Glitch Free

2A - 4A

2FSEN –

Channels 2 - 4

3

4FSEN

2B - 4B

2R - 4R

3

2RE – 4RE

(1) The signaling rate of a line, is the number of voltage

transitions that are made per second expressed in the units

bps (bits per second).

DESCRIPTION

The SN65MLVD040 provides four half-duplex transceivers for transmitting and receiving Multipoint-Low-Voltage

Differential Signals in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at

signaling rates up to 250 Mbps. The driver outputs have been designed to support multipoint buses presenting

loads as low as 30-Ω and incorporates controlled transition times to allow for stubs off of the backplane

transmission line.

The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers have

thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2

receivers implement a failsafe by using an offset threshold. The xFSEN pins is used to select the Type-1 and

Type-2 receiver for each of the channels. In addition, the driver rise and fall times are between 1 ns and 2 ns,

complying with the M-LVDS standard to provide operation at 250 Mbps while also accommodating stubs on the

bus. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current

surges. The M-LVDS standard allows for 32 nodes on the bus providing a high-speed replacement for RS-485

where lower common-mode can be tolerated or when higher signaling rates are needed.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SN65MLVD040

SLLS902 –FEBRUARY 2010

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION CONTINUED

The driver logic inputs and the receiver logic outputs are on separate pins rather than tied together as in some

transceiver designs. The drivers have separate enables (DE) and so does the receivers (RE). This arrangement

of separate logic inputs, logic outputs, and enable pins allows for a listen-while-talking operation. The devices are

characterized for operation from –40°C to 85°C.

Pin Functions

I/O

DESCRIPTION

NAME

1D–4D

1R–4R

1A–4A

1B–4B

NO.

35, 32, 28, 25

36, 33, 29, 26

47, 3, 9, 13

48, 4, 10, 14

I

Data inputs for drivers

O

Data output for receivers

Bus I/O M-LVDS bus non-inverting input/output

Bus I/O M-LVDS bus inverting input/output

6, 7, 18, 23, 27, 31, 34, 38,

43

GND

V_CC

Circuit ground. ALL GND pins must be connected to ground.

Supply voltage. ALL VCC pins must be connected to supply.

2, 11, 15, 16, 24, 37, 45,

46

Receiver enable, active low, enable individual receivers. When this pin is left

floating, internally this pin will be pulled to logic HIGH.

1RE–4RE

1DE–4DE

40, 42, 19, 21

1, 5, 8, 12

I

Driver enable, active high, individual enables the drivers. When this pin is left

floating, internally this pin will be pulled to logic LOW.

I

Failsafe enable pin. When this pin is left floating, internally this pin will be

pulled to logic HIGH.

This pin enables the Type 2 receiver for the respective channel.

xFSEN = L → Type 1 receiver inputs

xFSEN = H → Type 2 receiver inputs

1FSEN–4FSEN

39, 41, 20, 22

I

Power Down pin. When this pin is left floating, internally this pin will be pulled

to logic LOW.

When PDN is HIGH, the device is powered up.

When PDN is LOW, the device overrides all other control and powers down. All

outputs are Hi-Z.

PDN

30

NC

17

44

–

Not Connected

Not Connected. Internal TI Test pin. This pin must be left unconnected.

Connected to GND

PowerPAD™

2

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PIN ASSIGNMENTS

RGZ PACKAGE

(TOP VIEW)

1DE

1R

1D

36

35

34

33

32

1

2

VCC

2A

GND

2R

3

2B

4

2DE

GND

3DE

3A

2D

5

GND

31

30

29

28

27

26

25

6

PDN

3R

7

8

3D

9

GND

4R

3B

10

11

12

VCC

4DE

4D

Table 1. Device Function Tables

RECEIVER

DRIVER

RECEIVER

OUTPUT⁽¹⁾

TYPE

INPUTS⁽¹⁾

PDN

INPUTS⁽¹⁾

OUTPUTS⁽¹⁾

V_ID= V_A– V_B

FSEN

RE

L

R

H

?

D

DE

A

L

B

H

L

V_ID> 35 mV

–35 mV ≤ V_ID≤ 35 mV

V_ID< 35 mV

H

L

Type 1

L

H

L

H

L

OPEN

X

H

Z

OPEN

L

Z

V_ID> 135 mV

65 mV ≤ V_ID≤ 135 mV

V_ID< 65 mV

H

L

Type 2

H

?

L

X

Open Circuit

H

L

Type 1

Type 2

?

L

H

X

H

L

X

H

OPEN

X

Z

(1) H=high level, L=low level, Z=high impedance, X=Don’t care, ?=indeterminate

ORDERING INFORMATION

PART NUMBER

SN65MLVD040RGZR

SN65MLVD040RGZT

RECEIVER TYPE

PACKAGE MARKING

PACKAGE/CARRIER

48-Pin QFN/ Tape and Reeled

Type 1, 2

MLVD040

Type 1, 2

MLVD040

48-Pin QFN/Small Tape and Reeled

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PACKAGE DISSIPATION RATINGS

T

_A≤ 25°C

DERATING FACTOR⁽¹⁾

ABOVE T_A= 25°C

T_A= 85°C

POWER RATING

PCB JEDEC

PACKAGE

POWER RATING

STANDARD

RGZ

Low-K⁽²⁾

High-K⁽³⁾

1298 mW

12.98 mW/°C

34.48 mW/°C

519 mW

3448 mW

1379 mW

(1) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.

(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.

(3) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.

THERMAL CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

TYP

9

MAX

UNIT

°C/W

R_qJB

R_qJC

R_qJP

Junction-to-board thermal resistance

Junction-to-case thermal resistance

Junction-to-pad thermal resistance

20

1.37

Device power dissipation (See typical REat 0 V, DE at 0 V, C_L= 15 pF, V_ID= 400 mW,

curves for additional information) 125 MHz, All others open

P_D

382

mW

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted⁽¹⁾

SN65MLVD040

–0.5 V to 4 V

–1.8 V to 4 V

–0.3 V to 4 V

–1.8 V to 4 V

±7 kV

Supply voltage range⁽²⁾, V_CC

D, DE, RE, FSEN

Input voltage range

A, B

R

Output voltage range

A, or B

Human Body Model⁽³⁾

Charged-Device Model⁽⁴⁾

All pins

Electrostatic discharge

±1500 V

Storage temperature range

–65°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

(3) Tested in accordance with JEDEC Standard 22, Test Method A114-E. Bus pin stressed with respect to a common connection of GND

and V_CC

(4) Tested in accordance with JEDEC Standard 22, Test Method C101-D.

RECOMMENDED OPERATING CONDITIONS

MIN

3

NOM

MAX

3.6

UNIT

V

V_CC

V_IH

V_IL

Supply voltage

3.3

High-level input voltage

2

V_CC

0.8

V

Low-level input voltage

GND

–1.4

0.05

–40

V

Voltage at any bus terminal V_Aor V_B

Magnitude of differential input voltage

Operating free-air temperature

Maximum junction temperature

3.8

V

|V_ID

|

V_CC

85

V

T_A

°C

140

4

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DEVICE ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

RE and DE at V_CC, R_L= 50 Ω, 125MHz, All

others open

Driver only

76

RE at V_CC, DE at 0 V, R_L= No Load,

125MHz, All others open

Both disabled

Both enabled

Receiver only

10

Supply

current

I_CC

mA

REat 0 V, DE at V_CC, R_L= 50 Ω, C_L= 15

pF, All others open, 125MHz, No external

RX stimulus

165

REat 0 V, DE at 0 V, C_L= 15 pF, V_ID= 400

mV, 125 MHz, All others open

100

Power down PDN = L

5

mA

(1) All typical values are at 25°C and with a 3.3-V supply voltage.

DRIVER ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN⁽¹⁾

TYP⁽²⁾

MAX

UNIT

|V_AB

|

Differential output voltage magnitude (A, B)

480

650

mV

Change in differential output voltage

magnitude

between logic states (A, B)

See Figure 2

See Figure 3

Δ|V_AB

|

–50

50

mV

Steady-state common-mode output voltage

(A, B)

V_OS(SS)

ΔV_OS(SS)

V_OS(PP)

V_A(OC)

V_B(OC)

V_P(H)

0.7

1.1

50

V

mV

V

Change in steady-state common-mode

output voltage between logic states (A, B)

–50

Peak-to-peak common-mode output voltage

(A, B)

150

Maximum steady-state open-circuit output

voltage (A, B)

0

2.4

See Figure 7

See Figure 5

Maximum steady-state open-circuit output

voltage (A, B)

2.4

V

Voltage overshoot, low-to-high level output

(A, B)

1.2 V_SS

V

Voltage overshoot, high-to-low level output

(A, B)

V_P(L)

–0.2 V_SS

V

I_IH

I_IL

High-level input current (D, DE)

Low-level input current (D, DE)

V_IH= 2 V to V_CC

10

mA

V_IL= GND to 0.8 V

Differential short-circuit output current

magnitude (A, B)

|I_OS

C_I

|

See Figure 4

24

mA

pF

(3)

Input capacitance (D, DE)

V_I= 0.4 sin(30E6pt) + 0.5 V

5

(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

(2) All typical values are at 25°C and with a 3.3-V supply voltage.

(3) HP4194A impedance analyzer (or equivalent)

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RECEIVER ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

35

UNIT

Type 1

Type 2

Type 1

Type 2

Type 1

Type 2

Positive-going differential input

voltage threshold (A, B)

V_IT+

V_IT–

V_HYS

mV

135

–35

65

Negative-going differential input

voltage threshold (A, B)

See Table 2 and

Table 3

mV

25

0

Differential input voltage hysteresis,

(V_IT+– V_IT–) (A, B)

V_OH

V_OL

I_IH

High-level output voltage (R)

Low-level output voltage (R)

High-level input current (RE)

Low-level input current (RE)

High-impedance output current (R)

I_OH= –8 mA

2.4

V

I_OL= 8 mA

0.4

15

V

V_IH= 2 V to V_CC

V_IL= GND to 0.8 V

V_O= 0 V or V_CC

–10

mA

I_IL

I_OZ

(1) All typical values are at 25°C and with a 3.3-V supply voltage.

BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

Receiver or transceiver V_A= 3.8 V,

with driver disabled

V_B= 1.2 V

32

I_A

mA

V_A= –1.4 V,

input current

V_B= 1.2 V

V_A= 1.2 V

–32

Receiver or transceiver V_B= 3.8 V,

with driver disabled

32

I_B

mA

V_B= –1.4 V,

input current

–32

–4

Receiver or transceiver

with driver disabled

differential input current

(I_A– I_B)

I_AB

V_A= V_B

,

1.4 ≤ V_A≤ 3.8 V

4

32

V_A= 3.8 V,

V_A= –1.4 V,

V_B= 3.8 V,

V_B= –1.4 V,

V_B= 1.2 V,

V_A= 1.2 V,

0 V ≤ V_CC≤ 1.5 V

Receiver or transceiver

power-off input current

I_A(OFF)

mA

0 V ≤ V_CC≤ 1.5 V

–32

–4

Receiver or transceiver

power-off input current

I_B(OFF)

Receiver input or

transceiver power-off

differential input current

I_AB(OFF)

V_A= V_B, 0 V ≤ V_CC≤ 1.5 V, –1.4 ≤ V_A≤ 3.8 V

4

mA

(I_A(off)– I_B(off)

)

Transceiver with driver

disabled

input capacitance

C_A

C_B

V_A= 0.4 sin (30E6pt) + 0.5 V⁽²⁾

,

V_B= 1.2 V

V_A= 1.2 V

5

pF

Transceiver with driver

disabled

V_B= 0.4 sin (30E6pt) + 0.5 V⁽²⁾

input capacitance

Transceiver with driver

disabled

differential input

capacitance

C_AB

V_AB= 0.4 sin (30E6pt)V⁽²⁾

3

pF

Transceiver with driver

disabled

input capacitance

balance, (C_A/C_B)

C_A/B

0.99

1.01

(1) All typical values are at 25°C and with a 3.3-V supply voltage.

(2) HP4194A impedance analyzer (or equivalent)

6

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DRIVER SWITCHING CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

Propagation delay time,

low-to-high-level output

t_pLH

t_pHL

1.3

1.9

2.4

ns

Propagation delay time,

high-to-low-level output

1.3

1.9

2.4

ns

t_r

Differential output signal rise time

Differential output signal fall time

Output skew

0.9

2

2.2

ns

ps

See Figure 5

t_f

t_sk(o)

t_sk(p)

t_sk(pp)

200

150

300

Pulse skew (|t_PHL– t_PLH|)

(2)

Part-to-part skew

Period jitter, rms (1 standard

deviation)⁽³⁾

Cycle-to-cycle jitter, rms⁽³⁾

Deterministic jitter⁽³⁾

t_jit(per)

2

ps

All channels switching, 125 MHz

clock input⁽⁴⁾, see Figure 8

t_jit(c-c)

t_jit(det)

t_jit(r)

9

290

4

ps

All channels switching, 250 Mbps

2¹⁵–1 PRBS input⁽⁴⁾, see Figure 8

(3)

Random jitter

Enable time,

t_PZH

t_PZL

t_PHZ

t_PLZ

high-impedance-to-high-level

output

7

ns

Enable time,

high-impedance-to-low-level output

See Figure 6

Disable time,

high-level-to-high-impedance

output

Disable time,

low-level-to-high-impedance output

(1) All typical values are at 25°C and with a 3.3-V supply voltage.

(2) t_sk(pp)is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both

devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.

(4) t_r= t_f= 0.5 ns (10% to 90%)

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RECEIVER SWITCHING CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

2.5

1.4

TYP⁽¹⁾

4.5

MAX

6

UNIT

ns

t_pLH

t_pHL

t_r

Propagation delay time, low-to-high-level output

Propagation delay time, high-to-low-level output

Output signal rise time

4.5

6

ns

2.35

350

210

470

800

6

ns

t_f

Output signal fall time

ns

C_L= 15 pF, See Figure 10

t_sk(o)

Output skew

ps

Type 1

Pulse skew (|t_PHL– t_PLH|)

Type 2

Part-to-part skew⁽²⁾

35

t_sk(p)

ps

150

t_sk(pp)

t_jit(per)

t_jit(c-c)

ps

(3)

Period jitter, rms (1 standard deviation)

All channels switching, 125

MHz clock input⁽⁴⁾, See

Figure 12

Cycle-to-cycle jitter, rms⁽³⁾

13

ps

Type 1

Deterministic jitter⁽³⁾

Type 2

800

945

9

ps

ns

t_jit(det)

All channels switching, 250

Mbps 2¹⁵–1 PRBS

input⁽⁴⁾,See Figure 12

Type 1

(3)

t_jit(r)

Random jitter

Type 2

8

t_PZH

t_PZL

t_PHZ

t_PLZ

Enable time, high-impedance-to-high-level output

Enable time, high-impedance-to-low-level output

Disable time, high-level-to-high-impedance output

Disable time, low-level-to-high-impedance output

15

10

C_L= 15 pF, See Figure 11

(1) All typical values are at 25°C and with a 3.3-V supply voltage.

(2) t_sk(pp)is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both

devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.

(4) t_r= t_f= 0.5 ns (10% to 90%)

8

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PARAMETER MEASUREMENT INFORMATION

V

CC

I

A

B

I

D

V

AB

I

B

V

A

V

I

V

OS

V

B

V

A

+ V

2

B

Figure 1. Driver Voltage and Current Definitions

3.32 kΩ

A

+

-1 V ≤ V

≤ 3.4 V

V

AB

49.9 Ω

D

test

_

B

3.32 kΩ

NOTE: All resistors are 1% tolerance.

Figure 2. Differential Output Voltage Test Circuit

A

B

R1

≈ 1.3 V

24.9 Ω

A

B

≈ 0.7 V

C1

1 pF

D

V

∆V

OS(SS)

OS(PP)

V

OS

C3

2.5 pF

R2

24.9 Ω

V

OS(SS)

C2

1 pF

A. All input pulses are supplied by a generator having the following characteristics: t_ror t_f≤ 1 ns, pulse frequency = 1

MHz, duty cycle = 50 ±5%.

B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.

C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.

D. The measurement of V_OS(PP)is made on test equipment with a –3 dB bandwidth of at least 1 GHz.

Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage

I

OS

A

B

0 V or V

CC

+

V

-

-1 V or 3.4 V

Test

Figure 4. Driver Short-Circuit Test Circuit

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PARAMETER MEASUREMENT INFORMATION (continued)

A

C1

1 pF

C3

0.5 pF

R1

50 Ω

Output

D

B

C2

1 pF

V

CC

/2

CC

Input

0 V

t

pHL

pLH

V

SS

0.9V

SS

V

P(H)

Output

0 V

V

P(L)

0.1V

SS

0 V

SS

t

f

t

r

A. All input pulses are supplied by a generator having the following characteristics: t_ror t_f≤ 1 ns, frequency = 1 MHz,

duty cycle = 50 ±5%.

B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.

C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.

D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.

Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal

R1

24.9 Ω

A

C1

1 pF

D

C4

0.5 pF

0 V or V

Output

CC

C3

2.5 pF

C2

1 pF

B

R2

24.9 Ω

DE

V

CC

/2

CC

DE

0 V

t

pZH

pHZ

0.6 V

0.1 V

Output With

D at V

0 V

CC

t

pZL

pLZ

Output With

D at 0 V

0 V

-0.1 V

-0.6 V

A. All input pulses are supplied by a generator having the following characteristics: t_ror t_f≤ 1 ns, frequency = 1 MHz,

duty cycle = 50 ±5%.

B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.

C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.

D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.

Figure 6. Driver Enable and Disable Time Circuit and Definitions

10

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PARAMETER MEASUREMENT INFORMATION (continued)

A

0 V or V

CC

B

V

A

or V

B

1.62 kΩ , ±1%

Figure 7. Maximum Steady State Output Voltage

V

CC

CLOCK

INPUT

/2

CC

0 V

1/f0

Period Jitter

IDEAL

OUTPUT

V

CC

0 V

PRBS INPUT

/2

CC

V

A

-V

B

1/f0

0 V

ACTUAL

OUTPUT

Peak to Peak Jitter

0 V

V

-V

A

B

V

-V

B

A

OUTPUT 0 V

t

c(n)

V

A

t

=

t

-1/f0

B

jit(per)

c(n)

t

jit(pp)

Cycle to Cycle Jitter

OUTPUT

0 V

V - V

A

B

t

c(n+1)

c(n)

t

= | t

- t

|

jit(cc)

c(n) c(n+1)

A. All input pulses are supplied by the Agilent 81250 Parallel BERT Stimulus System with plug-in E4832A.

B. The cycle-to-cycle measurement is made on a TEK TDS6604 running TDSJIT3 application software.

C. All other jitter measurements are made with an Agilent Infiniium DCA-J 86100C Digital Communications Analyzer.

D. Period jitter and cycle-to-cycle jitter are measured using a 125 MHz 50 ±1% duty cycle clock input. Measured over

75K samples.

E. Deterministic jitter and random jitter are measured using a 250 Mbps 2¹⁵–1 PRBS input. Measured over BER = 10^-12

Figure 8. Driver Jitter Measurement Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

I

A

B

I

O

R

V

ID

V

O

V

CM

V

A

I

B

(V + V )/2

V

B

A

B

Figure 9. Receiver Voltage and Current Definitions

Table 2. Type-1 Receiver Input Threshold Test Voltages

RESULTING DIFFERENTIAL

INPUT VOLTAGE

RESULTING COMMON-

MODE INPUT VOLTAGE

APPLIED VOLTAGES

RECEIVER

OUTPUT⁽¹⁾

V_IA

2.400

0.000

3.400

3.365

–0.965

–1

V_IB

0.000

2.400

3.365

3.400

–1

V_ID

V_IC

2.400

–2.400

0.035

–0.035

0.035

–0.035

1.200

H

L

1.200

3.3825

–0.9825

H

L

H

L

–0.965

(1) H= high level, L = low level, output state assumes receiver is enabled (RE = L)

Table 3. Type-2 Receiver Input Threshold Test Voltages

RESULTING DIFFERENTIAL

INPUT VOLTAGE

RESULTING COMMON-

MODE INPUT VOLTAGE

APPLIED VOLTAGES

RECEIVER

OUTPUT⁽¹⁾

V_IA

V_IB

0.000

2.400

3.265

3.335

–1

V_ID

V_IC

2.400

0.000

3.400

3.4000

–0.865

–0.935

2.400

–2.400

0.135

0.065

0.135

0.065

1.200

H

L

1.200

3.3325

3.3675

–0.9325

–0.9675

H

L

H

L

–1

(1) H= high level, L = low level, output state assumes receiver is enabled (RE = L)

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V

ID

V

A

C

L

V

O

15 pF

V

B

V

1.2 V

1.0 V

A

V

B

V

ID

0.2 V

0 V

-0.2 V

t

pLH

pHL

V

OH

V

O

90%

10%

V

/2

CC

OL

t

f

t

r

A. All input pulses are supplied by a generator having the following characteristics: t_ror t_f≤ 1 ns, frequency = 1 MHz,

duty cycle = 50 ±5%. C_Lis a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture

capacitance within 2 cm of the D.U.T.

B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.

Figure 10. Receiver Timing Test Circuit and Waveforms

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R

L

B

A

1.2 V

499 Ω

+

C

L

V

TEST

V

O

_

Inputs

RE

15 pF

V

CC

V

TEST

1 V

A

V

CC

RE

/2

CC

0 V

t

pLZ

pZL

V

CC

V

CC

V

O

V

OL

V

OL

+0.5 V

V

TEST

0 V

1.4 V

A

V

CC

RE

/2

CC

0 V

t

pHZ

pZH

V

OH

-0.5 V

OH

V

O

/2

CC

0 V

A. All input pulses are supplied by a generator having the following characteristics: t_ror t_f≤ 1 ns, frequency = 1 MHz,

duty cycle = 50 ± 5%.

B. R_Lis 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.

C. C_Lis the instrumentation and fixture capacitance within 2 cm of the DUT and ±20%. The measurement is made on

test equipment with a –3 dB bandwidth of at least 1 GHz.

Figure 11. Receiver Enable/Disable Time Test Circuit and Waveforms

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INPUTS

CLOCK INPUT

V

A

- V

V

CM

B

0.2 V

0.4 V

Type 1

Type 2

pk

V

A

-V

B

1 V

1/f0

pk

Period Jitter

V

OH

IDEAL

OUTPUT

V

A

V /2

CC

PRBS INPUT

V

OL

1/f0

V

B

V

OH

ACTUAL

OUTPUT

Peak to Peak Jitter

V

/2

CC

V

OH

V

OL

OUTPUT

V /2

CC

t

c(n)

t

= | t

-1/f0 |

V

OL

jit(per)

c(n)

t

jit(pp)

Cycle to Cycle Jitter

V

OH

OUTPUT

V /2

CC

V

OL

t

c(n+1)

c(n)

t

= | t - t

c(n) c(n+1)

|

jit(cc)

A. All input pulses are supplied by the Agilent 81250 Parallel BERT Stimulus System with plug-in E4832A.

B. The cycle-to-cycle measurement is made on a TEK TDS6604 running TDSJIT3 application software.

C. All other jitter measurements are made with an Agilent Infiniium DCA-J 86100C Digital Communications Analyzer.

D. Period jitter and cycle-to-cycle jitter are measured using a 125 MHz 50 ±1% duty cycle clock input. Measured over

75K samples.

E. Deterministic jitter and random jitter are measured using a 250 Mbps 2¹⁵–1 PRBS input. Measured over BER = 10^-12

Figure 12. Receiver Jitter Measurement Waveforms

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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

DRIVER OUTPUT

DRIVER INPUT AND DRIVER ENABLE

RECEIVER ENABLE

V

CC

V

CC

V

CC

360 kΩ

400 Ω

D or DE

7 V

Y or Z

RE

7 V

360 kΩ

RECEIVER INPUT

RECEIVER OUTPUT

V

CC

V

CC

100 kΩ

250 kΩ

100 kΩ

250 kΩ

10 Ω

R

A

B

200 kΩ

7 V

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

vs

SUPPLY CURRENT

vs

FREQUENCY

FREE-AIR TEMPERATURE

150

100

50

100

80

V

= 3.3 V,

CC

Rx

T

= 25°C,

= 400 mV,

= 1 V

A

Tx & Rx

V

ID

IC

60

Tx

Rx

Tx

40

20

0

V

= 3.3 V,

CC

f = 100 MHz,

V

= 800 mV,

ID

IC

V

= 1 V

0

-40

25

85

0

25

50

75

100

125

T

- Free-Air Temperature - °C

A

f - Frequency - MHz

Figure 13.

Figure 14.

16

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TYPICAL CHARACTERISTICS (continued)

DIFFERENTIAL OUTPUT VOLTAGE

vs

FREQUENCY

OUTPUT RESISTANCE

3000

2000

1000

0

1500

V

T

= 3.3 V,

V

T

= 3.3 V,

CC

= 25°C

A

1000

500

0

50

100

150

25

50

75

100

125

Output Resistance - W

f - Frequency - MHz

Figure 15.

Figure 16.

DIFFERENTIAL OUTPUT VOLTAGE

DRIVER PROPAGATION DELAY

vs

TRACE LENGTH

FREE-AIR TEMPERATURE

1500

3

2.5

2

V

T

= 3.3 V,

V

= 3.3 V,

CC

f = 1 MHz

= 25°C,

A

Trace Width = 8 mil,

f = 1 MHz

1000

500

0

t

PLH

t

PHL

1.5

1

-40

25

85

T

- Free-Air Temperature - °C

A

Trace Length - inches

Figure 17.

Figure 18.

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TYPICAL CHARACTERISTICS (continued)

RECEIVER TYPE-1 PROPAGATION DELAY

RECEIVER TYPE-2 PROPAGATION DELAY

vs

FREE-AIR TEMPERATURE

5

4.5

4

5

4.5

4

V

= 3.3 V,

CC

f = 1 MHz,

C

= 15 pF,

= 800 mV,

= 1 V

t

L

PHL

V

ID

IC

t

V

PLH

t

PLH

t

PHL

V

= 3.3 V,

CC

f = 1 MHz,

3.5

C

= 15 pF,

= 400 mV,

= 1 V

L

V

ID

IC

V

3

-40

25

85

-40

25

85

T

- Free-Air Temperature - °C

T

- Free-Air Temperature - °C

A

Figure 19.

Figure 20.

DRIVER TRANSITION TIME

vs

TYPE-1 RECEIVER TRANSITION TIME

vs

FREE-AIR TEMPERATURE

3

V

= 3.3 V,

CC

f = 1 MHz,

V

= 3.3 V,

CC

f = 1 MHz

C

= 15 pF,

= 400 mV,

= 1 V

L

V

ID

IC

2.5

V

t

r

2

1.5

1

2

1.5

1

t

f

t

f

t

r

-40

25

85

-40

25

85

T

- Free-Air Temperature - °C

T

- Free-Air Temperature - °C

A

Figure 21.

Figure 22.

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TYPICAL CHARACTERISTICS (continued)

TYPE-2 RECEIVER TRANSITION TIME

ADDED RECEIVER TYPE-1 PERIOD JITTER

vs

FREE-AIR TEMPERATURE

FREQUENCY

3

2.5

2

10

8

V

= 3.3 V,

V

= 3.3 V,

CC

f = 1 MHz,

CC

TA = 25°C,

C

= 15 pF,

= 800 mV,

= 1 V

V

= 400 mV,

L

ID

V

= 1 V,

ID

IC

Input = Clock

V

6

t

r

4

t

f

1.5

2

0

1

-40

25

- Free-Air Temperature - °C

85

50

75

100

125

T

f - Frequency - MHz

A

Figure 23.

Figure 24.

ADDED RECEIVER TYPE-2 PERIOD JITTER

ADDED DRIVER PERIOD JITTER

vs

FREQUENCY

4

3

10

8

V

= 3.3 V,

V

= 3.3 V,

CC

TA = 25°C,

CC

TA = 25°C,

V

= 800 mV,

Input = Clock

ID

V

= 1 V,

IC

Input = Clock

6

2

1

0

4

2

0

50

75

100

125

50

75

100

125

f - Frequency - MHz

Figure 25.

Figure 26.

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TYPICAL CHARACTERISTICS (continued)

ADDED RECEIVER TYPE-1 CYCLE-TO-CYCLE JITTER

ADDED RECEIVER TYPE-2 CYCLE-TO-CYCLE JITTER

vs

FREQUENCY

15

10

5

V

= 3.3 V,

CC

TA = 25°C,

V

= 400 mV,

ID

V

= 1 V,

IC

Input = Clock

10

5

0

V

= 3.3 V,

CC

TA = 25°C,

V

= 800 mV,

ID

V

= 1 V,

IC

Input = Clock

0

50

75

100

125

50

75

100

125

f - Frequency - MHz

Figure 27.

Figure 28.

ADDED DRIVER CYCLE-TO-CYCLE JITTER

ADDED RECEIVER TYPE-1 DETERMINISTIC JITTER

vs

FREQUENCY

DATA RATE

50

40

30

20

800

V

= 3.3 V,

V

= 3.3 V,

CC

TA = 25°C,

CC

TA = 25°C,

Input = Clock

V

= 400 mV,

ID

IC

V

= 1 V

600

400

200

0

Input = PRBS 2¹⁵-1

10

0

50

100

150

200

250

50

75

100

125

Data Rate - Mbps

f - Frequency - MHz

Figure 29.

Figure 30.

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TYPICAL CHARACTERISTICS (continued)

ADDED RECEIVER TYPE-2 DETERMINISTIC JITTER

vs

DRIVER OUTPUT EYE PATTERN

250 Mbps, 2¹⁵–1 PRBS, V_CC= 3.3 V

DATA RATE

800

600

400

200

0

V

= 3.3 V,

CC

TA = 25°C,

V

= 800 mV,

ID

IC

V

= 1 V

Input = PRBS 2¹⁵-1

50

100

150

200

250

Data Rate - Mbps

Figure 31.

Figure 32.

RECEIVER OUTPUT EYE PATTERN

250 Mbps, 2¹⁵–1 PRBS, V_CC= 3.3 V

|V_ID| = 400 mV_PP, V_IC= 1 V

RECEIVER OUTPUT EYE PATTERN

250 Mbps, 2¹⁵–1 PRBS, V_CC= 3.3 V

|V_ID| = 800 mV_PP, V_IC= 1 V

Figure 33.

Figure 34.

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APPLICATION INFORMATION

Source Synchronous System Clock (SSSC)

There are two approaches to transmit data in a synchronous system: centralized synchronous system clock

(CSSC) and source synchronous system clock (SSSC). CSSC systems synchronize data transmission between

different modules using a clock signal from a centralized source. The key requirement for a CSSC system is for

data transmission and reception to complete during a single clock cycle. The maximum operating frequency is

the inverse of the shortest clock cycle for which valid data transmission and reception can be ensured. SSSC

systems achieve higher operating frequencies by sending clock and data signals together to eliminate the flight

time on the transmission media, backplane, or cables. In SSSC systems, the maximum operating frequency is

limited by the cumulated skews that can exist between clock and data. The absolute flight time of data on the

backplane does not provide a limitation on the operating frequency as it does with CSSC.

The SN65MLVD082 can be designed for interfacing the data and clock to support source synchronous system

clock (SSSC) operation. It is specified for transmitting data up to 250 Mbps and clock frequencies up to 125

MHz. Figure 35 shows an example of a SSSC architecture supported by M-LVDS transceivers. The

SN65MLVD206, a single channel transceiver, transmits the main system clock between modules. A retiming unit

is then applied to the main system clock to generate a local clock for subsystem synchronization processing.

System operating data (or control) and subsystem clock signals are generated from the data processing unit,

such as a microprocessor, FPGA, or ASIC, on module 1, and sent to slave modules through the SN65MLVD082.

Such design configurations are common while transmitting parallel control data over the backplane with a higher

SSSC subsystem clock frequency. The subsystem clock frequency is aligned with the operating frequencies of

the data processing unit to synchronize data transmission between different units.

Main System Clock

MLVD206

1Tx 1Rx

Modules 1

Modules N

Data Process Unit

ASIC/FPGA

uController

Data Process Unit

ASIC/FPGA

uController

Timing

Process

Unit

Timing

Process

Unit

tsk(o)Source

1 Data Width 15

Subsystem

Clock

1 Data Width 15

Subsystem

Clock

tsk(pp)RCVR

Number of Modules

MLVD206

1Tx 1Rx

MLVD206

1Tx 1Rx

MLVD040 (x2)

4Tx 4Rx

MLVD040 (x2)

4Tx 4Rx

tsk(pp)DRVR

Centralized - Synchronous Main System Clock M-LVDS Differential Bus

80 ~ 100W R

T

80 ~ 100W R

T

Data/Control M-LVDS Differential Bus #1 ~ #15

tsk(flight)BP

80 ~ 100W R

T

80 ~ 100W R

T

Source - Synchronous Subsystem Clock M-LVDS Differential Bus

80 ~ 100W R

T

M-LVDS Backplane

Figure 35. Using Differential M-LVDS to Perform Source Synchronous System Clock Distribution

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The maximum SSSC frequencies in a transparent mode can be calculated with Equation 1:

f_max(clk)< 1/[ t_sk(o)Source+ t_sk(pp)DRVR+ t_sk(flight)BP+ t_sk(pp)RCVR

(1)

Setup time and hold time on the receiver side are decided by the data processing unit, FPGA, or ASIC in this

example. By considering data passes through the transceiver only, the general calculation result is 238 MHz

when using the following data:

t_sk(o)Source= 2 ns – Output skew of data processing unit; any skew between data bits, or clock and data bits

t_sk(pp)DRVR= 0.6 ns – Driver part-to-part skew of the SN65MLVD040

t_sk(flight)BP= 0.4 ns – Skew of propagation delay on the backplane between data and clock

t_sk(pp)RCVR= 1 ns – Receiver part-to-part skew of the SN65MLVD040

The 238-MHz maximum operating speed calculated above was determined based on data and clock skews only.

Another important consideration when calculating the maximum operating speed is output transition time.

Transition-time-limited operating speed is calculated from Equation 2:

1

f + 45%

2 t_transition

(2)

Using the typical transition time of the SN65MLVD040 of 1.4 ns, a transition-time-limited operating frequency of

170 MHz can be supported.

In addition to the high operating frequencies of SSSC that can be ensured, the SN65MLVD040 presents other

benefits as other M-LVDS bus transceivers can provide:

•

Robust system operation due to common mode noise cancellation using a low voltage differential receiver

Low EMI radiation noise due to differential signaling improves signal integrity through the backplane

A singly terminated transmission line is easy to design and implement

Low power consumption in both active and idle modes minimizes thermal concerns on each module

In dense backplane design, these benefits are important for improving the performance of the whole system.

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LIVE INSERTION/GLITCH-FREE POWER UP/DOWN

The SN65MLVD040 family of products offered by Texas Instruments provides a glitch-free powerup/down feature

that prevents the M-LVDS outputs of the device from turning on during a powerup or powerdown event. This is

especially important in live insertion applications, when a device is physically connected to an M-LVDS multipoint

bus and V_CCis ramping.

While the M-LVDS interface for these devices is glitch free on powerup/down, the receiver output structure is not.

Figure 36 shows the performance of the receiver output pin, R (CHANNEL 2), as V_CC(CHANNEL 1) is ramped.

Figure 36. M-LVDS Receiver Output: V_CC(CHANNEL 1), R Pin (CHANNEL 2)

The glitch on the R pin is independent of the RE voltage. Any complications or issues from this glitch are

resolved in power sequencing or system requirements that suspend operation until V_CChas reached a steady

state value.

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PACKAGE OPTION ADDENDUM

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29-Mar-2010

PACKAGING INFORMATION

Orderable Device

SN65MLVD040RGZR

SN65MLVD040RGZT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

VQFN

RGZ

48

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

VQFN

RGZ

48

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

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TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

Medical

Security

Logic

Space, Avionics and Defense www.ti.com/space-avionics-defense

Power Mgmt

power.ti.com

Transportation and

Automotive

www.ti.com/automotive

Microcontrollers

RFID

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

Wireless

www.ti.com/video

www.ti.com/wireless-apps

RF/IF and ZigBee® Solutions www.ti.com/lprf

TI E2E Community Home Page

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	SN65MLVD040RGZT
厂家：	TEXAS INSTRUMENTS
描述：	4-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS 4通道半双工M- LVDS线路收发器
文件：	总29页 (文件大小：813K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN65MLVD040RGZT [TI]

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