SN65MLVD047AD [TI]
Multipoint-LVDS Quad Differential Line Driver 16-SOIC -40 to 85;
| 型号： | SN65MLVD047AD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Multipoint-LVDS Quad Differential Line Driver 16-SOIC -40 to 85 驱动器 |
| 文件： | 总17页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65MLVD047
www.ti.com
SLLS606A–MARCH 2004–REVISED JULY 2005
MULTIPOINT-LVDS QUAD DIFFERENTIAL LINE DRIVER
FEATURES
DESCRIPTION
•
Differential Line Drivers for 30-Ω to 55-Ω
Loads and Data Rates(1) Up to 200 Mbps,
Clock Frequencies up to 100 MHz
The SN65MLVD047 is a quadruple line driver. The
output current of this device has been increased, in
comparison to standard LVDS compliant devices, in
order to support doubly terminated transmission lines
and heavily loaded backplane bus applications.
Backplane applications generally require impedance
matching termination resistors at both ends of the
bus. The effective impedance of a doubly terminated
bus can be as low as 30 Ω due to the bus
terminations, as well as the capacitive load of bus
interface devices. SN65MLVD047 drivers allow for
operation with loads as low as 30 Ω. The
SN65MLVD047 devices allow for multiple drivers to
be present on a single bus. Driver edge rate control is
•
•
•
Supports Multipoint Bus Architectures
Operates from a Single 3.3-V Supply
Characterized for Operation from –40°C to
85°C
•
16-Pin SOIC (JEDEC MS-012) and 16-Pin
TSSOP (JEDEC MS-153) Packaging
APPLICATIONS
•
Clock Distribution
•
Backplane or Cabled Multipoint Data Trans-
mission in Telecommunications, Automotive,
Industrial, and Other Computer Systems
incorporated
to
support
operation.
The
SN65MLVD047 provides 9-kV ESD protection on all
bus pins.
•
•
•
•
Cellular Base Stations
Central-Office and PBX Switching
Bridges and Routers
Low-Power High-Speed Short-Reach Alterna-
tive to TIA/EIA-485(1)
(1) The data rate of a line is the number of voltage transitions that
are made per second expressed in the units bps (bits per
second).
LOGIC DIAGRAM (POSITIVE LOGIC)
EN
EN
1 Y
1 Z
1A
2A
2 Y
2 Z
3 Y
3 Z
3A
4A
4 Y
4 Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65MLVD047
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SLLS606A–MARCH 2004–REVISED JULY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER
SN65MLVD047D
PACKAGE MARKING
MLVD047
PACKAGE/CARRIER
16-Pin SOIC/Tube
SN65MLVD047DR
SN65MLVD047PW
SN65MLVD047PWR
MLVD047
16-Pin SOIC/Tape and Reel
16-Pin TSSOP/Tube
MLVD047
MLVD047
16-Pin TSSOP/Tape and Reel
PACKAGE DISSIPATION RATINGS
PCB JEDEC
PACKAGE
T
A ≤ 25°C
DERATING FACTOR
TA = 85°C
POWER RATING
STANDARD
POWER RATING
ABOVE TA = 25°C(1)
7.81 mW/°C
D(16)
Low-K(2)
Low-K(2)
High-K(3)
898 mW
429 mW
283 mw
452 mw
592 mW
5.15 mW/°C
PW(16)
945 mW
8.22 mW/°C
(1) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNITS
–0.5 V to 4 V
–0.5 V to 4 V
–1.8 V to 4 V
±9 kV
VCC Supply voltage range(2)
VI
Input voltage range
Output voltage range
A, EN, EN
Y, Z
VO
Y and Z
All pins
All pins
All pins
Human Body Model(3)
±4 kV
Electrostatic discharge
Charged-Device Model(4)
Machine Model(5)
±1500 V
200 V
TJ
Junction temperature
140°C
PD
Continuous power dissipation
See Dissipation Rating Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to the circuit ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101-A.
(5) Tested in accordance with JEDEC Standard 22, Test Method A115-A.
2
SN65MLVD047
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SLLS606A–MARCH 2004–REVISED JULY 2005
RECOMMENDED OPERATING CONDITIONS (see Figure 1)
MIN
3
NOM
MAX UNIT
VCC
VIH
VIL
Supply voltage
3.3
3.6
VCC
0.8
3.8
55
V
V
V
V
Ω
High-level input voltage
Low-level input voltage
2
0
Voltage at any bus terminal (separate or common mode) VY or VZ
Differential load resistance
Signaling rate
–1.4
30
RL
1/tUI
200 Mbps
Clock frequency
100
125
MHz
TJ
Junction temperature
–40
°C
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
Low-K board(1), no airflow
Low-K board(1), no airflow
Low-K board(1), 150 LFM
Low-K board(1), 250 LFM
High-K board(2), no airflow
MIN
TYP
MAX UNIT
D
128
194.2
146.8
133.1
121.6
51.1
θJA
Junction-to-ambient thermal resistance
°C/W
PW
D
θJB
Junction-to-board thermal resistance
High-K board(2)
°C/W
PW
D
85.3
45.4
θJC
Junction-to-case thermal resistance
Device power dissipation
°C/W
PW
34.7
EN = VCC, EN = GND, RL = 50 Ω, Input 100 MHz 50 %
duty cycle square wave to 1A:4A, TA = 85°C
PD
288.5 mW
(1) In accordance with the Low-K thermal metric difinitions of EIA/JESD51-3.
(2) In accordance with the High-K thermal metric difinitions of EIA/JESD51-7.
DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
Driver enabled EN = VCC, EN = GND, RL = 50 Ω, All inputs = VCC or GND
Driver disabled EN = GND, EN = VCC, RL = No load, All inputs = VCC or GND
TEST CONDITIONS
MIN(1) TYP(2)
MAX UNIT
59
2
70
mA
4
ICC Supply current
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25°C and with a 3.3-V supply voltage.
3
SN65MLVD047
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SLLS606A–MARCH 2004–REVISED JULY 2005
DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
LVTTL (EN, EN, 1A:4A)
TEST CONDITIONS
MIN(1) TYP(2)
MAX UNIT
|IIH
|
High-level input current
Low-level input current
Input capacitance
VIH = 2 V or VCC
0
0
5
10
10
µA
µA
pF
|IIL|
Ci
VIL = GND or 0.8 V
VI = 0.4 sin(30E6πt) + 0.5 V(3)
M-LVDS (1Y/1Z:4Y/4Z)
|VYZ
|
Differential output voltage magnitude
480
–50
0.8
650
50
mV
mV
V
See Figure 2
See Figure 3
Change in differential output voltage magnitude
between logic states
∆|VYZ
|
VOS(SS)
∆VOS(SS)
VOS(PP)
VY(OC)
Steady-state common-mode output voltage
1.2
50
Change in steady-state common-mode output
voltage between logic states
–50
mV
mV
V
Peak-to-peak common-mode output voltage
150
2.4
Maximum steady-state open-circuit output volt-
age
0
0
See Figure 7
Maximum steady-state open-circuit output volt-
age
VZ(OC)
2.4
V
VP(H)
VP(L)
Voltage overshoot, low-to-high level output
Voltage overshoot, high-to-low level output
1.2 VSS
V
V
See Figure 5
See Figure 4
–0.2 VSS
Differential short-circuit output current magni-
tude
|IOS
IOZ
IO(OFF)
|
24
10
10
mA
µA
µA
pF
pF
–1.4 V ≤ (VY or VZ) ≤ 3.8 V,
Other output = 1.2 V
High-impedance state output current
Power-off output current
–15
–10
–1.4 V ≤ (VY or VZ) ≤ 3.8 V,
Other output = 1.2 V, VCC = 0 V
VY or VZ = 0.4 sin(30E6πt) + 0.5 V,(3)
Other input at 1.2 V, driver disabled
VYZ = 0.4 sin(30E6πt) V,(3)
Driver disabled
CY or CZ Output capacitance
3
CYZ
Differential output capacitance
Output capacitance balance, (CY/CZ)
2.5
CY/Z
0.99
1.01
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25°C and with a 3.3-V supply voltage.
(3) HP4194A impedance analyzer (or equivalent)
4
SN65MLVD047
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SLLS606A–MARCH 2004–REVISED JULY 2005
SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
Differential output signal fall time
Output skew
1
1
1
1
1.5
1.5
2.4
2.4
1.9
1.9
100
100
600
1
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
tf
See Figure 5
tsk(o)
tsk(p)
tsk(pp)
tjit(per)
tjit(c-c)
tjit(pp)
tPZH
tPZL
tPHZ
tPLZ
Pulse skew (|tpHL - tpLH|)
Part-to-part skew(2)
Period jitter, rms (1 standard deviation)(3)
Cycle-to-cycle jitter(3)
Peak-to-peak jitter(3)(4)
22
All inputs 100 MHz clock input
All inputs 100 MHz clock input
All inputs 200 Mbps 215-1 PRBS input
0.2
5
36
158
7
46
Enable time, high-impedance-to-high-level output
Enable time, high-impedance-to-low-level output
Disable time, high-level-to-high-impedance output
Disable time, low-level-to-high-impedance output
See Figure 6
See Figure 6
7
8
8
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) Stimulus jitter has been subtracted from the measurements.
(4) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
5
SN65MLVD047
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SLLS606A–MARCH 2004–REVISED JULY 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
I
Y
Y
Z
I
I
D
V
YZ
I
Z
V
Y
V
I
V
OS
V
Z
V
Y
+ V
2
Z
Figure 1. Driver Voltage and Current Definitions
3.32 kΩ
Y
+
-1 V ≤ V
≤ 3.4 V
V
YZ
49.9 Ω
D
test
_
Z
3.32 kΩ
NOTE: All resistors are 1% tolerance.
Figure 2. Differential Output Voltage Test Circuit
Y
Z
R1
≈ 1.3 V
≈ 0.7 V
24.9 Ω
Y
Z
C1
1 pF
D
V
nV
OS(SS)
OS(PP)
V
OS
C3
2.5 pF
R2
24.9 Ω
V
OS(SS)
C2
1 pF
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse frequency = 500
kHz, duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 3. Test Circuit and Definitions for the Common-Mode Output Voltage
I
OS
Y
Z
0 V or V
CC
+
V
-
-1 V to 3.4 V
Test
Figure 4. Short-Circuit Test Circuit
6
SN65MLVD047
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SLLS606A–MARCH 2004–REVISED JULY 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Y
C1
1 pF
C3
0.5 pF
R1
50 Ω
Output
D
Z
C2
1 pF
V
V
CC
/2
CC
Input
0 V
t
pLH
t
pHL
V
SS
0.9V
V
P(H)
SS
Output
0 V
V
P(L)
0.1V
SS
0 V
SS
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 500 kHz,
duty cycle = 50 ± 5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
R1
24.9 Ω
Y
C1
1 pF
D
C4
0.5 pF
0 V or V
Output
CC
C3
2.5 pF
C2
1 pF
Z
R2
24.9 Ω
Input
EN or EN
EN
V
V
CC
/2
CC
EN
0 V
t
t
t
pZH
pHZ
0.6 V
0.1 V
Output With
0 V
D at V
CC
t
pZL
pLZ
Output With
D at 0 V
0 V
-0.1 V
-0.6 V
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 500 kHz,
duty cycle = 50 ± 5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 6. Driver Enable and Disable Time Circuit and Definitions
7
SN65MLVD047
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SLLS606A–MARCH 2004–REVISED JULY 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Y
0 V or V
CC
Z
V , or V
Y
1.62 kΩ , ±1%
Z
Figure 7. Driver Maximum Steady State Output Voltage
V
V
CC
CLOCK
INPUT
/2
CC
0 V
1/f0
Period Jitter
IDEAL
OUTPUT
V
V
CC
0 V
PRBS INPUT
/2
CC
V
Y
-V
Z
1/f0
0 V
ACTUAL
OUTPUT
Peak to Peak Jitter
0 V
V
V
-V
Z
Y
V
Y
-V
Z
OUTPUT
0 V
t
c(n)
-V
Z
t
=
t
-1/f0
Y
jit(per)
c(n)
t
jit(pp)
Cycle to Cycle Jitter
OUTPUT
0 V
V
Y
- V
Z
t
t
c(n+1)
c(n)
t
= | t
- t
|
jit(cc)
c(n) c(n+1)
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50 ±1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 200 Mbps 215– 1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
8
SN65MLVD047
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SLLS606A–MARCH 2004–REVISED JULY 2005
DEVICE INFORMATION
PIN ASSIGNMENTS
D PACKAGE
(TOP VIEW)
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN
1A
2A
VCC
GND
3A
1Z
EN
1A
2A
VCC
GND
3A
1Z
1Y
2Y
2Z
3Z
3Y
4Y
4Z
15
14
13
12
11
10
9
1Y
2Y
2Z
3Z
3Y
4Y
4Z
4A
EN
4A
EN
DEVICE FUNCTION TABLE
INPUTS(1)
OUTPUTS(1)
D
EN
H
EN
Y
L
Z
L
H
L
H
L
H
L
H
L
OPEN
X
H
L
X
H
Z
Z
L or OPEN
X
Z
Z
X
H or OPEN
(1) H = high level, L = low level, Z = high impedance, X = Don't Care
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
DRIVER OUTPUT
DRIVER INPUT AND POSITIVE DRIVER ENABLE
NEGATIVE DRIVER ENABLE
V
CC
V
CC
V
CC
360 kΩ
400 Ω
400 Ω
D or EN
7 V
Y or Z
EN
7 V
360 kΩ
9
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SLLS606A–MARCH 2004–REVISED JULY 2005
TYPICAL CHARACTERISTICS
RMS SUPPLY CURRENT
RMS SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
vs
INPUT FREQUENCY
80
75
70
65
60
55
50
65
V
T
= 3.3 V,
V
= 3.3 V,
CC
CC
= 255C,
f = 50 MHz,
EN = V
A
EN = V
,
,
CC
CC
EN = GND,
= 50 W,
64
63
62
61
60
EN = GND,
= 50 W
R
R
L
L
All Inputs
25
50
75
100
125
−40
−15
10
35
60
85
f − Input Frequency − MHz
T
A
− Free-Air Temperature − °C
Figure 9.
Figure 10.
DIFFERENTIAL OUTPUT VOLTAGE MAGNITUDE
DRIVER PROPAGATION DELAY TIME
vs
vs
INPUT FREQUENCY
FREE-AIR TEMPERATURE
600
580
560
540
520
500
1.54
T
R
= 255C,
= 50 W
V
= 3.3 V,
A
CC
f = 500 kHz,
= 50 W
V
= 3.6 V
L
1.52
1.5
CC
t
PHL
R
L
V
CC
= 3.3 V
t
1.48
1.46
1.44
1.42
1.4
PLH
V
CC
= 3 V
1.38
1.36
1.34
25
50
75
100
125
−40
−15
10
35
60
85
f − Input Frequency − MHz
T
A
− Free-Air Temperature − °C
Figure 11.
Figure 12.
10
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SLLS606A–MARCH 2004–REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
DRIVER TRANSITION TIME
vs
FREE-AIR TEMPERATURE
PEAK-TO-PEAK JITTER
vs
DATA RATE
100
90
80
70
60
50
40
30
20
10
1.8
V
= 3.3 V,
V
T
= 3.3 V,
= 255C,
CC
CC
f = 500 kHz,
= 50 W
A
15
R
All Inputs = 2 −1 PRBS NRZ,
(See Figure 8)
L
1.7
1.6
1.5
1.4
1.3
1.2
t
f
t
r
−40
−15
10
35
60
85
50
100
150
200
250
T
A
− Free-Air Temperature − °C
Data Rate − Mbps
Figure 13.
Figure 14.
PERIOD JITTER
vs
CLOCK FREQUENCY
CYCLE-TO-CYCLE JITTER
vs
CLOCK FREQUENCY
10
9
8
7
6
5
4
3
2
1
0
1
V
= 3.3 V,
= 255C,
V
T
= 3.3 V,
= 255C,
CC
CC
T
0.9
0.8
0.7
A
A
All Inputs = Clock
(See Figure 8)
All Inputs = Clock
(See Figure 8)
0.6
0.5
0.4
0.3
0.2
0.1
0
25
50
75
100
125
25
50
75
100
125
f − Clock Frequency − MHz
f − Clock Frequency − MHz
Figure 15.
Figure 16.
11
SN65MLVD047
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SLLS606A–MARCH 2004–REVISED JULY 2005
APPLICATION INFORMATION
Multipoint Configuration
The SN65MLVD047 is designed to allow multipoint communication on a shared bus.
Multipoint is a bus configuration with multiple drivers and receivers present. An example is shown in Figure 17.
The figure shows transceivers interfacing to the bus, but a combination of drivers, receivers, and transceivers is
also possible. Termination resistors need to be placed on each end of the bus, with the termination resistor value
matched to the loaded bus impedance.
Figure 17. Multipoint Architecture
Multidrop Configuration
Multidrop configuration is similar to multipoint configuration, but only one driver is present on the bus. A multidrop
system can be configured with the driver at one end of the bus, or in the middle of the bus. When a driver is
located at one end, a single termination resistor is located at the far end, close to the last receiver on the bus.
Alternatively, the driver can be located in the middle of the bus, to reduce the maximum flight time. With a
centrally located driver, termination resistors are located at each end of the bus. In both cases the termination
resistor value should be matched to the loaded bus impedance. Figure 18 shows examples of both cases.
D
Z
t
Z
t
Z
t
D
Figure 18. Multidrop Architectures With Different Driver Locations
Unused Channel
The SN65MLVD047 is designed to allow multipoint communication on a standard bus. A 360-kΩ pull-down
resistor is built in every LVTTL input. The unused driver inputs and outputs may be left floating.
Live Insertion/Glitch Free Power Up/Down
During a live insertion event or a power cycle the outputs of the SN65MLVD047 leave the high impedance state
and possibly glitch the bus. Specifically when the VCC applied to the device is between 1.3 and 2.0 VDC the
output state (high or low) of the device reflects the input level at the corresponding A pin.
12
SN65MLVD047
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SLLS606A–MARCH 2004–REVISED JULY 2005
APPLICATION INFORMATION (continued)
Note: Channel 1: VCC, Channel 2: Differential Bus
Voltage
The output state of the part during this voltage range is independent of the EN and EN pins.
In order to insure that data is not corrupted during a live insertion event or the power cycling of an individual
node on a multipoint bus it is important to isolate the outputs of the device from the bus until the VCC has
reached at least 2.0 VDC. At this voltage level the device output state accurately reflects the logic conditions as
defined in the Device Function Table.
13
PACKAGE OPTION ADDENDUM
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6-Dec-2006
PACKAGING INFORMATION
Orderable Device
SN65MLVD047D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65MLVD047DG4
SN65MLVD047DR
SN65MLVD047DRG4
SN65MLVD047PW
SN65MLVD047PWG4
SN65MLVD047PWR
SN65MLVD047PWRG4
SOIC
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Use of such information may require a license from a third party under the patents or other intellectual property
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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
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is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
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Amplifiers
amplifier.ti.com
www.ti.com/audio
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dataconverter.ti.com
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www.ti.com/automotive
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dsp.ti.com
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Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
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Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
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Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2006, Texas Instruments Incorporated
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