SN65MLVD047APWG4_技术文档

SN65MLVD047A

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SLLS736A − JULY 2006 − REVISED MAY 2008

MULTIPOINT-LVDS QUAD DIFFERENTIAL LINE DRIVER

FEATURES

DESCRIPTION

D

Differential Line Drivers for 30-Ω to 55-Ω

Loads and Data Rates Up to 200 Mbps,

Clock Frequencies up to 100 MHz

The SN65MLVD047A is a quadruple line driver that

complies with the TIA/EIA-899 standard, Electrical

Characteristics of Multipoint-Low-Voltage Differential

Signaling (M−LVDS). The output current of this M−LVDS

device has been increased, in comparison to standard

LVDS compliant devices, in order to support doubly

terminated transmission lines and heavily loaded

backplane bus applications. Backplane applications

generally require impedance matching termination

resistors at both ends of the bus. The effective impedance

of a doubly terminated bus can be as low as 30 Ω due to

the bus terminations, as well as the capacitive load of bus

interface devices. SN65MLVD047A drivers allow for

operation with loads as low as 30 Ω. The SN65MLVD047A

devices allow for multiple drivers to be present on a single

bus. SN65MLVD047A drivers are high impedance when

disabled or unpowered. Driver edge rate control is

incorporated to support operation. The M−LVDS standard

allows up to 32 nodes (drivers and/or receivers) to be

connected to the same media in a backplane when

multiple bus stubs are expected from the main

(1)

D

Supports Multipoint Bus Architectures

Meets the Requirements of TIA/EIA-899

Operates from a Single 3.3-V Supply

Characterized for Operation from −405C to

855C

D

16-Pin SOIC (JEDEC MS-012) and 16-Pin

TSSOP (JEDEC MS-153) Packaging

APPLICATIONS

D

AdvancedTCAE (ATCAE) Clock Bus Driver

Clock Distribution

Backplane or Cabled Multipoint Data

Transmission in Telecommunications,

Automotive, Industrial, and Other Computer

Systems

transmission

line

to

interface

devices.

The

D

Cellular Base Stations

SN65MLVD047A provides 9-kV ESD protection on all bus

pins.

Central-Office and PBX Switching

Bridges and Routers

Low-Power High-Speed Short-Reach

Alternative to TIA/EIA-485

LOGIC DIAGRAM (POSITIVE LOGIC)

EN

1 Y

1 Z

1A

2A

2 Y

2 Z

3 Y

3 Z

3A

4A

4 Y

4 Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

(1)

The data rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

AdvancedTCA and ATCA are trademarks of the PCI Industrial Computer Manufacturers Group.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

SN65MLVD047A

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SLLS736A − JULY 2006 − REVISED MAY 2008

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PART NUMBER

PACKAGE MARKING

MLVD047A

BUL

PACKAGE/CARRIER

16-Pin SOIC/Tube

SN65MLVD047AD

SM65MLVD047ADR

SN65MLVD047APW

SM65MLVD047APWR

16-Pin SOIC/Tape and Reel

16-Pin TSSOP/Tube

BUL

16-Pin TSSOP/Tape and Reel

:

NOTE For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website

at www.ti.com.

PACKAGE DISSIPATION RATINGS

PCB JEDEC

STANDARD

T

≤ 25°C

DERATING FACTOR

T = 85°C

POWER RATING

A

PACKAGE

(1)

POWER RATING

ABOVE T = 25°C

A

(2)

D(16)

Low-K

898 mW

7.81 mW/_C

5.15 mW/_C

8.22 mW/_C

429 mW

(2)

Low-K

592 mW

283 mw

PW(16)

(3)

High-K

945 mW

452 mw

(1)

(2)

(3)

This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.

In accordance with the Low-K thermal metric difinitions of EIA/JESD51−3.

In accordance with the High-K thermal metric difinitions of EIA/JESD51−7.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

UNITS

−0.5 V to 4 V

−1.8 V to 4 V

±9 kV

(2)

Supply voltage range , V

CC

Input voltage range, V

A, EN, EN

I

Output voltage range, V

Y, Z

O

Y and Z

All pins

(3)

Human Body Model

±4 kV

Electrostatic discharge

Junction temperature, T

(4)

Charged-Device Model

±1500 V

200 V

(5)

Machine Model

140°C

J

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltage values, except differential I/O bus voltages, are with respect to the circuit ground terminal.

Tested in accordance with JEDEC Standard 22, Test Method A114−B.

(2)

(3)

(4)

(5)

Tested in accordance with JEDEC Standard 22, Test Method C101−A.

Tested in accordance with JEDEC Standard 22, Test Method A115−A.

2

SN65MLVD047A

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SLLS736A − JULY 2006 − REVISED MAY 2008

RECOMMENDED OPERATING CONDITIONS (see Figure 1)

MIN NOM

MAX UNIT

Supply voltage, V

3

2

3.3

3.6

V

Ω

CC

High-level input voltage, V

V

CC

IH

Low-level input voltage, V

0

0.8

IL

Voltage at any bus terminal (separate or common mode) V or V

−1.4

30

3.8

55

Y

Z

Differential load resistance, R

L

Signaling rate, 1/t

200 Mbps

100 MHz

UI

Clock frequency, f

Junction temperature, T

−40

125

°C

J

THERMAL CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

Low-K board , no airflow

D

128

194.2

146.8

133.1

121.6

51.1

(1)

Low-K board , no airflow

(1)

Low-K board , 150 LFM

Junction-to-ambient thermal resistance, Θ

°C/W

JA

PW

(1)

Low-K board , 250 LFM

(2)

High-K board , no airflow

D

(2)

Junction-to-board thermal resistance, Θ

High-K board

°C/W

JB

PW

D

85.3

45.4

Junction-to-case thermal resistance, Θ

JC

PW

34.7

EN = V , EN = GND, R = 50 Ω,

CC

L

Device power dissipation, P

Input 100 MHz 50 % duty cycle square wave to

all data inputs, T = 85°C

288.5

mW

D

A

(1)

(2)

In accordance with the Low-K thermal metric difinitions of EIA/JESD51−3.

In accordance with the High-K thermal metric difinitions of EIA/JESD51−7.

ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted

(1)

PARAMETER

TEST CONDITIONS

EN = V , EN = GND, R = 50 Ω, All data inputs = V or

MIN TYP

MAX

UNIT

CC

L

CC

Driver enabled

Driver disabled

59

70

GND

EN = GND, EN = V , R = No load, All data inputs = V

CC

I

Supply current

mA

CC

L

2

4

or GND

(1)

All typical values are at 25°C and with a 3.3-V supply voltage.

3

SN65MLVD047A

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SLLS736A − JULY 2006 − REVISED MAY 2008

ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted

(1)

(2)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVTTL (EN, EN, 1A:4A)

|I

|

0

10

µA

pF

High-level input current

Low-level input current

Input capacitance

V

= 2 V or V

IH

CC

|I |

= GND or 0.8 V

IL

(3)

C

5

V = 0.4 sin(30E6πt) + 0.5 V

I

i

M−LVDS (1Y/1Z:4Y/4Z)

⎪V

⎪

480

−50

0.8

650

50

mV

V

Differential output voltage magnitude

YZ

See Figure 2

See Figure 3

Change in differential output voltage magnitude

between logic states

∆⎪V

⎪

YZ

V

1.2

50

Steady-state common-mode output voltage

OS(SS)

Change in steady-state common-mode output

voltage between logic states

∆V

−50

mV

V

OS(SS)

OS(PP)

Y(OC)

V

150

2.4

Peak-to-peak common-mode output voltage

Maximum steady-state open-circuit output

voltage

0

See Figure 7

See Figure 5

Maximum steady-state open-circuit output

voltage

V

Z(OC)

2.4

V

⎪I

1.2 V

V

Voltage overshoot, low-to-high level output

Voltage overshoot, high-to-low level output

P(H)

SS

−0.2 V

P(L)

SS

⎪

24

10

mA

Differential short-circuit output current magnitude See Figure 4

OS

−1.4 V ≤ (V or V ) ≤ 3.8 V,

Y

Z

I

−15

−10

µA

High-impedance state output current

OZ

Other output = 1.2 V

−1.4 V ≤ (V or V ) ≤ 3.8 V,

Y

Z

I

10

µA

Power-off output current

Other output = 1.2 V,

= 1.5 V

O(OFF)

V

CC

V or V = 0.4 sin(30E6πt) +

Y

Z

(3)

0.5 V,

C

or C

3

pF

Output capacitance

Y

Z

Other outputs at 1.2 V, driver

disabled

(3)

V

YZ

= 0.4 sin(30E6πt) V,

C

2.5

Differential output capacitance

YZ

Driver disabled

0.99

1.01

Output capacitance balance, (C /C )

Y/Z

Y

Z

(1)

The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

All typical values are at 25°C and with a 3.3-V supply voltage.

HP4194A impedance analyzer (or equivalent)

(2)

(3)

4

SN65MLVD047A

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SLLS736A − JULY 2006 − REVISED MAY 2008

SWITCHING CHARACTERISTICS

over recommended operating conditions unless otherwise noted

(1)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

2.4

UNIT

ns

t

1

1.5

Propagation delay time, low-to-high-level output

Propagation delay time, high-to-low-level output

Differential output signal rise time

pLH

pHL

r

1.5

2.4

ns

1.9

ns

1.9

ns

Differential output signal fall time

See Figure 5

f

(2)

100

600

ps

Output skew

sk(o)

sk(p)

sk(pp)

22

ps

Pulse skew (|t

− t |)

pLH

pHL

(3)

ps

Part-to-part skew

See Figure 8, All data inputs 100 MHz

clock input

(4)

t

0.2

5

1

36

ps

Period jitter, rms (1 standard deviation)

jit(per)

jit(c−c)

jit(pp)

See Figure 8, All data inputs 100 MHz

clock input

(4)

Cycle-to-cycle jitter

See Figure 8, All data inputs 200 Mbps

(3)(5)

46

158

Peak-to-peak jitter

15

2

−1 PRBS input

t

9

ns

Enable time, high-impedance-to-high-level output

Enable time, high-impedance-to-low-level output

Disable time, high-level-to-high-impedance output

pZH

pZL

pHZ

pLZ

See Figure 6

10

Disable time, low-level-to-high-impedance output

(1)

(2)

(3)

All typical values are at 25°C and with a 3.3-V supply voltage.

t

, output skew is the magnitude of the time difference in propagation delay times between any specified terminals of a device.

sk(o)

is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate

sk(pp)

with the same supply voltages, at the same temperature, and have identical packages and test circuits.

Stimulus jitter has been subtracted from the measurements.

(4)

(5)

Peak-to-peak jitter includes jitter due to pulse skew (t

).

sk(p)

5

SN65MLVD047A

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SLLS736A − JULY 2006 − REVISED MAY 2008

PARAMETER MEASUREMENT INFORMATION

V

CC

I

Y

Z

I

D

V

YZ

I

Z

V

Y

V

I

V

OS

V

Z

V

Y

+ V

2

Z

Figure 1. Driver Voltage and Current Definitions

3.32 kΩ

Y

+

−1 V ≤ V

≤ 3.4 V

V

YZ

49.9 Ω

D

test

_

Z

3.32 kΩ

:

NOTE All resistors are 1% tolerance.

Figure 2. Differential Output Voltage Test Circuit

Y

Z

R1

24.9 Ω

≈ 1.3 V

≈ 0.7 V

Y

C1

1 pF

D

V

nV

OS(SS)

OS(PP)

V

OS

Z

C3

2.5 pF

R2

24.9 Ω

V

OS(SS)

C2

1 pF

NOTES:A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse frequency = 500 kHz,

r

f

duty cycle = 50 ± 5%.

B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.

C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.

D. The measurement of V

is made on test equipment with a −3 dB bandwidth of at least 1 GHz.

OS(PP)

Figure 3. Test Circuit and Definitions for the Common-Mode Output Voltage

I

OS

Y

Z

0 V or V

CC

+

V

−

−1 V to 3.4 V

Test

Figure 4. Short-Circuit Test Circuit

6

SN65MLVD047A

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SLLS736A − JULY 2006 − REVISED MAY 2008

Y

Z

C1

1 pF

C3

0.5 pF

R1

50 Ω

Output

D

C2

1 pF

V

CC

/2

CC

Input

0 V

t

pLH

t

pHL

V

SS

0.9V

V

P(H)

SS

Output

0 V

V

P(L)

0.1V

SS

0 V

SS

t

f

t

r

NOTES:A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, frequency = 500 kHz,

r

f

duty cycle = 50 ± 5%.

B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.

C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.

D. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.

Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal

R1

24.9 Ω

Y

C1

1 pF

D

C4

0.5 pF

0 V or V

Output

CC

C3

2.5 pF

C2

1 pF

Z

R2

24.9 Ω

Input

EN or EN

EN

V

CC

V

CC

/2

EN

0 V

t

pZH

pHZ

∼ 0.6 V

0.1 V

Output With

0 V

D at V

CC

t

pZL

pLZ

Output With

D at 0 V

0 V

−0.1 V

∼ −0.6 V

NOTES:A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, frequency = 500 kHz, duty cycle = 50 ±

r

f

5%.

B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.

C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.

D. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.

Figure 6. Driver Enable and Disable Time Circuit and Definitions

7

SN65MLVD047A

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SLLS736A − JULY 2006 − REVISED MAY 2008

Y

Z

0 V or V

CC

V , or V

Y

1.62 kΩ , ±1%

Z

Figure 7. Driver Maximum Steady State Output Voltage

V

CC

CLOCK

INPUT

/2

CC

0 V

1/f0

Period Jitter

IDEAL

OUTPUT

V

CC

0 V

PRBS INPUT

/2

CC

V

Y

−V

Z

1/f0

0 V

ACTUAL

OUTPUT

Peak to Peak Jitter

0 V

V

−V

Z

Y

V

Y

−V

Z

OUTPUT

0 V

t

c(n)

= ⎮t

−V

Z

t

−1/f0⎮

c(n)

Y

jit(per)

t

jit(pp)

Cycle to Cycle Jitter

OUTPUT

0 V

V − V

Y

Z

t

|

c(n)

c(n+1)

t

= | t

− t

jit(cc)

c(n) c(n+1)

NOTES:A. All input pulses are supplied by an Agilent 8304A Stimulus System.

B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software

C. Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50 ±1% duty cycle clock input.

15

D. Peak-to-peak jitter is measured using a 200 Mbps 2 −1 PRBS input.

Figure 8. Driver Jitter Measurement Waveforms

8

SN65MLVD047A

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SLLS736A − JULY 2006 − REVISED MAY 2008

DEVICE INFORMATION

PIN ASSIGNMENTS

D PACKAGE

(TOP VIEW)

PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

EN

1A

2A

VCC

GND

3A

1Z

1Y

2Y

2Z

3Z

3Y

4Y

4Z

EN

1A

2A

VCC

GND

3A

1Z

1Y

2Y

2Z

3Z

3Y

4Y

4Z

15

14

13

12

11

10

9

4A

EN

4A

EN

DEVICE FUNCTION TABLE

INPUTS

EN

OUTPUTS

D

EN

Y

Z

L

H

OPEN

X

H

L

X

L

H

L

Z

H

L

H

Z

H

L or OPEN

X

H or OPEN

H = high level, L = low level, Z = high impedance, X = Don’t care

EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

DRIVER INPUT AND ACTIVE−HIGH ENABLE

DRIVER OUTPUT

ACTIVE−LOW ENABLE

V

CC

V

CC

V

CC

_

10 mA

1 mA

+

360 kΩ

400 Ω

D or EN

7 V

EN

7 V

Y or Z

360 kΩ

+

_

0.2 V

_

+

10 mA

9

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SLLS736A − JULY 2006 − REVISED MAY 2008

TYPICAL CHARACTERISTICS

RMS SUPPLY CURRENT

vs

INPUT FREQUENCY

FREE-AIR TEMPERATURE

80

75

70

65

60

55

50

65

V

= 3.3 V,

V

= 3.3 V,

CC

f = 50 MHz,

EN = V

EN = GND,

T = 255C,

A

,

EN = V

,

CC

64

63

62

61

60

EN = GND,

R = 50 W,

All Inputs

R = 50 W

L

−40

−15

10

35

60

85

25

50

75

100

125

T − Free-Air Temperature − °C

A

f − Input Frequency − MHz

Figure 9

Figure 10

DRIVER PROPAGATION DELAY TIME

DIFFERENTIAL OUTPUT VOLTAGE MAGNITUDE

vs

FREE-AIR TEMPERATURE

INPUT FREQUENCY

600

1.54

T = 255C,

A

V

CC

= 3.3 V,

R = 50 W

L

V

= 3.6 V

f = 500 kHz,

R = 50 W

CC

1.52

1.5

t

PHL

L

V

CC

= 3.3 V

580

560

540

520

500

t

1.48

1.46

1.44

1.42

1.4

PLH

V

CC

= 3 V

1.38

1.36

1.34

25

50

75

100

125

−40

−15

10

35

60

85

f − Input Frequency − MHz

T − Free-Air Temperature − °C

A

Figure 12

Figure 11

10

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TYPICAL CHARACTERISTICS

DRIVER TRANSITION TIME

PEAK-TO-PEAK JITTER

vs

FREE-AIR TEMPERATURE

DATA RATE

100

90

80

70

60

50

40

30

20

10

1.8

V

= 3.3 V,

CC

T = 255C,

f = 500 kHz,

R = 50 W

A

15

All Inputs = 2 −1 PRBS NRZ,

(See Figure 8)

L

1.7

1.6

1.5

1.4

1.3

1.2

t

f

t

r

−40

−15

10

35

60

85

50

100

150

200

250

T − Free-Air Temperature − °C

A

Data Rate − Mbps

Figure 13

Figure 14

PERIOD JITTER

vs

CYCLE-TO-CYCLE JITTER

vs

CLOCK FREQUENCY

10

9

8

7

6

5

4

3

2

1

0

1

0.9

0.8

V

= 3.3 V,

V

= 3.3 V,

CC

T = 255C,

A

All Inputs = Clock

(See Figure 8)

All Inputs = Clock

(See Figure 8)

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

25

50

75

100

125

25

50

75

100

125

f − Clock Frequency − MHz

Figure 15

Figure 16

11

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APPLICATION INFORMATION

SYNCHRONIZATION CLOCK IN ADVANCEDTCA

Advanced Telecommunications Computing Architecture, also known as AdvancedTCA, is an open architecture to meet

the needs of the rapidly changing communications network infrastructure. M−LVDS bused clocking is recommended by

the ATCA.

The ATCA specification includes requirements for three redundant clock signals. An 8-KHz and a 19.44-MHz clock signal,

as well as an user-defined clock signal are included in the specification. The SN65MLVD047A quad driver supports

distribution of these three ATCA clock signals, supporting operation beyond 100 MHz, which is the highest clock frequency

included in the ATCA specification. A pair of SN65MLVD047A devices can be used to support the ATCA redundancy

requirements.

MULTIPOINT CONFIGURATION

The SN65MLVD047A is designed to meet or exceed the requirement of the TIA/EIA−899 (M−LVDS) standard, which allows

multipoint communication on a shared bus.

Multipoint is a bus configuration with multiple drivers and receivers present. An example is shown in Figure 17. The figure

shows transceivers interfacing to the bus, but a combination of drivers, receivers, and transceivers is also possible.

Termination resistors need to be placed on each end of the bus, with the termination resistor value matched to the loaded

bus impedance.

Z

t

Z

t

Figure 17. Multipoint Architecture

MULTIDROP CONFIGURATION

Multidrop configuration is similar to multipoint configuration, but only one driver is present on the bus. A multidrop system

can be configured with the driver at one end of the bus, or in the middle of the bus. When a driver is located at one end,

a single termination resistor is located at the far end, close to the last receiver on the bus. Alternatively, the driver can be

located in the middle of the bus, to reduce the maximum flight time. With a centrally located driver, termination resistors

are located at each end of the bus. In both cases the termination resistor value should be matched to the loaded bus

impedance. Figure 18 shows examples of both cases.

12

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D

Z

t

Z

t

Z

t

Z

t

D

Figure 18. Multidrop Architectures With Different Driver Locations

UNUSED CHANNEL

A 360−kΩ pull−down resistor is built in every LVTTL input. The unused driver inputs should be left floating or connected

to ground. The low−level output of an unused enabled driver may oscillate if left floating and should be connected to ground.

If the input is floating or connected to ground, the unused Y (non−inverting) output of an enabled driver should be connected

to ground. The unused Z (inverting) should be left floating.

13

PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

PACKAGING INFORMATION

Orderable Device

SN65MLVD047AD

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

16

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN65MLVD047ADG4

SN65MLVD047ADR

SN65MLVD047ADRG4

SN65MLVD047APW

SN65MLVD047APWG4

SN65MLVD047APWR

SN65MLVD047APWRG4

SOIC

D

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

PW

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN65MLVD047ADR

SN65MLVD047APWR

SOIC

D

16

2500

2000

330.0

16.4

12.4

6.5

6.9

10.3

5.6

2.1

1.6

8.0

16.0

12.0

Q1

TSSOP

PW

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN65MLVD047ADR

SN65MLVD047APWR

SOIC

D

16

2500

2000

367.0

38.0

35.0

TSSOP

PW

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	SN65MLVD047APWG4
厂家：	TEXAS INSTRUMENTS
描述：	Multipoint-LVDS Quad Differential Line Driver 16-TSSOP -40 to 85 驱动光电二极管接口集成电路驱动器
文件：	总21页 (文件大小：651K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN65MLVD047APWG4 [TI]

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