SN65MLVD128DGGR [TI]
1:8 LVTTL 到 M-LVDS 中继器 | DGG | 48 | -40 to 85;
| 型号： | SN65MLVD128DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1:8 LVTTL 到 M-LVDS 中继器 | DGG | 48 | -40 to 85 驱动 中继器 光电二极管 接口集成电路 驱动器 |
| 文件： | 总16页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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D
D
Independent Enables for each Driver
FEATURES
Output-to-Ouput Skew t
3 160 ps
sk(o)
3 800 ps
D
LVTTL Receiver and Eight Line Drivers
Configured as an 8-Port M-LVDS Repeater −
SN65MLVD128
Part-to-Part Skew t
sk(pp)
D
D
D
Single 3.3-V Voltage Supply
D
2 LVTTL Receivers and Eight Line Drivers
Configured as Dual 4-Port M-LVDS Repeaters
− SN65MLVD129
Bus Pin ESD Protection Exceeds 9 kV
Packaged in 48-Pin TSSOP (DGG)
D
D
Drivers Meet or Exceed the M-LVDS Standard
(TIA/EIA-899)
APPLICATIONS
Low-Voltage Differential 30-Ω to 55-Ω Line
Drivers for Data Rates Up to 250 Mbps or
Clock Frequencies Up to 125 MHz
D
D
D
AdvancedTCAE (ATCAE) Clock Bus Driver
(1)
Clock Distribution
Data and Clock Repeating Over Backplanes
and Cables
D
D
Power Up/Down Glitch Free
Controlled Driver Output Voltage Transition
Times for Improved Signal Quality
D
D
D
Cellular Base Stations
Central Office Switches
Network Switches and Routers
D
Bus Pins High Impedance When Disabled or
V
≤ 1.5 V
CC
LOGIC DIAGRAM
EN1
EN1
1A
1B
1A
1B
EN2
EN3
EN4
EN2
2A
2B
2A
2B
1 D
EN3
3A
3B
3A
3B
EN4
EN5
EN6
4A
4B
4A
4B
1D
EN5
5A
5B
5A
5B
EN6
EN7
EN8
6A
6B
6A
6B
2 D
EN7
7A
7B
7A
7B
EN8
8A
8B
8A
8B
SN65MLVD128
SN65MLVD129
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
(1)
The data rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
AdvancedTCA and ATCA are trademarks of the PCI Industrial Computer Manufacturers Group.
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Copyright 2004, Texas Instruments Incorporated
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SLLS586 − MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The SN65MLVD128 and SN65MLVD129 are LVTTL-to-M−LVDS translators/repeaters. Outputs comply with the M−LVDS
standard (TIA/EIA-899) and are optimized for data rates up to 250 Mbps, and clock frequencies up to 125 MHz. The driver
outputs have been designed to support multipoint buses presenting loads as low as 30 Ω and incorporates controlled
transition times for backbone operation.
M-LVDS compliant devices allow for 32 nodes on a common bus, providing a high-speed replacement for RS-485 devices
when lower common-mode voltage range and lower output signaling levels are acceptable. The SN65MLVD128 and
SN65MLVD129 provide separate driver enables, allowing for independent control of each output signal.
Intended applications for these devices include transmission of clock signals from a central clock module, as well as
translation and buffering of data or control signals for transmission through a controlled impedance backplane or cable.
ORDERING INFORMATION
INPUT:OUTPUT
CHANNEL
PART NUMBER
PART MARKING
PACKAGE/CARRIER
SN65MLVD128DGG
SM65MLVD128DGGR
SN65MLVD129DGG
SM65MLVD129DGGR
1:8
MLVD128
MLVD128
MLVD129
MLVD129
48-Pin TSSOP/Tube
48-Pin TSSOP/Tape and Reeled
48-Pin TSSOP/Tube
1:8
Dual 1:4
Dual 1:4
48-Pin TSSOP/Tape and Reeled
PACKAGE DISSIPATION RATINGS
(1)
PCB JEDEC
T
≤ 25°C
DERATING FACTOR
T = 85°C
A
POWER RATING
A
PACKAGE
STANDARD
POWER RATING
ABOVE T = 25°C
A
(2)
48-DGG
48-DGG
Low-K
1114.6 mW
9.7 mW/_C
533.1 mW
(3)
High-K
1824.5 mW
15.9 mW/_C
872.6 mw
(1)
(2)
(3)
This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
SN65MLVD128, 129
−0.5 V to 4 V
−0.5 V to 4 V
−1.8 V to 4 V
9 kV
(2)
Supply voltage range , V
CC
Input voltage range, V
D, EN
I
Output voltage range, V
A or B
O
A, B
(3)
Human Body Model
All pins
All pins
All pins
4 kV
Electrostatic discharge
(4)
Charged-Device Model
1500 V
(5)
Machine Model
200 V
Continuous power dissipation
See Dissipation Rating Table
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114−B.
(2)
(3)
(4)
(5)
Tested in accordance with JEDEC Standard 22, Test Method C101−A.
Tested in accordance with JEDEC Standard 22, Test Method A115−A.
2
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RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
Supply voltage, V
CC
3
2
3.3
3.6
V
V
V
V
Ω
High-level input voltage, V
IH
V
CC
0.8
Low-level input voltage, V
IL
0
Voltage at any bus terminal (separate or common mode) V or V
−1.4
30
3.8
55
A
B
Differential load resistance, R
L
Signaling rate, 1/t
Clock frequency
250 Mbps
125 MHz
UI
Ambient temperature, T
−40
85
°C
A
(1)
(2)
In accordance with the Low-K thermal metric difinitions of EIA/JESD51−3.
In accordance with the High-K thermal metric difinitions of EIA/JESD51−7.
DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
(1)
MIN
(2)
TYP
PARAMETER
TEST CONDITIONS
MAX
140
45
7
UNIT
mA
EN = V , Ιnput = V
CC
or GND, R = 50 Ω
112
CC
CC
CC
CC
L
Driver enabled
Driver disabled
EN = V , Ιnput = V
CC
or GND, R = No load
mA
L
I
Supply current
CC
EN = V , Ιnput = V
CC
or GND, R = 50 Ω
mA
L
EN = V , Ιnput = V
CC
or GND, R = No load
7
mA
L
V
CC
= 3.6 V, EN = V , C = 15 pF, R = 50 Ω,Input 125
CC
L
L
Device power dissipation, P
MHz 50 % duty cycle square wave,
= 85°C
529
mW
D
T
A
(1)
(2)
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
All typical values are at 25°C and with a 3.3-V supply voltage.
3
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DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
(1)
MIN
(2)
TYP
PARAMETER
TEST CONDITIONS
MAX
UNIT
LVTTL (D, EN) INPUT SPECIFICATIONS
|I
|I
|
10
10
µA
µA
pF
High-level input current
Low-level input current
Input capacitance
V
V
= 2 V or V
CC
IH
IH
|
= GND or 0.8 V
IL
IL
(3)
C
5
V = 0.4 sin(30E6πt) + 0.5 V
I
i
M−LVDS (A, B) OUTPUT SPECIFICATIONS
V
480
−50
0.8
650
50
mV
mV
V
Differential output voltage magnitude
AB
See Figure 2
See Figure 3
Change in differential output voltage magnitude
between logic states
∆V
AB
V
1.2
50
Steady-state common-mode output voltage
OS(SS)
Change in steady-state common-mode output
voltage between logic states
∆V
−50
mV
mV
V
OS(SS)
V
150
2.4
Peak-to-peak common-mode output voltage
OS(PP)
Maximum steady-state open-circuit output
voltage
V
0
0
A(OC)
See Figure 7
See Figure 5
Maximum steady-state open-circuit output
voltage
V
2.4
V
B(OC)
V
V
I
1.2V
V
V
Voltage overshoot, low-to-high level output
Voltage overshoot, high-to-low level output
P(H)
SS
−0.2 V
P(L)
SS
24
20
mA
Differential short-circuit output current magnitude See Figure 4
OS
−1.4 V ≤ (V or V ) ≤ 3.8 V,
A
B
I
−20
−20
µA
µA
High-impedance state output current
OZ
Other output = 1.2 V
−1.4 V ≤ (V or V ) ≤ 3.8 V,
A
B
I
20
Power-off output current
Other output = 1.2 V,
0 ≤ V ≤ 1.5 V
O(OFF)
CC
(3)
V = 0.4 sin(30E6πt) + 0.5 V,
I
C
or C
3
pF
pF
Output capacitance
A
B
Other input at 1.2 V, driver disabled
(3)
V = 0.4 sin(30E6πt) V,
I
C
C
2.5
Differential output capacitance
AB
Driver disabled
0.99
1.01
Output capacitance balance, (C /C )
A/B
A
B
(1)
(2)
(3)
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
All typical values are at 25°C and with a 3.3-V supply voltage.
HP4194A impedance analyzer (or equivalent)
4
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SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
(1)
PARAMETER
TEST CONDITIONS
See Figure 5
MIN TYP
MAX
3
UNIT
ns
t
t
t
t
t
t
t
t
1
1
1
1
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
pLH
pHL
r
3
ns
2
ns
2
ns
Differential output signal fall time
f
100
160
100
800
ps
Pulse skew (|t
− t
|)
sk(p)
sk(o)
sk(bb)
sk(pp)
pHL pLH
ps
Output skew
(2)
ps
Bank-to-bank skew
(3)
ps
Part-to-part skew
100 MHz clock input, All channels
enabled
(4)
t
t
t
1
3
20
ps
ps
ps
Period jitter, rms (1 standard deviation)
jit(per)
jit(c−c)
jit(pp)
100 MHz clock input, All channels
enabled
(4)
Cycle-to-cycle jitter
15
200 Mbps 2 −1 PRBS input, All
(4)
46
110
Peak-to-peak jitter
channels enabled
t
t
t
t
7
7
7
7
ns
ns
ns
ns
Enable time, high-impedance-to-high-level output
Enable time, high-impedance-to-low-level output
Disable time, high-level-to-high-impedance output
pZH
pZL
pHZ
pLZ
See Figure 6
See Figure 6
Disable time, low-level-to-high-impedance output
(1)
(2)
(3)
All typical values are at 25°C and with a 3.3-V supply voltage.
t , which only applies to the SN65MLVD129, is the magnitude of the difference between the t
sk(bb)
sk(pp)
and t
of two outputs of any bank.
PLH
PHL
t
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Stimulus jitter has been subtracted from the numbers.
(4)
5
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PARAMETER MEASUREMENT INFORMATION
V
CC
I
A
A
B
V
A
+ V
2
B
I
I
D
V
AB
I
B
V
Y
V
I
V
OS
V
B
Figure 1. Driver Voltage and Current Definitions
3.32 kΩ
A
+
−1 V ≤ V
test
≤ 3.4 V
V
AB
49.9 Ω
3.32 kΩ
D
_
B
:
NOTE All resistors are 1% tolerance.
Figure 2. Differential Output Voltage Test Circuit
A
B
R1
24.9 Ω
≈ 1.3 V
≈ 0.7 V
A
C1
1 pF
D
V
∆V
OS(SS)
OS(PP)
V
OS
B
C3
2.5 pF
R2
24.9 Ω
V
OS(SS)
C2
1 pF
NOTES:A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, frequency = 1 MHz,
r
f
duty cycle = 50 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C. R1 and R2 are metal film, surface mount, 1%, and located within 2 cm of the D.U.T.
D. The measurement of V
is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
OS(PP)
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
I
OS
A
B
0 V or V
CC
+
V
Test
−1 V or 3.4 V
−
Figure 4. Driver Short-Circuit Test Circuit
6
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V
CC
V
CC
/2
Input
0 V
t
pLH
t
pHL
V
SS
0.9V
V
P(H)
SS
Output
0 V
V
P(L)
0.1V
SS
0 V
SS
t
f
t
r
:
NOTE All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, frequency = 1 MHz,
r
f
duty cycle = 50 5%.
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
R1
24.9 Ω
A
C1
1 pF
D
C4
0.5 pF
GND or V
CC
Output
C3
2.5 pF
C2
1 pF
B
R2
24.9 Ω
EN
Input
V
CC
V
CC
/2
EN
0 V
t
t
t
pZH
pHZ
∼ 0.6 V
0.1 V
Output With
D at V
0 V
CC
t
pZL
pLZ
Output With
D at GND
0 V
−0.1 V
∼ −0.6 V
NOTES:A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, frequency = 1 MHz,
r
f
duty cycle = 50 5%.
B. C1, C2, C3, and C4 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C. R1 and R2 are metal film, surface mount, 1%, and located within 2 cm of the D.U.T.
Figure 6. Driver Enable and Disable Time Circuit and Definitions
A
0 V or V
CC
B
V
A
or V
B
1.62 kΩ, 1%
Figure 7. Driver Maximum Steady State Output Voltage
7
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V
V
CC
CLOCK
INPUT
/2
CC
0 V
1/f0
Period Jitter
IDEAL
OUTPUT
V
V
CC
0 V
PRBS INPUT
/2
CC
V
A
−V
B
1/f0
0 V
ACTUAL
OUTPUT
Peak to Peak Jitter
0 V
V
−V
−V
A
B
V
−V
B
A
OUTPUT 0 V
t
c(n)
=t
V
A
t
−1/f0
B
jit(per)
c(n)
t
jit(pp)
Cycle to Cycle Jitter
OUTPUT
0 V
− V
V
A
B
t
t
c(n+1)
c(n)
t
= | t |
− t
jit(cc)
c(n) c(n+1)
NOTES:D. All input pulses are supplied by an Agilent 8304A Stimulus System.
E. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
F. Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50 1% duty cycle clock input.
15
G. Peak-to-peak jitter is measured using a 200 Mbps 2 −1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
Terminal Functions − SN65MLVD128
PIN
TYPE
DESCRIPTION
NAME
1D
NO.
39
Input
Input
Data inputs for drivers
EN1 − EN8
1A − 8A
1B − 8B
27, 28, 32, 33, 40, 41, 45, 46
2, 4, 8, 10, 14, 16, 20, 22
3, 5, 9, 11, 15, 17, 21, 23
Driver enable, active high, individual enables
M-LVDS bus noninverting output
M-LVDS bus inverting output
Output
Output
6, 12, 18, 24, 25, 26, 31, 37,
38, 43, 44
GND
Power
Circuit ground
1, 7, 13, 19, 29, 30, 35, 36,
47, 48
V
Power
N/A
Supply voltage
Not connected
CC
NC
34, 42
8
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Terminal Functions − SN65MLVD129
PIN
TYPE
Input
Input
DESCRIPTION
NAME
NO.
1D, 2D
39, 34
Data inputs for drivers
27, 28, 32, 33,
40, 41, 45, 46
EN1 − EN8
1A − 8A
1B − 8B
GND
Driver enable, active high, individual enables
2, 4, 8, 10,
14, 16, 20, 22
Output
Output
Power
M-LVDS bus noninverting output
M-LVDS bus inverting output
Circuit ground
3, 5, 9, 11,
15, 17, 21, 23
6, 12, 18, 24, 25, 26, 31, 37,
38, 43, 44
1, 7, 13, 19, 29, 30, 35, 36,
47, 48
V
Power
N/A
Supply voltage
Not connected
CC
NC
42
PIN ASSIGNMENTS
MLVD129DGG
48-TSSOP PACKAGE
(TOP VIEW)
MLVD128DGG
48-TSSOP PACKAGE
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
VCC
1A
VCC
VCC
EN1
EN2
GND
GND
NC
EN3
EN4
1D
GND
GND
VCC
VCC
2D
EN5
EN6
GND
VCC
VCC
EN7
EN8
GND
GND
VCC
1A
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
VCC
VCC
EN1
EN2
GND
GND
NC
1B
1B
2A
2B
GND
VCC
3A
3B
4A
4B
GND
VCC
5A
5B
6A
6B
GND
VCC
7A
2A
2B
GND
VCC
3A
3B
4A
4B
GND
VCC
5A
5B
6A
EN3
EN4
1D
GND
GND
VCC
VCC
NC
EN5
EN6
GND
VCC
VCC
EN7
EN8
GND
GND
9
39
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
38
37
36
35
34
33
32
31
30
29
28
27
26
25
11
12
13
14
15
16
17
18
19
20
21
22
23
24
6B
GND
VCC
7A
7B
8A
8B
7B
8A
8B
GND
GND
NC − No internal connection
FUNCTION TABLE
MLVD128/MLVD129
INPUT ENABLE
OUTPUTS
D
EN
A
B
L
H
H
H
OPEN
L
L
H
L
Z
Z
H
L
H
Z
Z
H
OPEN
X
X
H = high level, L = low level, Z = high impedance, X = Don’t care, OPEN = indeterminate
9
ꢀ ꢁꢂꢃ ꢄꢅꢆꢇ ꢈ ꢉꢊ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢉ
ꢋ
www.ti.com
SLLS586 − MARCH 2004
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
DRIVER OUTPUT
DRIVER INPUT AND DRIVER ENABLE
V
CC
V
CC
400 Ω
D or EN
7 V
A or
B
360 kΩ
10
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇꢈ ꢉꢋ
www.ti.com
SLLS586 − MARCH 2004
TYPICAL CHARACTERISTICS
RMS SUPPLY CURRENT
RMS SUPPLY CURRENT
vs
vs
INPUT FREQUENCY
FREE-AIR TEMPERATURE
180
180
150
120
90
V
T
= 3.3 V
CC
A
V
CC
= 3.3 V
= 255C
f = 100 MHz
All EN = V
All EN = V
R
CC
CC
= 50 W
L
R
L
= 50 W
150
120
90
60
60
25
50
75
100
125
−40
−15
35
60
85
10
f − Input Frequency − MHz
T
A
− Free-Air Temperature − °C
Figure 9
Figure 10
DIFFERENTIAL OUTPUT VOLTAGE MAGNITUDE
PROPAGATION DELAY TIME
vs
vs
INPUT FREQUENCY
FREE-AIR TEMPERATURE
2.4
2.3
2.2
700
650
600
V
= 3.3 V
CC
T
= 255C
A
f = 500 kHz
EN = V
EN = V
R
CC
CC
= 50 W,
L
R
= 50 W
L
2.1
2
t
V
CC
= 3.6 V
PLH
V
CC
= 3.3 V
550
500
1.9
1.8
t
V
CC
= 3 V
PHL
1.7
1.6
450
−40
−15
10
60
85
35
25
50
75
100
125
T
A
− Free-Air Temperature − °C
f − Input Frequency − MHz
Figure 12
Figure 11
11
ꢀ ꢁꢂꢃ ꢄꢅꢆꢇ ꢈ ꢉꢊ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢉ
ꢋ
www.ti.com
SLLS586 − MARCH 2004
TRANSITION TIME
vs
PEAK-TO-PEAK JITTER
vs
FREE-AIR TEMPERATURE
DATA RATE
2
1.9
1.8
100
90
V
T
2
= 3.3 V,
V
= 3.3 V
CC
CC
f = 500 kHz
EN = V
= 255C,
A
15
-1 PRBS NRZ,
CC
= 50 W
All EN = V
See Figure 8
CC
R
80
L
1.7
70
60
50
40
30
1.6
1.5
1.4
t
f
t
r
1.3
1.2
20
10
1.1
1
35
−40
−15
60
85
10
50
100
150
200
250
T
A
− Free-Air Temperature − °C
Data Rate − Mbps
Figure 13
Figure 14
PERIOD JITTER
vs
CYCLE-TO-CYCLE JITTER
vs
CLOCK FREQUENCY
CLOCK FREQUENCY
13
12
11
10
1.0
V
= 3.3 V,
= 255C,
V
CC
= 3.3 V,
= 255C,
CC
T
T
0.9
0.8
0.7
0.6
A
A
Input = Clock
Input = Clock
All EN = V
See Figure 8
All EN = V
See Figure 8
CC
CC
9
8
7
6
5
4
0.5
0.4
0.3
0.2
0.1
3
2
1
0
0
25
50
75
100
125
50
75
100
125
25
f − Clock Frequency − MHz
f − Clock Frequency − MHz
Figure 15
Figure 16
12
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇꢈ ꢉꢋ
www.ti.com
SLLS586 − MARCH 2004
APPLICATION INFORMATION
CLOCK DISTRIBUTION
SN65MLVD128 Output
Input Source: 19.6608 MHz Clock With 50%
SN65MLVD128 Output
Input Source: 61.44 MHz Clock With 50%
Duty Cycle, V
= 3.3 V, R = 50 W, C = 2.5 pF
Duty Cycle, V
= 3.3 V, R = 50 W, C = 2.5 pF
CC
L
L
CC
L
L
Output Duty cycle = 49.97%.
Vertical scale = 142 mV/div
Horizontal scale = 11 ns/div
Output duty cycle = 50.01%.
Vertical scale = 142 mV/div
Horizontal scale = 4 ns/div
Figure 17
Figure 18
DATA DISTRIBUTION
SN65MLVD128 Output
15
Input Source: 250 Mbps, 2 −1 PRBS,
V
= 3.3 V, R = 50 W, C = 2.5 pF
CC
L L
Vertical scale = 150 mV/div
Horizontal scale = 1.21 ns/div
Figure 19
13
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN65MLVD128DGG
SN65MLVD128DGGR
SN65MLVD129DGG
SN65MLVD129DGGR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
DGG
48
48
48
48
40
2000
40
TBD
TBD
TBD
TBD
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
DGG
DGG
DGG
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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