SN65MLVD201D [TI]
MULTIPOINT-LVDS LINE DRIVER AND RECEIVER; 多点LVDS线路驱动器和接收器
| 型号： | SN65MLVD201D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MULTIPOINT-LVDS LINE DRIVER AND RECEIVER |
| 文件： | 总21页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
MULTIPOINT-LVDS LINE DRIVER AND RECEIVER
D
D
D
D
Backplane or Cabled Multipoint Data and
Clock Transmission
FEATURES
D
Low-Voltage Differential 30-Ω to 55-Ω Line
Drivers and Receivers for Signaling Rates
Up to 200 Mbps
Cellular Base Stations
(1)
Central-Office Switches
Network Switches and Routers
D
D
Type-1 Receivers Incorporate 25 mV of
Hysteresis
DESCRIPTION
Type-2 Receivers Provide an Offset
(100 mV) Threshold to Detect Open-Circuit
and Idle-Bus Conditions
The SN65MLVD201, 203, 206, and 207 are
multipoint-low-voltage differential (M-LVDS) line drivers
and receivers, which are optimized to operate at signaling
rates up to 200 Mbps. All parts comply with the multipoint
low-voltage differential signaling (M–LVDS) standard
TIA/EIA-899. These circuits are similar to their
TIA/EIA-644 standard compliant LVDS counterparts, with
added features to address multipoint applications. The
driver output has been designed to support multipoint
buses presenting loads as low as 30 Ω, and incorporates
controlled transition times to allow for stubs off of the
backbone transmission line.
D
Meets or Exceeds the M-LVDS Standard
TIA/EIA-899 for Multipoint Data Interchange
D
Power Up/Down Glitch Free
D
Controlled Driver Output Voltage Transition
Times for Improved Signal Quality
D
–1 V to 3.4 V Common-Mode Voltage Range
Allows Data Transfer With 2 V of Ground
Noise
D
D
Bus Pins High Impedance When Disabled or
These devices have Type-1 and Type-2 receivers that
detect the bus state with as little as 50 mV of differential
input voltage over a common-mode voltage range of –1 V
to 3.4 V. The Type-1 receivers exhibit 25 mV of differential
input voltage hysteresis to prevent output oscillations with
slowly changing signals or loss of input. Type-2 receivers
include an offset threshold to provide a known output state
under open-circuit, idle-bus, and other faults conditions.
The devices are characterized for operation from –40°C to
85°C.
V
≤ 1.5 V
CC
100-Mbps Devices Available
(SN65MLVD200, 202, 204, 205)
APPLICATIONS
D
Low-Power High-Speed Short-Reach
Alternative to TIA/EIA-485
LOGIC DIAGRAM (POSITIVE LOGIC)
SN65MLVD201,SN65MLVD206
SN65MLVD203,SN65MLVD207
9
3
Y
DE
5
D
DE
RE
10
Z
4
D
4
3
2
RE
R
12
11
A
B
6
7
2
A
B
1
R
Pleasebe aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
(1)
The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2002 – 2003, Texas Instruments Incorporated
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduring
storageor handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER
FOOTPRINT
SN75176
RECEIVER TYPE
Type 1
PACKAGE MARKING
MF201
SN65MLVD201D
SM65MLVD203D
SN65MLVD206D
SM65MLVD207D
SN75ALS180
SN75176
Type 1
MLVD203
Type 2
MF206
SN75ALS180
Type 2
MLVD207
PACKAGE DISSIPATION RATINGS
T
≤ 25°C
DERATING FACTOR
T = 85°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
D(8)
725 mW
5.8 mW/_C
7.6 mW/_C
377 mW
D(14)
950 mW
494 mw
ABSOLUTE MAXIMUM RATINGS
overoperating free-air temperature range unless otherwise noted
(1)
SN65MLVD201, 203, 206, AND
207
(2)
Supply voltage range , V
–0.5 V to 4 V
–0.5 V to 4 V
–1.8 V to 4 V
–4 V to 6 V
CC
D, DE, RE
A, B (201, 206)
A, B (203, 207)
R
Input voltage range
Output voltage range
Electrostaticdischarge
–0.3 V to 4 V
–1.8 V to 4 V
±8 kV
Y, Z, A, or B
A, B, Y, and Z
All pins
(3)
Human Body Model
±2 kV
(4)
Charged-DeviceModel
All pins
±1500 V
Continuouspowerdissipation
Storagetemperaturerange
See Dissipation Rating Table
–65°C to 150°C
(1)
Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice. Thesearestressratingsonly,and
functionaloperation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114–A.
(2)
(3)
(4)
Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
Supply voltage, V
3
2
3.3
3.6
V
V
CC
High-level input voltage, V
V
IH
CC
0.8
Low-level input voltage, V
IL
GND
–1.4
0.05
–40
V
Voltage at any bus terminal V , V
V
or V
Z
3.8
V
A
B,
Y
Magnitude of differential input voltage, V
V
V
ID
CC
85
Operatingfree-airtemperature, T
°C
A
2
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
DEVICE ELECTRICAL CHARACTERISTICS
overrecommended operating conditions unless otherwise noted
(1)
PARAMETER
TEST CONDITIONS
= 50 Ω, All others open
MIN TYP
MAX
22
4
UNIT
Driver only
RE and DE at V
,
R
L
13
1
CC
Bothenabled
Bothenabled
Receiver only
RE at V , DE at 0 V, R = No Load, All others open
CC
L
I
Supplycurrent
mA
CC
RE at 0 V, DE at V , R = 50 Ω, All others open
16
4
24
13
CC
RE at 0 V, DE at 0 V,
L
R
= 50 Ω, All others open
L
(1)
All typical values are at 25°C and with a 3.3-V supply voltage.
DRIVER ELECTRICAL CHARACTERISTICS
overrecommended operating conditions unless otherwise noted
(1)
MIN
(2)
TYP
PARAMETER
TEST CONDITIONS
MAX
UNIT
V
or
AB
480
650
mV
Differentialoutputvoltagemagnitude
V
YZ
See Figure 2
See Figure 3
∆ V
or
Change in differentialoutputvoltagemagnitude
between logic states
AB
–50
0.8
50
1.2
50
mV
V
∆ V
YZ
V
Steady-statecommon-modeoutputvoltage
OS(SS)
Changeinsteady-statecommon-modeoutput
voltage between logic states
∆V
–50
mV
mV
V
OS(SS)
V
150
2.4
Peak-to-peakcommon-modeoutputvoltage
OS(PP)
V
V
Maximumsteady-stateopen-circuitoutput
voltage
Y(OC) or
A(OC)
0
0
See Figure 7
See Figure 5
V
Maximumsteady-stateopen-circuitoutput
voltage
Z(OC) or
B(OC)
2.4
V
V
V
V
I
1.2V
V
V
Voltage overshoot, low-to-high level output
Voltageovershoot, high-to-low level output
High-level input current (D, DE)
P(H)
P(L)
SS
–0.2 V
SS
0
10
10
24
µA
µA
mA
V
V
= 2 V
IH
IH
I
IL
0
Low-level input current (D, DE)
= 0.8 V
IL
I
Differentialshort-circuitoutputcurrentmagnitude See Figure 4
OS
High-impedance state output current (driver
only)
–1.4 V ≤ V or V ≤ 3.8 V,
Y Z
I
I
–15
–10
10
10
µA
µA
OZ
Other output = 1.2 V
–1.4 V ≤ V or V ≤ 3.8 V,
Y
Z
Power-off output current
Outputcapacitance
Other output = 1.2 V,
0 V ≤ V ≤ 1.5 V
O(OFF)
CC
V = 0.4 sin(30E6πt) + 0.5 V,
(3)
I
C
or C
3
pF
pF
Y
Z
Other input at 1.2 V, driver disabled
(3)
V
= 0.4 sin(30E6πt) V,
AB
C
C
2.5
Differentialoutputcapacitance
YZ
Driver disabled
0.99
1.01
Output capacitance balance, (C /C )
Y/Z
Y
Z
(1)
(2)
(3)
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
All typical values are at 25°C and with a 3.3-V supply voltage.
HP4194A impedance analyzer (or equivalent)
3
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
RECEIVER ELECTRICAL CHARACTERISTICS
(1)
overrecommended operating conditions unless otherwise noted
(1)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
50
UNIT
Type 1
Positive-goingdifferentialinputvoltage
V
V
V
mV
mV
mV
IT+
threshold
Type 2
Type 1
Type 2
Type 1
Type 2
150
–50
Negative-goingdifferentialinputvoltage
threshold
See Figure 9 and Table 1 and
Table 2
IT–
50
25
0
Differential input voltage hysteresis,
HYS
(V
IT+
– V )
IT
V
V
I
2.4
V
High-leveloutputvoltage
I
I
= –8 mA
= 8 mA
OH
OH
0.4
0
V
Low-leveloutputvoltage
OL
OL
–10
–10
–10
µA
µA
µA
High-level input current (RE)
Low-level input current (RE)
High-impedanceoutputcurrent
V
V
V
= 2 V
IH
IH
IL
O
I
0
= 0.8 V
IL
OZ
I
15
= 0 V or 3.6 V
(2)
V = 0.4 sin(30E6πt) + 0.5 V,
Other input at 1.2 V
I
C
C
or C
3
pF
pF
Inputcapacitance
A
B
(2)
2.5
Differentialinputcapacitance
V
AB
= 0.4 sin(30E6πt) V
AB
C
(1)
(2)
0.99
1.01
Input capacitance balance, (C C )
A/ B
All typical values are at 25°C and with a 3.3-V supply voltage.
HP4194A impedance analyzer (or equivalent)
A/B
BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS
overrecommended operating conditions unless otherwise noted
(1)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
32
20
0
UNIT
0
–20
–32
0
V
= 3.8 V,
V
V
V
= 1.2 V,
= 1.2 V
= 1.2 V
= 1.2 V
= 1.2 V
= 1.2 V
A
B
B
B
Receiver or transceiver with driver
disabled input current
V
A
= 0 V or 2.4 V,
= –1.4 V,
I
A
µA
V
A
32
20
0
V
B
V
B
V
B
= 3.8 V,
V
A
Receiver or transceiver with driver
disabled input current
–20
–32
= 0 V or 2.4 V,
= –1.4 V,
V
A
I
I
I
µA
µA
µA
B
V
A
Receiver or transceiver with driver
disabled differential input current
(I – I )
–4
4
V
A
= V
B,
–1.4 ≤ V ≤ 3.8 V
A
AB
A
B
0
–20
–32
0
32
20
0
V
A
= 3.8 V,
V
V
= 1.2 V, 0 V ≤ V
= 1.2 V, 0 V ≤ V
≤ 1.5 V
≤ 1.5 V
≤ 1.5 V
≤ 1.5 V
≤ 1.5 V
≤ 1.5 V
B
CC
CC
CC
CC
CC
CC
Receiver or transceiver power-off input
current
V
A
= 0 V or 2.4 V,
= –1.4 V,
B
A(OFF)
V
A
V = 1.2 V, 0 V ≤ V
B
32
20
0
V
= 3.8 V,
V
= 1.2 V, 0 V ≤ V
= 1.2 V, 0 V ≤ V
= 1.2 V, 0 V ≤ V
B
B
B
A
Receiver or transceiver power-off input
current
–20
–32
V
V
= 0 V or 2.4 V,
= –1.4 V,
V
A
I
I
µA
B(OFF)
V
A
Receiver input or transceiver power-off
–4
4
µA
pF
pF
V
= V , 0 V ≤ V
≤ 1.5 V, –1.4 ≤ V ≤ 3.8 V
AB(OFF)
A
B
CC
A
differential input current (I – I )
A
B
Transceiver with driver disabled input
capacitance
(2)
,
C
A
5
5
V
A
= 0.4 sin (30E6πt) + 0.5V
= 0.4 sin (30E6πt) + 0.5V
V
B
=1.2 V
=1.2 V
Transceiver with driver disabled input
capacitance
(2)
,
C
B
V
B
V
A
(1)
(2)
All typical values are at 25°C and with a 3.3-V supply voltage.
HP4194A impedance analyzer (or equivalent)
4
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS (continued)
(1)
MIN TYP
PARAMETER
TEST CONDITIONS
MAX
UNIT
Transceiver with driver disabled differential
inputcapacitance
(2)
= 0.4 sin (30E6πt)V
C
C
3
pF
V
AB
AB
Transceiver with driver disabled input
0.99
1.01
A/B
capacitance balance, (C /C )
A
B
(1)
(2)
All typical values are at 25°C and with a 3.3-V supply voltage.
HP4194A impedance analyzer (or equivalent)
DRIVER SWITCHING CHARACTERISTICS
overrecommended operating conditions unless otherwise noted
(1)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
2.4
2.4
1.6
1.6
100
1
UNIT
ns
ns
ns
ns
ps
ns
ps
ps
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
1
1
1
1
1.5
1.5
Propagationdelaytime,low-to-high-leveloutput
Propagationdelaytime,high-to-low-leveloutput
Differential output signal rise time
pLH
pHL
r
See Figure 5
Differential output signal fall time
f
0
Pulse skew (|t
– t |)
pHL pLH
sk(p)
sk(pp)
jit(per)
jit(pp)
pHZ
pLZ
pZH
pZL
Part-to-partskew
(2)
(3)
2
3
Periodjitter, rms (1 standard deviation)
100 MHz clock input
15
(2)(5)
Peak-to-peakjitter
(4)
30
130
7
200 Mbps 2 –1 PRBS input
Disable time, high-level-to-high-impedance output
Disable time, low-level-to-high–impedance output
Enable time, high-impedance-to-high-level output
7
See Figure 6
7
7
Enable time, high-impedance-to-low-level output
(1)
(2)
(3)
(4)
(5)
All typical values are at 25°C and with a 3.3-V supply voltage.
Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
t = t = 0.5 ns (10% to 90%), measured over 30 k samples.
r
f
t = t = 0.5 ns (10% to 90%), measured over 100 k samples.
r
f
Peak-to-peak jitter includes jitter due to pulse skew (t
).
sk(p)
RECEIVER SWITCHING CHARACTERISTICS
overrecommended operating conditions unless otherwise noted
(1)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
6
UNIT
ns
t
t
t
t
2
2
1
1
4
4
Propagationdelaytime,low-to-high-leveloutput
Propagationdelaytime,high-to-low-leveloutput
Output signal rise time
pLH
6
ns
pHL
2.3
2.3
300
500
1
ns
r
f
ns
Output signal fall time
C = 15 pF, See Figure 10
L
Type 1
Type 2
100
300
ps
Pulse skew (|t
– t
|)
t
pHL pLH
sk(p)
ps
(2)
t
t
ns
Part-to-partskew
sk(pp)
(3)
(4)
100 MHz clock input
4
300
450
7
700
800
10
ps
ps
ps
ns
ns
ns
ns
Periodjitter, rms (1 standard deviation)
jit(per)
Type 1
Type 2
(3)(6)
Peak-to-peakjitter
15
(5)
200 Mbps 2 –1 PRBS input
t
jit(pp)
t
t
t
t
Disable time, high-level-to-high-impedance output
Disable time, low-level-to-high-impedance output
Enable time, high-impedance-to-high-level output
Enable time, high-impedance-to-low-level output
pHZ
pLZ
pZH
pZL
10
See Figure 11
15
15
(1)
(2)
(3)
(4)
(5)
(6)
All typical values are at 25°C and with a 3.3-V supply voltage.
HP4194A impedance analyzer (or equivalent)
Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
V
V
= 200 mV (LVD201, 203), V = 400 mV (LVD206, 207), V
pp ID pp
= 1 V, t = t = 0.5 ns (10% to 90%), measured over 30 k samples.
r f
ID
ID
cm
cm
= 200 mV (LVD201, 203), V = 400 mV (LVD206, 207), V
= 1 V, t = t = 0.5 ns (10% to 90%), measured over 100 k samples.
r f
pp ID pp
Peak-to-peak jitter includes jitter due to pulse skew (t
).
sk(p)
5
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
I
A
or I
Y
A/Y
I
I
D
V
or V
or V
AB
YZ
I
B
or I
Z
V
A
or V
Y
B/Z
V
I
V
OS
V
B
Z
V
A
+ V
2
V
Y
+ V
2
B
Z
or
Figure 1. Driver Voltage and Current Definitions
3.32 kΩ
A/Y
+
–1 V ≤ V
≤ 3.4 V
V
AB
or V
YZ
49.9 Ω
D
test
_
B/Z
3.32 kΩ
:
NOTE All resistors are 1% tolerance.
Figure 2. Differential Output Voltage Test Circuit
A/Y
B/Z
R1
24.9 Ω
≈ 1.3 V
≈ 0.7 V
A/Y
C1
1 pF
D
V
V
OS(SS)
OS(PP)
V
OS
B/Z
C3
2.5 pF
R2
24.9 Ω
V
OS
C2
1 pF
NOTES:A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse frequency = 500 kHz,
r
f
duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
D. The measurement of V
is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
OS(PP)
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
I
OS
A/Y
B/Z
0 V or V
CC
+
V
Test
–1 V or 3.4 V
–
Figure 4. Driver Short-Circuit Test Circuit
6
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
A/Y
B/Z
C1
1 pF
C3
0.5 pF
R1
50 Ω
Output
D
C2
1 pF
V
CC
V
CC
/2
Input
0 V
t
t
pHL
pLH
V
SS
0.9V
SS
V
P(H)
Output
0 V
V
P(L)
0.1V
SS
0 V
SS
t
f
t
r
NOTES:A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, frequency = 500 kHz,
r
f
duty cycle = 50 ± 5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
R1
24.9 Ω
A/Y
C1
1 pF
D
C4
0.5 pF
0 V or V
Output
CC
C3
2.5 pF
C2
1 pF
B/Z
R2
24.9 Ω
DE
V
CC
V
CC
/2
DE
0 V
t
t
t
pZH
pHZ
0.6 V
0.1 V
Output With
D at V
0 V
CC
t
pZL
pLZ
Output With
D at 0 V
0 V
–0.1 V
–0.6 V
NOTES:A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, frequency = 500 kHz, duty cycle = 50 ±
r
f
5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 6. Driver Enable and Disable Time Circuit and Definitions
7
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
A/Y
B/Z
0 V or V
CC
V , V , V or V
Z
1.62 kΩ , ±1%
A
B
Y
Figure 7. Maximum Steady State Output Voltage
V
V
CC
CLOCK
INPUT
/2
CC
0 V
1/f0
Period Jitter
IDEAL
OUTPUT
V
V
CC
0 V
PRBS INPUT
/2
CC
V
A
–V or V –V
B
Y
Z
1/f0
0 V
ACTUAL
OUTPUT
Peak to Peak Jitter
0 V
V
–V or V –V
B Y Z
A
V
A
–V or V –V
B Y Z
OUTPUT 0 V Diff
–V or V –V
Z
t
c(n)
= t
V
t
–1/f0
c(n)
A
B
Y
jit(per)
t
jit(pp)
NOTES:A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input.
15
D. Peak-to-peak jitter is measured using a 200Mbps 2 –1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
I
A
A
B
I
O
R
V
ID
V
O
V
CM
V
A
I
B
(V + V )/2
V
B
A
B
Figure 9. Receiver Voltage and Current Definitions
8
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
Table 1. Type-1 Receiver Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON–
MODE INPUT VOLTAGE
APPLIED VOLTAGES
RECEIVER
OUTPUT
V
IA
V
IB
V
ID
V
IC
2.400
0.000
3.800
3.750
–1.350
–1.400
0.000
2.400
3.750
3.800
–1.400
–1.350
2.400
–2.400
0.050
1.200
1.200
3.775
3.775
–1.375
–1.375
H
L
H
L
–0.050
0.050
H
L
–0.050
:
NOTE H= high level, L = low level, output state assumes receiver is enabled (RE = L)
Table 2. Type-2 Receiver Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON–
MODE INPUT VOLTAGE
APPLIED VOLTAGES
RECEIVER
OUTPUT
V
IA
V
IB
V
ID
V
IC
2.400
0.000
3.800
3.800
–1.250
–1.350
0.000
2.400
3.650
3.750
–1.400
–1.400
2.400
–2.400
0.150
0.050
0.150
0.050
1.200
1.200
3.725
3.775
–1.325
–1.375
H
L
H
L
H
L
:
NOTE H= high level, L = low level, output state assumes receiver is enabled (RE = L)
V
ID
V
A
C
L
15 pF
V
O
V
B
V
1.2 V
1.0 V
A
V
B
V
ID
0.2 V
0 V
–0.2 V
t
t
pLH
pHL
V
V
O
OH
90%
10%
V
CC
V
OL
/2
t
f
t
r
NOTES:A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, frequency = 50 MHz, duty cycle = 50 ±
r
f
5%.C isacombinationofa20%-tolerance,low-lossceramic,surface-mountcapacitorandfixturecapacitancewithin2cmoftheD.U.T.
L
B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 10. Receiver Timing Test Circuit and Waveforms
9
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
R
L
B
A
1.2 V
499 Ω
R
+
_
C
L
V
TEST
V
O
Inputs
RE
15 pF
V
CC
V
TEST
1 V
A
V
V
CC
RE
/2
CC
0 V
t
pLZ
t
pZL
V
CC
V
CC
/2
Output
R
V
OL
V
OL
+0.5 V
V
TEST
0 V
1.4 V
A
V
V
CC
RE
/2
CC
0 V
t
pHZ
t
pZH
V
V
V
OH
–0.5 V
OH
/2
V
O
CC
0 V
NOTES:A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, frequency = 500 kHz,
r
f
duty cycle = 50 ± 5%.
B. R is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
L
C. R is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
L
D. C is the instrumentation and fixture capacitance within 2 cm of the DUT and ±20%.
L
Figure 11. Receiver Enable/Disable Time Test Circuit and Waveforms
10
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
INPUTS
–V
CLOCK INPUT
V
A
V
IC
B
0.2 V – Type 1 1 V
0.4 V – Type 2
V
A
–V
B
1/f0
Period Jitter
V
IDEAL
OUTPUT
OH
V
A
V
CC
/2
PRBS INPUT
V
OL
1/f0
V
B
V
OH
ACTUAL
OUTPUT
Peak to Peak Jitter
V
CC
/2
V
OH
V
OL
OUTPUT
V
CC
/2
t
c(n)
t
= t –1/f0
c(n)
V
OL
jit(per)
t
jit(pp)
NOTES:A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input.
15
D. Peak-to-peak jitter is measured using a 200 Mbps 2 –1 PRBS input.
Figure 12. Receiver Jitter Measurement Waveforms
PIN ASSIGNMENTS
SN65MLVD201D (Marked as MF201)
SN65MLVD206D (Marked as MF206)
(TOP VIEW)
SN65MLVD203D(Marked as MLVD203)
SN65MLVD207D (Marked as MLVD207)
(TOP VIEW)
R
RE
DE
D
V
B
A
1
2
3
4
8
7
6
5
NC
R
RE
V
V
A
B
Z
Y
1
2
3
4
5
6
7
14
13
12
11
10
9
CC
CC
CC
GND
DE
D
GND
GND
8
NC
NC – No internal connection
11
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
DEVICE FUNCTION TABLE
TYPE-1 RECEIVER (201, 203)
TYPE-2 RECEIVER (206, 207)
INPUTS
= V – V
OUTPUT
R
INPUTS
= V – V
OUTPUT
R
RE
RE
V
ID
V
ID
A
B
A
B
L
L
H
?
L
Z
Z
L
L
H
?
L
Z
Z
V
≥ 50 mV
V
≥ 150 mV
ID
–50 mV < V < 50 mV
ID
50 mV < V < 150 mV
ID
ID
≤ 50 mV
V
ID
≤ –50 mV
L
V
L
ID
X
X
H
X
X
H
Open
Open
Open Circuit
?
Open Circuit
L
L
L
DRIVER
INPUT ENABLE
OUTPUTS
A OR Y B OR Z
D
DE
L
H
H
H
OPEN
L
L
H
L
Z
Z
H
L
H
Z
Z
H
OPEN
X
X
H = high level, L = low level, Z = high impedance, X = Don’t care, ? = indeterminate
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
DRIVER OUTPUT
DRIVER INPUT AND DRIVER ENABLE
RECEIVER ENABLE
V
CC
V
CC
V
CC
360 kΩ
400 Ω
400 Ω
D or DE
7 V
A/Y or B/Z
RE
7 V
360 kΩ
RECEIVER INPUT
RECEIVER OUTPUT
V
CC
V
CC
100 kΩ
250 kΩ
100 kΩ
250 kΩ
10 Ω
R
A
B
10 Ω
200 kΩ
200 kΩ
7 V
12
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
FREQUENCY
FREE-AIR TEMPERATURE
20
20
16
12
V
T
A
=3.3V
= 25°C
CC
16
12
Driver
Driver
Receiver
8
4
0
8
4
0
Receiver
Receiver
V
= 3.3 V
= 25°C
Receiver
CC
V
ID
V
IC
= 250 mV
= 1 V
T
V
ID
V
IC
= 250 mV
= 1 V
A
f = 100 MHz
10
30
50
70
90
110
–50 –30
–10
10
30
50
70
90
T
A
– Free-Air Temperature– °C
f – Frequency – MHz
Figure 13
Figure 14
RECEIVER HIGH-LEVEL OUTPUT CURRENT
RECEIVER LOW-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
70
60
0
T = 25°C
A
T
A
= 25°C
–10
V
CC
=3.6V
–20
–30
V
V
=3.3V
=3.0V
CC
50
40
30
CC
V
CC
=3.0V
–40
–50
–60
–70
V
CC
=3.3V
20
10
0
V
CC
=3.6V
–80
–90
0
1
2
3
4
0
1
2
3
4
V
OH
– High Level Output Voltage – V
V
OL
– Low Level Output Voltage – V
Figure 15
Figure 16
13
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
DIFFERENTIAL OUTPUT VOLTAGE
DRIVER PROPAGATION DELAY
vs
vs
OUTPUT CURRENT
FREE-AIR TEMPERATURE
2
2
V
= 3.3 V
CC
f = 1 MHz
1.6
1.2
1.8
1.6
t
pLH
t
pHL
0.8
1.4
0.4
0
1.2
1
V
T
A
= 3.3 V
2
CC
= 25°C
0
4
6
8
10
12
–50 –30
–10
10
30
50
70
90
I
O
– Output Current – mA
T
A
– Free-Air Temperature– °C
Figure 17
Figure 18
ADDED DRIVER CYCLE-TO-CYCLE JITTER (PEAK)
RECEIVER PROPAGATION DELAY
vs
vs
FREQUENCY
FREE-AIR TEMPERATURE
45
6
4
V
= 3.3 V
= 250 mV
= 1 V
V
= 3.3 V
CC
CC
T = 25°C
A
V
ID
V
IC
Input = Clock
t
pHL
36
27
f = 1 MHz
t
pLH
18
9
2
1
0
10
30
50
70
90
110
–50 –30
–10
10
30
50
70
90
f – Frequency – MHz
T
A
– Free-Air Temperature– °C
Figure 19
Figure 20
14
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
ADDED DRIVER PEAK-TO-PEAK JITTER
ADDED DRIVER PEAK-TO-PEAK JITTER
vs
vs
DATA RATE
FREE-AIR TEMPERATURE
60
60
V
= 3.3 V
CC
= 25°C
T
A
15–1
Input = PRBS 2
50
40
50
40
30
30
20
10
20
10
V
= 3.3 V
CC
= 25°C
T
A
15–1
Input = PRBS 2
f = 200 Mbps
0
0
25
65
105
145
185
225
–50 –30 –10
10
30
50
70
90
Data Rate – Mbps
T
A
– Free-Air Temperature– °C
Figure 21
Figure 22
ADDED RECEIVER CYCLE-TO-CYCLE JITTER
ADDED RECEIVER PEAK-TO-PEAK JITTER
vs
vs
FREQUENCY
FREE-AIR TEMPERATURE
35
28
21
400
320
240
V
V
T
= 3.3 V
CC
= 250 mV
V
V
T
A
= 3.3 V
CC
= 250 mV
ID
= 25°C
ID
V
IC
= 3.0 V
A
= 25°C
15–1
Pattern = 2
V
IC
= –0.5 V
V
IC
= 1 V
14
7
160
80
0
0
10
30
50
70
90
110
0
30
60
90
120
150
180 210
Data Rate – Mbps
f – Frequency – MHz
Figure 23
Figure 24
15
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
ADDED RECEIVER PEAK-TO–PEAK JITTER
vs
SN65MLVD201 DRIVER OUTPUT EYE PATTERN
FREE-AIR TEMPERATURE
15–1
200 Mbps, 2
PRBS, R = 50 Ω
L
400
320
240
160
V
V
V
= 3.3 V
= 250 mV
=1 V
CC
ID
IC
80
0
f =200 Mbps
15–1
Pattern = 2
Horizontal Scale = 1 ns/div
–50 –30
–10
10
30
50
70
90
T
A
– Free-Air Temperature– °C
Figure 25
Figure 26
SN65MLVD201 RECEIVER OUTPUT EYE PATTERN
15–1
200 Mbps, 2
PRBS, C = 15 pF
L
Horizontal Scale = 1 ns/div
Figure 27
16
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558A– DECEMBER 2002 – JUNE 2003
APPLICATION INFORMATION
COMPARISON OF MLVD TO TIA/EIA-485
Receiver Input Threshold (Failsafe)
The MLVD standard defines a type 1 and type 2 receiver. Type 1 receivers include no provisions for failsafe and have their
differential input voltage thresholds near zero volts. Type 2 receivers have their differential input voltage thresholds offset
from zero volts to detect the absence of a voltage difference. The impact to receiver output by the offset input can be seen
in Table 3 and Figure 28.
Table 3. Receiver Input Voltage Threshold Requirements
RECEIVER TYPE
Type 1
OUTPUT LOW
OUTPUT HIGH
0.05 V ≤ V ≤ 2.4 V
–2.4 V ≤ V ≤ –0.05 V
ID
–2.4 V ≤ V ≤ 0.05 V
ID
Type 2
0.15 V ≤ V ≤ 2.4 V
ID
ID
Type 1
High
Type 2
High
200
150
100
50
0
Low
–50
Low
–100
Transition Regions
Figure 28. Expanded Graph of Receiver Differential Input Voltage Showing Transition Region
17
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2005
PACKAGING INFORMATION
Orderable Device
SN65MLVD201D
SN65MLVD201DR
SN65MLVD203D
SN65MLVD203DR
SN65MLVD206D
SN65MLVD206DR
SN65MLVD207D
SN65MLVD207DR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
75
2500
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
8
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
14
14
8
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
2500
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
8
2500
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
14
14
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
2500
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Use of such information may require a license from a third party under the patents or other intellectual property
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
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Amplifiers
amplifier.ti.com
www.ti.com/audio
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dataconverter.ti.com
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www.ti.com/automotive
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dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
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Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
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www.ti.com/opticalnetwork
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www.ti.com/video
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www.ti.com/wireless
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Copyright 2005, Texas Instruments Incorporated
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