SN65MLVD201_10 [TI]
MULTIPOINT-LVDS LINE DRIVER AND RECEIVER; 多点LVDS线路驱动器和接收器
| 型号： | SN65MLVD201_10 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MULTIPOINT-LVDS LINE DRIVER AND RECEIVER |
| 文件： | 总28页 (文件大小：732K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
MULTIPOINT-LVDS LINE DRIVER AND RECEIVER
1
FEATURES
APPLICATIONS
•
Low-Power High-Speed Short-Reach
Alternative to TIA/EIA-485
Backplane or Cabled Multipoint Data and
Clock Transmission
Cellular Base Stations
Central-Office Switches
Network Switches and Routers
•
Low-Voltage Differential 30-Ω to 55-Ω Line
Drivers and Receivers for Signaling Rates(1)
Up to 200 Mbps
•
•
•
Type-1 Receivers Incorporate 25 mV of
Hysteresis
•
•
•
Type-2 Receivers Provide an Offset (100 mV)
Threshold to Detect Open-Circuit and Idle-Bus
Conditions
DESCRIPTION
•
•
•
•
•
•
Meets or Exceeds the M-LVDS Standard
TIA/EIA-899 for Multipoint Data Interchange
The SN65MLVD201, 203, 206, and 207 are
multipoint-low-voltage differential (M-LVDS) line
drivers and receivers, which are optimized to operate
at signaling rates up to 200 Mbps. All parts comply
with the multipoint low-voltage differential signaling
(M-LVDS) standard TIA/EIA-899. These circuits are
similar to their TIA/EIA-644 standard compliant LVDS
counterparts, with added features to address
multipoint applications. The driver output has been
designed to support multipoint buses presenting
loads as low as 30 Ω, and incorporates controlled
transition times to allow for stubs off of the backbone
transmission line.
Controlled Driver Output Voltage Transition
Times for Improved Signal Quality
-1 V to 3.4 V Common-Mode Voltage Range
Allows Data Transfer With 2 V of Ground Noise
Bus Pins High Impedance When Disabled or
VCC ≤ 1.5 V
100-Mbps Devices Available (SN65MLVD200A,
202A, 204A, 205A)
M-LVDS Bus Power Up/Down Glitch Free
The signaling rate of a line, is the number of voltage transitions
that are made per second expressed in the units bps (bits per
second).
These devices have Type-1 and Type-2 receivers
that detect the bus state with as little as 50 mV of
differential input voltage over
a common-mode
voltage range of -1 V to 3.4 V. The Type-1 receivers
exhibit 25 mV of differential input voltage hysteresis
to prevent output oscillations with slowly changing
signals or loss of input. Type-2 receivers include an
offset threshold to provide a known output state
under open-circuit, idle-bus, and other faults
conditions. The devices are characterized for
operation from –40°C to 85°C.
LOGIC DIAGRAM (POSITIVE LOGIC)
SN65MLVD201, SN65MLVD206
SN65MLVD203, SN65MLVD207
9
3
Y
DE
5
D
DE
RE
10
Z
4
D
4
3
2
RE
R
12
11
A
B
6
7
2
A
B
1
R
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER(1)
SN65MLVD201D
SM65MLVD203D
SN65MLVD206D
SM65MLVD207D
FOOTPRINT
SN75176
RECEIVER TYPE
Type 1
PACKAGE MARKING
MF201
SN75ALS180
SN75176
Type 1
MLVD203
Type 2
MF206
SN75ALS180
Type 2
MLVD207
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
PACKAGE DISSIPATION RATINGS
T
A ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
D(8)
725 mW
5.8 mW/°C
7.6 mW/°C
377 mW
494 mw
D(14)
950 mW
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE / UNIT
–0.5 V to 4 V
–0.5 V to 4 V
–1.8 V to 4 V
–4 V to 6 V
Supply voltage range(2), VCC
D, DE, RE
Input voltage range
Output voltage range
Electrostatic discharge
A, B (201, 206)
A, B (203, 207)
R
–0.3 V to 4 V
–1.8 V to 4 V
±8 kV
Y, Z, A, or B
A, B, Y, and Z
All pins
Human Body Model(3)
±2 kV
Charged-Device Model(4)
All pins
±1500 V
Continuous power dissipation
Storage temperature range
See Dissipation Rating Table
–65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
VCC
VIH
VIL
Supply voltage
3
2
3.3
3.6
VCC
0.8
V
V
V
V
V
High-level input voltage
Low-level input voltage
GND
–1.4
0.05
–40
Voltage at any bus terminal VA, VB, VY or VZ
Magnitude of differential input voltage
Operating free-air temperature
3.8
|VID
|
VCC
TA
85 °C
2
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Copyright © 2002–2007, Texas Instruments Incorporated
Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
Driver only
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
RE and DE at VCC, RL = 50 Ω, All others open
RE at VCC, DE at 0 V, RL = No Load, All others open
RE at 0 V, DE at VCC, RL = 50 Ω, All others open
RE at 0 V, DE at 0 V, RL = 50 Ω, All others open
13
1
22
Both disabled
Both enabled
Receiver only
4
ICC
Supply current
mA
24
16
4
13
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN(1) TYP(2)
MAX UNIT
|VAB| or
|VYZ
Differential output voltage magnitude
480
650
mV
|
See Figure 2
See Figure 3
Δ|VAB| or Change in differential output voltage magnitude
–50
0.8
50
1.2
50
mV
V
Δ|VYZ
|
between logic states
VOS(SS)
ΔVOS(SS)
VOS(PP)
Steady-state common-mode output voltage
Change in steady-state common-mode output
voltage between logic states
–50
mV
mV
V
Peak-to-peak common-mode output voltage
150
2.4
VY(OC) or Maximum steady-state open-circuit output
VA(OC) voltage
0
0
See Figure 7
See Figure 5
VZ(OC) or Maximum steady-state open-circuit output
2.4
V
VB(OC)
VP(H)
VP(L)
IIH
voltage
Voltage overshoot, low-to-high level output
Voltage overshoot, high-to-low level output
High-level input current (D, DE)
Low-level input current (D, DE)
1.2 VSS
V
V
–0.2 VSS
VIH = 2 V
0
0
10
10
24
µA
µA
mA
IIL
VIL = 0.8 V
JIOS
J
Differential short-circuit output current magnitude See Figure 4
–1.4 V ≤ VY or VZ ≤ 3.8 V,
Other output = 1.2 V
IOZ
High-impedance state output current (driver only)
–15
–10
10
µA
–1.4 V ≤ VY or VZ ≤ 3.8 V,
Other output = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
IO(OFF)
Power-off output current
10
µA
(3)
VI = 0.4 sin(30E6πt) + 0.5 V,
CY or CZ Output capacitance
3
pF
pF
Other input at 1.2 V, Driver disabled
(3)
VAB = 0.4 sin(30E6πt) V,
CYZ
Differential output capacitance
Output capacitance balance, (CY/CZ)
2.5
Driver disabled
CY/Z
0.99
1.01
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25°C and with a 3.3-V supply voltage.
(3) HP4194A impedance analyzer (or equivalent)
Copyright © 2002–2007, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted(1)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
Type 1
50
mV
150
VIT+
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
Differential input voltage hysteresis, (VIT+ – VIT)
Type 2
Type 1
Type 2
Type 1
Type 2
–50
50
25
0
See Figure 9 and Table 1 and
Table 2
VIT-
mV
VHYS
mV
V
VOH
VOL
IIH
High-level output voltage
Low-level output voltage
IOH = –8 mA
IOL = 8 mA
2.4
0.4
0
V
High-level input current (RE)
Low-level input current (RE)
High-impedance output current
VIH = 2 V
–10
–10
–10
µA
µA
µA
IIL
VIL = 0.8 V
0
IOZ
VO = 0 V or 3.6 V
15
VI = 0.4 sin(30E6πt) + 0.5 V,(2)
Other input at 1.2 V
VAB = 0.4 sin(30E6πt) V(2)
CA or CB Input capacitance
3
pF
pF
CAB
Differential input capacitance
Input capacitance balance, (CA/CB)
2.5
CA/B
0.99
1.01
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)
4
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Copyright © 2002–2007, Texas Instruments Incorporated
Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VB = 1.2 V,
VB = 1.2 V
MIN TYP(1) MAX UNIT
VA = 3.8 V,
0
–20
–32
0
32
20
0
Receiver or transceiver with driver
disabled input current
IA
VA = 0 V or 2.4 V,
VA = –1.4 V,
µA
VB = 1.2 V
VB = 3.8 V,
VA = 1.2 V
32
20
0
Receiver or transceiver with driver
disabled input current
IB
VB = 0 V or 2.4 V,
VB = –1.4 V,
VA = 1.2 V
–20
–32
µA
µA
µA
VA = 1.2 V
Receiver or transceiver with driver
disabled differential input current
(IA – IB)
IAB
VA = VB,
1.4 ≤ VA ≤ 3.8 V
-4
4
VA = 3.8 V,
VB = 1.2 V,
VB = 1.2 V,
VB= 1.2 V,
VA = 1.2 V,
VA = 1.2 V,
VA = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
0 V ≤ VCC ≤ 1.5 V
0 V ≤ VCC ≤ 1.5 V
0 V ≤ VCC ≤ 1.5 V
0 V ≤ VCC ≤ 1.5 V
0 V ≤ VCC ≤ 1.5 V
0
–20
–32
0
32
20
0
Receiver or transceiver power-off
input current
IA(OFF)
VA = 0 V or 2.4 V,
VA = –1.4 V,
VB = 3.8 V,
32
20
0
Receiver or transceiver power-off
input current
IB(OFF)
VB = 0 V or 2.4 V,
VB = –1.4 V,
–20
–32
µA
µA
Receiver input or transceiver
IAB(OFF) power-off differential input current
(IA – IB)
VA = VB, 0 V ≤ VCC ≤ 1.5 V, –1.4 ≤ VA ≤ 3.8 V
–4
4
Transceiver with driver disabled input
capacitance
CA
VA = 0.4 sin (30E6πt) + 0.5V(2)
,
VB = 1.2 V
VA = 1.2 V
5
5
pF
pF
pF
Transceiver with driver disabled input
capacitance
CB
VB = 0.4 sin (30E6πt) + 0.5 V(2)
,
Transceiver with driver disabled
CAB
VAB = 0.4 sin (30E6πt)V(2)
3
differential input capacitance
Transceiver with driver disabled input
capacitance balance, (CA/CB)
CA/B
0.99
1.01
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
1
1
1
1
1.5
1.5
2.4
2.4
1.6
1.6
100
1
ns
ns
ns
ns
ps
ns
ps
ps
ns
ns
ns
ns
Propagation delay time, high-to-low-level output
Differential output signal rise time
See Figure 5
tf
Differential output signal fall time
tsk(p)
tsk(pp)
tjit(per)
tjit(pp)
tPHZ
tPLZ
tPZH
tPZL
Pulse skew (|tPHL – tPLH|)
Part-to-part skew(2)
Period jitter, rms (1 standard deviation)(3)
Peak-to-peak jitter(3) (5)
0
100 MHz clock input(4)
200 Mbps 215–1 PRBS input(6)
2
3
30
130
7
Disable time, high-level-to-high-impedance output
Disable time, low-level-to-high-impedance output
Enable time, high-impedance-to-high-level output
Enable time, high-impedance-to-low-level output
7
See Figure 6
7
7
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4) tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples.
(5) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
(6) tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples.
Copyright © 2002–2007, Texas Instruments Incorporated
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Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
tpLH
tpHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Output signal rise time
2
2
1
1
4
4
6
6
ns
ns
ns
ns
ps
ps
ns
ps
ps
ps
ns
ns
ns
ns
2.3
2.3
300
500
1
tf
Output signal fall time
CL = 15 pF, See Figure 10
Type 1
Type 2
100
300
tsk(p)
Pulse skew (|tpHL – tpLH|)
Part-to-part skew(2)
tsk(pp)
tjit(per)
Period jitter, rms (1 standard deviation)
100 MHz clock input(4)
4
300
450
7
(3)
Type 1
Type 2
700
800
10
tjit(pp)
Peak-to-peak jitter
200 Mbps 215–1 PRBS input(6)
(3)(5)
tpHZ
tpLZ
tpZH
tpZL
Disable time, high-level-to-high-impedance output
Disable time, low-level-to-high-impedance output
Enable time, high-impedance-to-high-level output
Enable time, high-impedance-to-low-level output
10
See Figure 11
15
15
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4) VID = 200 mVpp (LVD201, 203), VID = 400 mVpp (LVD206, 207), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples.
(5) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
(6) VID = 200 mVpp (LVD201, 203), VID = 400 mVpp (LVD206, 207), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples.
6
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Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
V
CC
I
or I
A
Y
A/Y
B/Z
I
I
D
V
AB
or V
YZ
I
B
or I
Z
V
A
or V
Y
V
I
V
OS
V
B
or V
Z
V
A
+ V
2
V
Y
+ V
2
B
Z
or
Figure 1. Driver Voltage and Current Definitions
3.32 kΩ
A/Y
+
-1 V ≤ V
≤ 3.4 V
V
AB
or V
YZ
49.9 Ω
D
test
_
B/Z
3.32 kΩ
A. All resistors are 1% tolerance.
Figure 2. Differential Output Voltage Test Circuit
A/Y
B/Z
R1
≈ 1.3 V
≈ 0.7 V
24.9 Ω
A/Y
B/Z
C1
1 pF
D
V
V
OS(SS)
OS(PP)
V
OS
C3
2.5 pF
R2
24.9 Ω
V
OS
C2
1 pF
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse frequency = 500
kHz, duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C. R1 and R2 are metal film, surface mount, 1%, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
I
OS
A/Y
B/Z
0 V or V
CC
+
V
-
-1 V or 3.4 V
Test
Figure 4. Driver Short-Circuit Test Circuit
Copyright © 2002–2007, Texas Instruments Incorporated
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SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
A/Y
C1
1 pF
C3
0.5 pF
R1
50 Ω
Output
D
B/Z
C2
1 pF
V
V
CC
/2
CC
Input
0 V
t
t
pHL
pLH
V
SS
0.9V
SS
V
P(H)
Output
0 V
V
P(L)
0.1V
SS
0 V
SS
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz,
duty cycle = 50 5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
R1
24.9 Ω
A/Y
C1
1 pF
D
C4
0.5 pF
0 V or V
Output
CC
C3
2.5 pF
C2
1 pF
B/Z
R2
24.9 Ω
DE
V
V
CC
/2
CC
DE
0 V
t
t
t
pZH
pHZ
0.6 V
0.1 V
Output With
D at V
0 V
CC
t
pZL
pLZ
Output With
D at 0 V
0 V
-0.1 V
-0.6 V
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz,
duty cycle = 50 5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 6. Driver Enable and Disable Time Circuit and Definitions
8
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Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207
SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
www.ti.com
SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
A/Y
0 V or V
CC
B/Z
V , V , V or V
Z
1.62 kΩ , ±1%
A
B
Y
Figure 7. Maximum Steady State Output Voltage
V
V
CC
CLOCK
INPUT
/2
CC
0 V
1/f0
Period Jitter
IDEAL
OUTPUT
V
V
CC
0 V
PRBS INPUT
/2
CC
V
A
-V or V -V
B
Y
Z
1/f0
0 V
ACTUAL
OUTPUT
Peak to Peak Jitter
0 V
V
A
-V or V -V
B Y Z
V
A
-V or V -V
B Y
Z
OUTPUT 0 V Diff
-V or V -V
t
c(n)
V
t
=
t
-1/f0
A
B
Y
Z
jit(per)
c(n)
t
jit(pp)
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 200Mbps 215-1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
I
A
A
B
I
O
R
V
ID
V
O
V
CM
V
A
I
B
(V + V )/2
V
B
A
B
Figure 9. Receiver Voltage and Current Definitions
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SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
Table 1. Type-1 Receiver Input Threshold Test Voltages
APPLIED
VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
RECEIVER
OUTPUT(1)
VIA
VIB
VID
VIC
2.400
0.000
3.800
3.750
–1.350
–1.400
0.000
2.400
3.750
3.800
–1.400
–1.350
2.400
–2.400
0.050
–0.050
0.050
–0.050
1.200
1.200
3.775
3.775
–1.375
–1.375
H
L
H
L
H
L
(1) H = high level, L = low level, output state assumes receiver is enabled (RE = L)
Table 2. Type-2 Receiver Input Threshold Test Voltages
APPLIED
VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
RECEIVER
OUTPUT(1)
VIA
VIB
VID
VIC
2.400
0.000
3.800
3.800
–1.250
–1.350
0.000
2.400
3.650
3.750
–1.400
–1.400
2.400
–2.400
0.150
0.050
0.150
0.050
1.200
1.200
3.725
3.775
–1.325
–1.375
H
L
H
L
H
L
(1) H = high level, L = low level, output state assumes receiver is enabled (RE = L)
V
ID
V
A
C
L
V
O
15 pF
V
B
V
1.2 V
1.0 V
A
V
B
V
ID
0.2 V
0 V
-0.2 V
t
t
pLH
pHL
V
OH
V
O
90%
10%
V
V
/2
CC
OL
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 50 MHz,
duty cycle = 50 5%. CL is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture
capacitance within 2 cm of the D.U.T.
B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 10. Receiver Timing Test Circuit and Waveforms
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SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
R
L
B
A
1.2 V
499 Ω
R
+
C
L
V
TEST
_
V
O
Inputs
RE
15 pF
V
CC
V
TEST
1 V
A
V
V
CC
RE
/2
/2
CC
0 V
t
t
pLZ
pZL
V
CC
V
CC
Output
V
R
V
V
+0.5 V
OL
OL
TEST
0 V
1.4 V
A
V
V
CC
RE
/2
CC
0 V
t
t
pHZ
pZH
V
V
V
OH
-0.5 V
OH
V
O
/2
CC
0 V
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 500 kHz,
duty cycle = 50 5%.
B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
C. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
D. CL is the instrumentation and fixture capacitance within 2 cm of the DUT and 20%.
Figure 11. Receiver Enable/Disable Time Test Circuit and Waveforms
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SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
INPUTS
-V
CLOCK INPUT
V
A
V
IC
B
0.2 V - Type 1
0.4 V - Type 2
1 V
V
A
-V
B
1/f0
Period Jitter
V
OH
IDEAL
OUTPUT
V
A
V /2
CC
PRBS INPUT
V
OL
1/f0
V
B
V
OH
ACTUAL
OUTPUT
Peak to Peak Jitter
V
/2
CC
V
OH
V
OL
OUTPUT
V
/2
t
CC
c(n)
t
=
t
-1/f0
V
OL
jit(per)
c(n)
t
jit(pp)
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 200 Mbps 215-1 PRBS input.
Figure 12. Receiver Jitter Measurement Waveforms
PIN ASSIGNMENTS
SN65MLVD201D (Marked as MF201)
SN65MLVD206D (Marked as MF206)
(TOP VIEW)
SN65MLVD203D (Marked as MLVD203)
SN65MLVD207D (Marked as MLVD207)
(TOP VIEW)
R
RE
DE
D
VCC
B
A
1
2
3
4
8
7
6
5
NC
R
RE
VCC
VCC
A
1
2
3
4
5
6
7
14
13
12
11
10
9
GND
DE
D
B
Z
GND
GND
Y
8
NC
NC - No internal connection
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SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
DEVICE FUNCTION TABLES
TYPE-1 RECEIVER (201, 203)
TYPE-2 RECEIVER (206, 207)
INPUTS
= V - V
OUTPUT
R
INPUTS
= V - V
OUTPUT
R
RE
RE
V
ID
V
ID
A
B
A
B
L
L
H
?
L
Z
Z
L
L
H
?
L
Z
Z
V
≥ 50 mV
V
≥ 150 mV
ID
ID
-50 mV < V < 50 mV
50 mV < V < 150 mV
ID
ID
V
ID
≤ -50 mV
L
V
≤ 50 mV
L
ID
X
X
H
X
X
H
Open
Open
Open Circuit
?
Open Circuit
L
L
L
DRIVER
INPUT ENABLE
OUTPUTS
A OR Y B OR Z
D
DE
L
H
H
H
OPEN
L
L
H
L
Z
Z
H
L
H
Z
Z
H
OPEN
X
X
H = high level, L = low level, Z = high impedance, X = Don’t care, ? = indeterminate
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
DRIVER OUTPUT
DRIVER INPUT AND DRIVER ENABLE
RECEIVER ENABLE
V
CC
V
CC
V
CC
360 kΩ
400 Ω
400 Ω
D or DE
7 V
A/Y or B/Z
RE
7 V
360 kΩ
RECEIVER INPUT
RECEIVER OUTPUT
V
CC
V
CC
100 kΩ
250 kΩ
100 kΩ
250 kΩ
10 Ω
10 Ω
R
A
B
200 kΩ
200 kΩ
7 V
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SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
FREQUENCY
20
16
12
20
16
12
V
T
A
= 3.3 V
= 25°C
CC
Driver
Driver
Receiver
8
4
0
8
4
0
Receiver
Receiver
V
= 3.3 V
= 25°C
Receiver
CC
V
ID
V
IC
= 250 mV
= 1 V
T
V
ID
V
IC
= 250 mV
= 1 V
A
f = 100 MHz
10
30
50
70
90
110
−50 −30
−10
10
30
50
70
90
T
A
− Free-Air Temperature −° C
f − Frequency − MHz
Figure 13.
Figure 14.
RECEIVER LOW-LEVEL OUTPUT CURRENT
RECEIVER HIGH-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
70
60
0
T
A
= 25°C
T
A
= 25°C
−10
V
CC
= 3.6 V
−20
−30
V
V
= 3.3 V
= 3.0 V
CC
50
40
30
CC
V
CC
= 3.0 V
−40
−50
−60
−70
V
CC
= 3.3 V
20
10
0
V
CC
= 3.6 V
−80
−90
0
1
2
3
4
0
1
2
3
4
V
OL
− Low Level Output Voltage − V
V
OH
− High Level Output Voltage − V
Figure 15.
Figure 16.
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SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL OUTPUT VOLTAGE
DRIVER PROPAGATION DELAY
vs
vs
OUTPUT CURRENT
FREE-AIR TEMPERATURE
2
2
V
CC
= 3.3 V
f = 1 MHz
1.6
1.2
0.8
1.8
1.6
1.4
t
pLH
t
pHL
0.4
V
1.2
1
= 3.3 V
= 25°C
CC
T
A
0
−50 −30
−10
10
30
50
70
90
0
2
4
6
8
10
12
T
A
− Free-Air Temperature −° C
I
O
− Output Current − mA
Figure 17.
Figure 18.
ADDED DRIVER CYCLE-TO-CYCLE
RECEIVER PROPAGATION DELAY
vs
JITTER (PEAK)
vs
FREE-AIR TEMPERATURE
FREQUENCY
6
45
V
V
V
= 3.3 V
= 250 mV
= 1 V
V
= 3.3 V
CC
CC
T = 25°C
A
Input = Clock
ID
IC
t
pHL
36
27
f = 1 MHz
4
t
pLH
18
9
2
1
0
10
30
50
70
90
110
−50 −30
−10
10
30
50
70
90
f − Frequency − MHz
T
A
− Free-Air Temperature −° C
Figure 19.
Figure 20.
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SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
ADDED DRIVER PEAK-TO-PEAK JITTER
ADDED DRIVER PEAK-TO-PEAK JITTER
vs
vs
DATA RATE
FREE-AIR TEMPERATURE
60
60
V
CC
= 3.3 V
T
= 25°C
A
15−1
Input = PRBS 2
50
40
50
40
30
30
20
10
20
10
V
= 3.3 V
= 25°C
CC
T
A
15−1
Input = PRBS 2
f = 200 Mbps
0
0
25
65
105
145
185
225
−50 −30 −10
10
30
50
70
90
Data Rate − Mbps
T
A
− Free-Air Temperature −° C
Figure 21.
Figure 22.
ADDED RECEIVER CYCLE-TO-CYCLE JITTER
ADDED RERCEIVER PEAK-TO-PEAK JITTER
vs
vs
FREQUENCY
FREE-AIR TEMPERATURE
35
28
21
400
320
240
V
V
T
= 3.3 V
= 250 mV
= 25°C
CC
V
V
T
A
= 3.3 V
= 250 mV
= 25°C
CC
ID
ID
V
IC
= 3.0 V
A
15−1
Pattern = 2
V
IC
= −0.5 V
V
IC
= 1 V
160
80
0
14
7
0
0
30
60
90
120
150
180 210
10
30
50
70
90
110
Data Rate − Mbps
f − Frequency − MHz
Figure 23.
Figure 24.
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SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
SN65MLVD201 DRIVER OUTPUT
EYE PATTERN
ADDED RECEIVER PEAK-TO-PEAK JITTER
vs
FREE-AIR TEMPERATURE
200 Mbps, 215–1 PRBS, RL = 50 Ω
400
320
240
160
V
V
V
= 3.3 V
= 250 mV
=1 V
CC
ID
IC
80
0
f =200 Mbps
Pattern = 2
15−1
Horizontal Scale = 1 ns/div
−50 −30
−10
10
30
50
70
90
T
A
− Free-Air Temperature −° C
Figure 25.
Figure 26.
SN65MLVD201 RECEIVER OUTPUT
EYE PATTERN
200 Mbps, 215–1 PRBS, RL = 15 Ω
Horizontal Scale = 1 ns/div
Figure 27.
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SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
APPLICATION INFORMATION
Receiver Input Threshold (Failsafe)
The MLVD standard defines a type 1 and type 2 receiver. Type 1 receivers include no provisions for failsafe and
have their differential input voltage thresholds near zero volts. Type 2 receivers have their differential input
voltage thresholds offset from zero volts to detect the absence of a voltage difference. The impact to receiver
output by the offset input can be seen in Table 3 and Figure 28.
Table 3. Receiver Input Voltage Threshold Requirements
RECEIVER TYPE
Type 1
OUTPUT LOW
OUTPUT HIGH
0.05 V ≤ VID ≤ 2.4 V
0.15 V ≤ VID ≤ 2.4 V
–2.4 V ≤ VID ≤ –0.05 V
–2.4 V ≤ VID ≤ 0.05 V
Type 2
Type 1
Type 2
High
200
150
100
50
High
0
Low
-50
Low
-100
Transition Regions
Figure 28. Expanded Graph of Receiver Differential Input Voltage Showing Transition Region
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SLLS558C–DECEMBER 2002–REVISED JANUARY 2007
LIVE INSERTION/GLITCH-FREE POWER UP/DOWN
The SN65MLVD201/203/206/207 family of products offered by Texas Instruments provides a glitch-free
powerup/down feature that prevents the M-LVDS outputs of the device from turning on during a powerup or
powerdown event. This is especially important in live insertion applications, when a device is physically
connected to an M-LVDS multipoint bus and VCC is ramping.
While the M-LVDS interface for these devices is glitch free on powerup/down, the receiver output structure is
not.Figure 29 shows the performance of the receiver output pin, R (CHANNEL 2), as Vcc (CHANNEL 1) is
ramped.
Figure 29. M-LVDS Receiver Output: VCC (CHANNEL 1), R Pin (CHANNEL 2)
The glitch on the R pin is independent of the RE voltage. Any complications or issues from this glitch are easily
resolved in power sequencing or system requirements that suspend operation until VCC has reached a steady
state value.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Jan-2008
PACKAGING INFORMATION
Orderable Device
SN65MLVD201D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65MLVD201DG4
SN65MLVD201DR
SN65MLVD201DRG4
SN65MLVD203D
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
14
14
14
14
8
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65MLVD203DG4
SN65MLVD203DR
SN65MLVD203DRG4
SN65MLVD206D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65MLVD206DG4
SN65MLVD206DR
SN65MLVD206DRE4
SN65MLVD207D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65MLVD207DG4
SN65MLVD207DR
SN65MLVD207DRG4
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jan-2008
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN65MLVD201DR
SN65MLVD203DR
SN65MLVD206DR
SN65MLVD207DR
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
14
8
2500
2500
2500
2500
330.0
330.0
330.0
330.0
12.4
16.4
12.4
16.4
6.4
6.5
6.4
6.5
5.2
9.0
5.2
9.0
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
12.0
16.0
12.0
16.0
Q1
Q1
Q1
Q1
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65MLVD201DR
SN65MLVD203DR
SN65MLVD206DR
SN65MLVD207DR
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
14
8
2500
2500
2500
2500
340.5
333.2
340.5
333.2
338.1
345.9
338.1
345.9
20.6
28.6
20.6
28.6
14
Pack Materials-Page 2
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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
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TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
Automotive
www.ti.com/automotive
www.ti.com/communications
Communications and
Telecom
DSP
dsp.ti.com
Computers and
Peripherals
www.ti.com/computers
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Consumer Electronics
Energy
www.ti.com/consumer-apps
www.ti.com/energy
Logic
Industrial
www.ti.com/industrial
Power Mgmt
Microcontrollers
RFID
power.ti.com
Medical
www.ti.com/medical
microcontroller.ti.com
www.ti-rfid.com
Security
www.ti.com/security
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
Wireless
www.ti.com/video
www.ti.com/wireless-apps
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2010, Texas Instruments Incorporated
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