SN65MLVD205DR [TI]
LINE TRANSCEIVER, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14;
| 型号： | SN65MLVD205DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LINE TRANSCEIVER, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14 驱动器 |
| 文件： | 总23页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
D
D
D
Low-Voltage Differential 30-Ω Line Drivers
and Receivers for Signaling Rates up to
100 Mbps
D
Type-2 Receivers Provide an Offset
(100 mV) Threshold to Detect Open-Circuit
and Idle-Bus Conditions
†
Power Dissipation at 100 Mbps
– Driver: 50 mW Typical
– Receiver: 30 mW Typical
D
D
Operates From a Single 3.3-V Supply
Propagation Delay Times Typically 2.3 ns
for Drivers and 5 ns for Receivers
Meets or Exceeds Current Revision of
M-LVDS Standard TIA/EIA–899 for
Multipoint Data Interchange
D
Power-Up/Down Glitch-Free Driver
D
Driver Handles Operation Into a
Continuous Short Circuit Without Damage
D
D
Controlled Driver Output Voltage Transition
Times for Improved Signal Quality
D
D
Bus Pins High Impedance When Disabled
or V
≤ 1.5 V
CC
–1-V to 3.4-V Common-Mode Voltage Range
Allows Data Transfer With up to 2 V of
Ground Noise
200-Mbps Devices Available
(SN65MLVD201, 203, 206, and 207)
D
Type-1 Receivers Incorporate 25 mV of
Hysteresis
SN65MLVD200D (Marked as MF200)
SN65MLVD204D (Marked as MF204)
(TOP VIEW)
SN65MLVD202D (Marked as MLVD202)
SN65MLVD205D (Marked as MLVD205)
(TOP VIEW)
R
RE
DE
D
V
B
A
1
2
3
4
8
7
6
5
NC
R
V
V
A
B
Z
Y
1
2
3
4
5
6
7
14
13
12
11
10
9
CC
CC
CC
RE
GND
DE
D
GND
GND
8
NC
NC – No internal connection
logic diagram (positive logic)
SN65MLVD200, SN65MLVD204
SN65MLVD202, SN65MLVD205
9
3
Y
DE
5
D
DE
RE
10
Z
4
D
4
3
2
RE
R
12
11
A
B
6
7
2
A
B
1
R
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
The signaling rate of a line is the number of voltage transitions that are made per second expressed in bps (bits per second) units.
Copyright 2001–2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
description
This series of SN65MLVD20x devices are low-voltage differential line drivers and receivers complying with the
proposed multipoint low-voltage differential signaling (M-LVDS) standard (TIA/EIA–899). These circuits are
similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint
applications. Driver output current has been increased to support doubly-terminated, 50-Ω load multipoint
applications. Driver output slew rates are optimized for signaling rates up to 100 Mbps.
Types 1 and 2 receivers are available. Both types of receivers operate over a common-mode voltage range of
–1 V to 3.4 V to provide increased noise immunity in harsh electrical environments. Type-1 receivers have their
differential input voltage thresholds near zero volts (±50 mV), and include 25 mV of hysteresis to prevent output
oscillationsinthepresenceofnoise. Type-2receiversincludeanoffsetthresholdtodetectopen-circuit, idle-bus,
and other fault conditions, and provide a known output state under these conditions.
The intended application of these devices is in half-duplex or multipoint baseband data transmission over
controlled impedance media of approximately 100-Ω characteristic impedance. The transmission media may
be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
application-specific characteristics).
These devices are characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
NOMINAL
SIGNALING RATE,
Mbps
†
FOOTPRINT
RECEIVER TYPE
PART NUMBER
100
100
100
100
SN75176
SN75ALS180
SN75176
Type 1
Type 1
Type 2
Type 2
SN65MLVD200D
SN65MLVD202D
SN65MLVD204D
SN65MLVD205D
SN75ALS180
†
The D package is available taped and reeled. Add the R suffix to the device type (e.g., SN65MLVD200DR)
Function Tables
TYPE-1 RECEIVER (200, 202)
INPUTS OUTPUT
= V – V
TYPE-2 RECEIVER (204, 205)
INPUTS OUTPUT
= V – V
RE
RE
V
ID
R
V
ID
R
A
B
A
B
L
L
H
?
L
Z
Z
L
L
H
?
L
Z
Z
V
≥ 50 mV
V
≥ 150 mV
ID
–50 mV < V < 50 mV
ID
50 mV < V < 150 mV
ID
ID
≤ 50 mV
V
ID
≤ –50 mV
L
V
L
ID
X
X
H
X
X
H
Open
Open
Open Circuit
?
Open Circuit
L
L
L
DRIVER
INPUT ENABLE
OUTPUTS
D
DE
A OR Y
B OR Z
L
H
OPEN
X
X
H
H
H
OPEN
L
L
H
L
Z
Z
H
L
H
Z
Z
H = high level, L = low level, Z = high impedance, X = Don’t care, ? = indeterminate
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
equivalent input and output schematic diagrams
RECEIVER OUTPUT
DRIVER INPUT AND DRIVER ENABLE
RECEIVER ENABLE
V
CC
V
CC
V
CC
360 kΩ
400 Ω
10 Ω
400 Ω
D or DE
7 V
RE
7 V
R
360 kΩ
10 Ω
7 V
RECEIVER INPUT
DRIVER OUTPUT
V
CC
V
CC
100 kΩ
250 kΩ
100 kΩ
250 kΩ
A/Y or B/Z
A
B
200 kΩ
200 kΩ
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
CC
Input voltage range: D, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
A, B (200, 204) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.8 V to 4 V
A, B (202, 205) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –4 V to 6 V
Output voltage range: R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Y, Z, A, or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.8 V to 4 V
Electrostatic discharge: Human body model (see Note 2)
A, B, Y, or Z . . . . . . . . . . . . . . . . . . . . . . ±3 kV
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 kV
Charged-device model (see Note 3) All pins . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see Dissipation Rating table)
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114-A.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
DISSIPATION RATING
T
≤ 25°C
OPERATING FACTOR
T = 85°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
D(8)
725 mW
5.8 mW/°C
7.6 mW/°C
377 mW
D(14)
950 mW
494 mW
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
CC
3
2
3.3
3.6
High-level input voltage, V
IH
V
CC
0.8
V
Low-level input voltage, V
0
V
IL
Magnitude of differential input voltage,
Voltage at any bus terminal, V , V , V
V
0.05
–1.4
–1
V
V
ID
CC
3.8
V
B
V
A
Y
Z, or
Common-mode input voltage V
CM
, (V + V )/2
3.4
15
85
V
A
B
Receiver load capacitance, C
5
pF
°C
L
Operating free-air temperature, T
–40
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
device electrical characteristics over recommended operating conditions (unless otherwise
noted)
†
MIN
‡
PARAMETER
TEST CONDITIONS
RE and DE at V
TYP
MAX
UNIT
,
CC
= 50 Ω, All others open
Receiver disabled and driver enabled
13
1
22
R
L
RE at V , DE at 0 V,
CC
Driver and receiver disabled
7
26
11
R
= No load, All others open
L
I
Supply current
mA
RE at 0 V, DE at V
,
CC
CC
= 50 Ω, All others open,
Receiver enabled and driver enabled
Receiver enabled and driver disabled
R
16
4
L
No receiver load
RE at 0 V, DE at 0 V,
All others open, No receiver load
†
‡
The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
All typical values are at 25°C and with a 3.3-V supply voltage.
driver electrical characteristics over recommended operating conditions (unless otherwise noted)
†
MIN
‡
TYP
PARAMETER
TEST CONDITIONS
MAX
UNIT
V
or
AB
Differential output voltage magnitude
See Figure 2
480
650
mV
V
YZ
∆ V
or
Change in differential output voltage magnitude
between logic states
AB
∆ V
See Figure 2
See Figure 3
–50
0.8
50
1.2
50
mV
V
YZ
V
Steady-state common-mode output voltage
OS(SS)
Change in steady-state common-mode output
voltage between logic states
∆V
OS(SS)
–50
mV
mV
V
V
Peak-to-peak common-mode output voltage
150
2.4
OS(PP)
V
or
or
A(OC)
Maximum steady-state open-circuit output voltage
0
0
V
Y(OC)
See Figure 7
See Figure 5
V
V
B(OC)
Z(OC)
Maximum steady-state open-circuit output voltage
2.4
V
V
Voltage overshoot, low-to-high level output
Voltage overshoot, high-to-low level output
High-level input current
1.2V
V
V
P(H)
P(L)
SS
V
–0.2V
SS
0
I
IH
V
V
= 2 V
10
10
24
µA
µA
mA
IH
I
IL
Low-level input current
= 0.8 V
0
IL
I
Differential short-circuit output current
See Figure 4
OS
–1.4 V ≤ (V or V ) ≤ 3.8 V,
Other output at 1.2 V
Y
Z
I
High-impedance state output current (driver only)
–15
–10
10
µA
OZ
–1.4 V ≤ (V or V ) ≤ 3.8 V,
Y
Z
I
Power-off output current (driver only)
V
≤ 1.5 V,
10
µA
O(OFF)
CC
Other output at 1.2 V
†
‡
The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
All typical values are at 25°C and with a 3.3-V supply voltage.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
50
UNIT
Type 1
Type 2
Type 1
Type 2
Type 1
Type 2
V
V
V
Positive-going differential input voltage threshold
mV
IT+
150
–50
See Figure 8,
Table 1 and Table 2
Negative-going differential input voltage threshold
mV
mV
IT–
50
25
0
Differential input voltage hysteresis, V
– V
IT–
ID(HYS)
IT+
V
V
High-level output voltage
Low-level output voltage
High-level input current
Low-level input current
I
I
= –8 mA
= 8 mA
2.4
V
OH
OH
0.4
0
V
OL
OL
I
I
I
V
V
V
= 2 V
–10
–10
–10
µA
µA
µA
IH
IH
IL
O
= 0.8 V
0
IL
High-impedance output current
= 0 V or 3.6 V
15
OZ
†
All typical values are at 25°C and with a 3.3-V supply voltage.
bus input and output electrical characteritics over recommended operating conditions (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
32
20
0
UNIT
V
= 3.8 V,
V
V
V
= 1.2 V
= 1.2 V
= 1.2 V
= 1.2 V
= 1.2 V
= 1.2 V
0
–20
–32
0
A
B
B
B
Receiver input or transceiver input/output
current
V
A
= 0 V or 2.4 V,
= –1.4 V,
I
A
µA
V
A
V
B
V
B
V
B
= 3.8 V,
V
A
32
20
0
Receiver input or transceiver input/output
current
= 0 V or 2.4 V,
= –1.4 V,
V
A
–20
–32
I
I
µA
µA
B
V
A
Receiver input or transceiver input/output
V
A
= V ,
B
–1.4 ≤ V ≤ 3.8 V
–4
4
AB
A
differential current (I – I )
A
B
V
= 3.8 V,
V
V
V
= 1.2 V,
= 1.2 V,
= 1.2 V,
= 1.2 V,
= 1.2 V,
= 1.2 V,
V
V
V
≤ 1.5 V
≤ 1.5 V
≤ 1.5 V
≤ 1.5 V
≤ 1.5 V
≤ 1.5 V
0
–20
–32
0
32
20
0
A
B
B
B
CC
CC
CC
CC
CC
CC
Receiver input or transceiver input/output
power-off current
V
A
= 0 V or 2.4 V,
= –1.4 V,
I
µA
A(OFF)
V
A
V
= 3.8 V,
V
A
V
V
V
32
20
0
B
B
B
Receiver input or transceiver input/output
power-off current
V
V
= 0 V or 2.4 V,
= –1.4 V,
V
A
–20
–32
I
I
µA
µA
B(OFF)
V
A
Receiver input or transceiver input/output
V
A
= V ,
B
–1.4 ≤ V ≤ 3.8 V,
V ≤ 1.5 V
CC
–4
4
AB(OFF)
A
power-off differential current (I – I )
A
B
Receiver input, driver high-impedance
output, or transceiver input/output
capacitance
C
C
V
= 0.4 sin(2E8πt) +0.5,
= 0.4 sin(2E8πt) +0.5,
V
= 1.2 V
V = 1.2 V
A
3
3
pF
pF
A
B
A
B
V
B
†
All typical values are at 25°C and with a 3.3-V supply voltage.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
†
PARAMETER
TEST CONDITIONS
MIN
1.6
1.6
1.5
1.5
TYP
MAX
4.1
4.1
3
UNIT
ns
t
t
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
2.3
2.3
2
PLH
PHL
r
ns
ns
See Figure 5
Differential output signal fall time
2
3
ns
f
Pulse skew (|t
–- t |)
PLH
30
ps
sk(p)
sk(pp)
PZH
PZL
PHZ
PLZ
PHL
Part-to-part skew (see Note 4)
900
6.5
6.5
6.8
6.1
ps
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
1.5
1.5
1.3
1.8
3.7
3.7
3.5
3.5
ns
ns
See Figure 6
ns
ns
50-MHz clock input
(see Figure 8)
t
t
t
Period jitter, rms (1 standard deviation) (see Notes 5 and 6)
Cycle-to-cycle jitter, peak (see Notes 5 and 6)
Peak-to-peak jitter, (see Notes 5, 7, and 8)
23
180
210
ps
ps
ps
jit(per)
jit(cc)
jit(pp)
50-MHz clock input
(see Figure 8)
15
100 Mbps 2 –1 PRBS
input (see Figure 8)
†
All typical values are at 25°C and with a 3.3-V supply voltage.
NOTES: 4. t is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both
sk(pp)
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
5. Jitterparametersarebasedondesignandcharacterization. Stimulussystemjitterof11 ps t , 43 ps t , or 54 ps t have
jit(pp)
jit(per)
jit(cc)
been subtracted from the values.
6. Input voltage = 0 V to V , t = t ≤ 1 ns (20% to 80%), measured over 30k samples.
CC
r
f
7. Input voltage = 0 V to V , t = t ≤ 1 ns (20% to 80%), measured over 100k samples.
CC
r
f
8. Peak-to-peak jitter includes jitter due to pulse skew (t
).
sk(p)
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
6.7
UNIT
ns
ns
ps
ns
ns
ns
ns
ns
ps
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
3
5
PLH
PHL
sk(p)
sk(pp)
r
3
4.6
6.7
Pulse skew (|t
–- t
|)
PLH
400
PHL
C
= 5 pF, See Figure 10
L
Part-to-part skew (see Note 9)
1.5
2
Output signal rise time
0.8
0.8
3.4
3.4
1.4
1.5
5.8
5.4
400
Output signal fall time
2
f
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
9
PLH
PHL
sk(p)
sk(pp)
r
9
Pulse skew (|t
–- t
|)
PLH
PHL
C
= 15 pF, See Figure 10
L
Part-to-part skew (see Note 9)
Output signal rise time
2.5
2.6
2.6
1
1
2
Output signal fall time
1.4
f
Propagation delay time, high-level-to-high-impedance
output
t
t
t
t
4.5
2
6
3.4
9.8
8.7
15
5
ns
ns
ns
ns
PHZ
PLZ
PZH
PZL
Propagation delay time, low-level-to-high-impedance
output
See Figure 11
Propagation delay time, high-impedance-to-high-level
output
3.5
4
15
15
Propagation delay time, high-impedance-to-low-level
output
Type 1
Type 2
Type 1
Type 2
Type 1
Type 2
10
10
Period jitter, rms (1 standard deviation)
(see Notes 10 and 11)
50-MHz clock input
(see Figure 12)
t
t
t
ps
ps
ps
jit(per)
jit(cc)
jit(pp)
93
50-MHz clock input
(see Figure 12)
Cycle-to-cycle jitter, peak (see Notes 10 and 11)
Peak-to-peak jitter, (see Notes 10, 12, and 13)
86
15
850
790
100 Mbps 2 –1 PRBS
input (see Figure 12)
†
All typical values are at 25°C and with a 3.3-V supply voltage.
NOTES: 9. t is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both
sk(pp)
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
10. Jitterparametersarebasedondesignandcharacterization. Stimulussystemjitterof11 ps t , 43 ps t , or 54 ps t have
jit(pp)
jit(per)
jit(cc)
been subtracted from the values.
11. Differential input voltage = 250 mV
samples.
12. Differential input voltage = 250 mV
samples.
(Type 1) or 500 mV
(Type 2), V = 1 V, t = t ≤ 1 ns (20% to 80%), measured over 30k
CM r f
p–p
p–p
p–p
p–p
(Type 1) or 500 mV
(Type 2), V = 1 V, t = t ≤ 1 ns (20% to 80%), measured over 100k
CM r f
13. Peak-to-peak jitter includes jitter due to pulse skew (t
).
sk(p)
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
I
A
or I
Y
A/Y
I
I
D
V
or V
or V
I
B
or I
AB
YZ
Z
V
A
or V
Y
B/Z
V
I
V
OS
V
B
Z
V
A
+ V
2
V
Y
+ V
2
B
Z
or
Figure 1. Driver Voltage and Current Definitions
3.32 kΩ
A/Y
+
–1 V ≤ V
≤ 3.4 V
V
AB
or V
YZ
49.9 Ω
D
test
_
B/Z
3.32 kΩ
NOTE: All resistors are 1% tolerance.
Figure 2. Differential Output Voltage Test Circuit
A/Y
B/Z
≈ 1.3 V
≈ 0.7 V
24.9 Ω ±1%
A/Y
B/Z
D
V
V
OS(SS)
OS(PP)
C
L
V
OS
2 pF
V
OS
24.9 Ω ±1%
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤1 ns, pulse repetition rate (PRR) = 0.25 Mpps,
r
f
pulse width = 500 ±10 ns. C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of V
is made on test equipment with a –3-dB bandwidth of at least 1 GHz.
L
OS(PP)
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
I
OS
A/Y
B/Z
0 V or V
CC
+
V
Test
–1 V or 3.4 V
–
Figure 4. Driver Short-Circuit Test Circuit
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
A/Y
C
L
0.5 pF
Output
49.9 Ω ±1%
D
(Metal Film Surface Mount)
B/Z
V
V
CC
/2
Input
CC
0 V
t
t
PHL
PLH
V
SS
0.9V
SS
V
P(H)
0 V
Output
V
P(L)
0.1V
SS
0 V
SS
t
t
r
f
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤1 ns, pulse repetition rate (PRR) = 1 Mpps,
r
f
pulse width = 0.5 ±0.05 µs. C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
24.9 Ω ±1%
(2 Places)
A/Y
C
L
0.5 pF
0 V or V
Output
CC
B/Z
+
1 V
DE
V
CC
V
CC
/2
DE
0 V
t
t
t
PZH
PHZ
PLZ
0.6 V
0.1 V
Output With
D at V
0 V
CC
t
PZL
Output With
D at 0 V
0 V
–0.1 V
–0.6 V
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤1 ns, pulse repetition rate (PRR) = 0.25 Mpps,
r
f
pulse width = 500 ±10 ns. C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
Figure 6. Driver Enable and DIsable Time Circuit and Definitions
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
A/Y
0 V or V
CC
B/Z
V , V , V or V
Z
1.62 kΩ
A
B
Y
C
Figure 7. Maximum Steady-State Output Voltage Test Circuit
OUTPUT
0 V DIFF
V
CC
CLOCK
INPUT
V
/2
CC
V
A
–V or V –V
B Y Z
0 V
t
t
c(n+1)
c(n)
1/f0
t
= | t
– t |
c(n) c(n+1)
jit(cc)
Period Jitter
IDEAL
V
V
CC
0 V
OUTPUT
–V or V –V
Z
PRBS INPUT
/2
CC
V
A
1/f0
0 V
B
Y
Peak to Peak Jitter
ACTUAL
OUTPUT
0 V
V
A
– V or V – V
Z
B
Y
OUTPUT 0 V Diff
V
A
–V or V –V
B Y Z
t
c(n)
t
= t
–1/f0
c(n)
jit(per)
t
jit(pp)
NOTES: A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input.
15
D. Peak-to-peak jitter is measured using a 200Mbps 2 –1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
I
A
A
B
I
O
R
V
ID
I
B
V
O
V
CM
V
A
(V + V )/2
A
B
V
B
Figure 9. Receiver Voltage and Current Definitions
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
Table 1. Type-1 Receiver Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
APPLIED VOLTAGES
RECEIVER OUTPUT
V
A
V
B
V
ID
V
CM
V
O
3.425 V
3.375 V
–0.975 V
–1.025 V
3.800 V
3.000 V
–0.600 V
–1.400 V
3.375 V
3.425 V
–1.025 V
–0.975 V
3.000 V
3.800 V
–1.400 V
–0.600 V
50 mV
–50 mV
50 mV
3.4 V
3.4 V
H
L
H
L
–1.0 V
–1.0 V
3.4 V
–50 mV
800 mV
–800 mV
800 mV
–800 mV
H
L
3.4 V
–1.0 V
–1.0 V
H
L
NOTE: H= high level, L = low level. Output state assumes receiver is enabled (RE is Low).
Table 2. Type-2 Receiver Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON–
MODE INPUT VOLTAGE
APPLIED VOLTAGES
RECEIVER OUTPUT
V
A
V
B
V
ID
V
CM
V
O
3.475 V
3.425 V
–0.925 V
–0.975 V
3.800 V
3.000 V
–0.600 V
–1.400 V
3.325 V
3.375 V
–1.075 V
–1.025 V
3.000 V
3.800 V
–1.400 V
–0.600 V
150 mV
50 mV
3.4 V
3.4 V
H
L
H
L
150 mV
50 mV
–1.0 V
–1.0 V
3.4 V
800 mV
–800 mV
800 mV
–800 mV
H
L
3.4 V
–1.0 V
–1.0 V
H
L
NOTE: H= high level, L = low level. Output state assumes receiver is enabled (RE is Low).
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
R1
453 Ω
V
ID
R2
49.9 Ω
C
V
O
L
V
A
V
B
V
1.1 V
0.9 V
V
1.2 V
0.8 V
A
A
V
B
V
B
0.2 V
0 V
0.4 V
0.1 V
V
ID
V
ID
–0.2 V
–0.4 V
t
t
t
t
PLH
pHL
pLH
PHL
0.1 V
0.1 V
OH
OH
90%
10%
90%
10%
0.1 V /2
CC
0.1 V
0.1 V /2
V
O
V
O
CC
0.1 V
OL
OL
t
t
t
t
r
f
r
f
Type 1
Type 2
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t ≤1 ns, pulse repetition rate (PRR) = 1 Mpps,
r
f
pulse width = 0.5 ±0.05 µs.
B. Resistors are 1% tolerance, metal film, and surface mount.
C.
C is 20% tolerance, low-loss ceramic, and surface mount.
L
D. R1 and C are located within 2 cm of the D.U.T.
E. R2 is located within 15 cm of the D.U.T.
L
Figure 10. Receiver Timing Test Circuit and Waveforms
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
B
A
500 Ω ±1%
1.2 V
R
C
L
+
_
V
test
Output
Inputs
5 pF
RE
V
CC
V
TEST
1 V
A
Inputs
V
V
CC
RE
/2
/2
CC
0 V
t
t
PLZ
PZL
V
CC
V
CC
Output
R
V
OL
V
OL
+0.5 V
V
0 V
1.4 V
TEST
A
Inputs
V
V
CC
RE
/2
CC
0 V
t
t
PHZ
PZH
V
V
V
OH
OH
CC
–0.5 V
/2
Output
R
0 V
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤1 ns, pulse repetition rate (PRR) = 0.25 Mpps,
r
f
pulse width = 500 ±10 ns. C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
Figure 11. Receiver Enable/Disable Time Test Circuit and Waveforms
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
V
OH
OUTPUT
/2
INPUTS
– V
0.25 V – Type 1 1 V
0.5 V – Type 2
CLOCK INPUT
V
A
V
IC
B
V
CC
V
A
– V
B
V
1/f0
OL
t
t
c(n+1)
c(n)
Period Jitter
t
= | t
– t |
c(n) c(n+1)
jit(cc)
V
IDEAL
OUTPUT
OH
V
A
V
CC
/2
PRBS INPUT
V
OL
1/f0
V
B
V
OH
Peak to Peak Jitter
ACTUAL
OUTPUT
V
CC
/2
V
OH
V
OL
OUTPUT
V
/2
CC
t
c(n)
= t
V
OL
t
–1/f0
c(n)
jit(per)
t
jit(pp)
NOTES: A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input.
15
D. Peak-to-peak jitter is measured using a 200Mbps 2 –1 PRBS input.
Figure 12. Receiver Jitter Measurement Waveforms
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
DRIVER LOW-TO-HIGH PROPAGATION DELAY
DRIVER HIGH-TO-LOW PROPAGATION DELAY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
2.5
2.5
See Figure 5
See Figure 5
V
CC
= 3 V
V
CC
= 3 V
2.4
2.3
2.4
2.3
V
CC
= 3.3 V
V
CC
= 3.3 V
V
CC
= 3.6 V
V
CC
= 3.6 V
2.2
2.1
2.2
2.1
–50
0
50
100
–50
0
50
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 13
Figure 14
RECEIVER LOW-TO-HIGH PROPAGATION DELAY
RECEIVER HIGH-TO-LOW PROPAGATION DELAY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5.5
5.5
C
= 5 pF
L
C = 5 pF
L
See Figure 9
V
CC
= 3 V
See Figure 9
V
CC
= 3 V
V
CC
= 3.3 V
5
4.5
4
5
V
CC
= 3.3 V
V
= 3.6 V
CC
4.5
V
= 3.6 V
CC
4
–50
–50
0
50
100
0
50
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 15
Figure 16
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
DRIVER LOW-LEVEL OUTPUT CURRENT
DRIVER HIGH-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
5
0
15
10
5
T
= 25 °C
A
T
= 25 °C
A
V
CC
= 3.3 V
V
CC
= 3.3 V
–5
–10
0
–5
–15
–1
0
1
2
3
4
–1
0
1
2
3
4
V
OL
– Low-Level Output Voltage – V
V
OH
– High-Level Output Voltage – V
Figure 17
Figure 18
RECEIVER LOW-LEVEL OUTPUT CURRENT
RECEIVER HIGH-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
20
0
120
100
T
= 25 °C
T
= 25 °C
A
A
V
CC
= 3.3 V
V
CC
= 3.3 V
80
60
40
20
0
–20
–40
–60
–80
0
0.5
V
1
1.5
2
2.5
3
3.5
4
0
0.5
V
1
1.5
2
2.5
3
3.5
4
– High-Level Output Voltage – V
– Low-Level Output Voltage – V
OH
OL
Figure 19
Figure 20
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
AVERAGE DRIVER SUPPLY CURRENT
DIFFERENTIAL OUTPUT VOLTAGE
vs
vs
FREQUENCY
OUTPUT CURRENT
2
17
16
15
14
50% Duty Cycle
R
= 50 Ω
= 25°C
L
T
A
V
CC
= 3.6 V
See Figure 5
1.6
1.2
V
CC
= 3.3 V
V
CC
= 3 V
0.8
0.4
0
13
12
V
T
A
= 3.3 V
2
CC
= 25°C
Note: 100 MHz = 200 Mbps
25 50
0
75
100
0
4
6
8
10
12
f – Frequency – MHz
I
O
– Output Current – mA
Figure 21
Figure 22
AVERAGE RECEIVER SUPPLY CURRENT
ADDED DRIVER PERIOD JITTER (1 SIGMA)
vs
vs
FREQUENCY
CLOCK FREQUENCY
20
15
10
50
50% Duty Cycle
R
C
T
= 500 Ω
= 5 pF
= 25°C
V
T
A
= 3.3 V,
CC
= 25°C,
Input = Clock
L
L
A
40
V
= 3.6 V
CC
CC
See Figure 9
V
CC
= 3.3 V
30
20
10
0
V
= 3 V
5
0
Note: 100 MHz = 200 Mbps
25 50
0
75
100
10
20
30
40
50
f – Frequency – MHz
f – Clock Frequency – MHz
Figure 23
Figure 24
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
ADDED TYPE 1 RECEIVER PERIOD JITTER (1 SIGMA)
ADDED TYPE 2 RECEIVER PERIOD JITTER (1 SIGMA)
vs
vs
CLOCK FREQUENCY
25
CLOCK FREQUENCY
25
V
= 3.3 V,
CC
= 25°C,
V
= 3.3 V,
CC
T = 25°C,
A
T
A
Input = Clock,
= 250 mV
20
15
10
20
15
Input = Clock,
V = 500 mV
ID
V
ID
V
IC
= –0.5 V
V
IC
= 3 V
V
IC
= 1 V
10
V
IC
= 3 V
V
= –0.5 V
V
= 1 V
IC
IC
5
0
5
0
10
10
20
30
40
50
20
30
40
50
f – Clock Frequency – MHz
f – Clock Frequency – MHz
Figure 25
Figure 26
ADDED TYPE 1 RECEIVER CYCLE-TO-CYCLE
JITTER (PEAK)
vs
ADDED DRIVER CYCLE-TO-CYCLE JITTER (PEAK)
vs
CLOCK FREQUENCY
CLOCK FREQUENCY
250
200
150
250
200
150
100
50
V
= 3.3 V,
CC
= 25°C,
V
= 3.3 V,
CC
= 25°C,
T
A
T
A
Input = Clock,
= 250 mV
Input = Clock
V
ID
V
IC
= –0.5 V
V
= 3 V
IC
100
50
0
V
IC
= 1 V
0
10
20
30
40
50
10
20
30
40
50
f – Clock Frequency – MHz
f – Clock Frequency – MHz
Figure 27
Figure 28
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
ADDED TYPE 2 RECEIVER CYCLE-TO-CYCLE
ADDED DRIVER PEAK-TO-PEAK JITTER
JITTER (PEAK)
vs
CLOCK FREQUENCY
vs
DATA RATE
250
200
150
100
50
250
200
150
V
= 3.3 V,
CC
T = 25°C,
A
V
= 3.3 V,
CC
= 25°C,
T
15
Input = PRBS(2 – 1)
A
Input = Clock,
= 500 mV
V
ID
V
IC
= 1 V
V
= –0.5 V
IC
100
50
0
V
= 3 V
IC
0
20
40
60
80
100
10
20
30
40
50
Data Rate – Mbps
f – Clock Frequency – MHz
Figure 29
Figure 30
ADDED TYPE 2 RECEIVER PEAK-TO-PEAK JITTER
ADDED TYPE 1 RECEIVER PEAK-TO-PEAK JITTER
vs
vs
DATA RATE
DATA RATE
2000
1600
1200
800
2000
1600
1200
800
V
= 3.3 V,
CC
= 25°C,
V
= 3.3 V,
CC
= 25°C,
T
A
T
A
15
Input = PRBS(2 – 1),
15
Input = PRBS(2 – 1),
V
ID
= 500 mV
V
ID
= 250 mV
400
0
400
0
20
40
60
80
100
20
40
60
80
100
Data Rate – Mbps
Data Rate – Mbps
Figure 31
Figure 32
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
APPLICATION INFORMATION
Type-1 and Type-2 receivers
The M-LVDS standard defines Type-1 and Type-2 receivers. Type-1 receivers include no provisions for failsafe
and have their differential input voltage thresholds near zero volts. Type-2 receivers have their differential input
voltage thresholds offset from zero volts to detect the absence of a voltage difference. Type-1 receivers
maximize the differential noise margin and are intended for maximum signaling rates. Type-2 receivers are
intended for control signals and slower signaling rates. The impact on receiver output by the offset input can
be seen in Table 3 and Figure 33.
Table 3. M-LVDS Receiver Input Voltage Threshold Requirements
Receiver Type
Output Low
Output High
0.05 V ≤ V ≤ 2.4 V
1
2
–2.4 V ≤ V ≤ –0.05 V
ID
–2.4 V ≤ V ≤ 0.05 V
ID
0.15 V ≤ V ≤ 2.4 V
ID
ID
Type 1
Type 2
High
200
150
100
50
High
0
Low
–50
–100
Low
Transition Regions
Figure 33. Receiver Differential Input Voltage Showing Transition Region
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65MLVD200, SN65MLVD202
SN65MLVD204, SN65MLVD205
MULTIPOINT–LVDS LINE DRIVERS AND RECEIVERS
SLLS463E – SEPTEMBER 2001 – REVISED JUNE 2003
APPLICATION INFORMATION
comparison of M-LVDS with RS-485
RS-485 applications are similar to M-LVDS. The two standards define balanced multipoint systems with some
basic architecture changes due to the different applications. Table 4 gives a high-level comparison of the two
different technologies.
Table 4. Comparison Between M-LVDS and RS-485 Standards
Differential Voltage
Range
Common-Mode
Voltage Range
Maximum Signaling Receiver Minimum
Number of Loads
Rate (Mbps)
Threshold
±200 mV
±50 mV
RS-485
M-LVDS
32
32
1.5 V to 5 V
–7 V to 12 V
–1 V to 3.4 V
50 Mbps
480 mV to 650 mV
500 Mbps
It can be seen that with the greater differential output voltage and common-mode voltage range of the
RS-485-type device, it can handle longer signaling distances where M-LVDS offers ten times the signaling rate
of RS-485.
SN65MLVD200
SN65MLVD200
R
R
T
T
Up to 32
Transceivers
NOTE A: The line should be terminated at both ends in its characteristic impedance (R = Z ). Stub lengths off the main line should be kept
T
O
as short as possible.
Figure 34. Typical Application Circuit
22
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