SN7407DE4 [TI]
HEX BUFFERS DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS; 具有集电极开路高压输出HEX缓冲区DRIVERS
| 型号： | SN7407DE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HEX BUFFERS DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS |
| 文件： | 总17页 (文件大小：1044K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SDLS032G − DECEMBER 1983 − REVISED MAY 2004
SN5407, SN5417 . . . J OR W PACKAGE
SN7407, SN7417 . . . D, N, OR NS PACKAGE
(TOP VIEW)
D
D
D
D
D
Convert TTL Voltage Levels to MOS Levels
High Sink-Current Capability
Input Clamping Diodes Simplify System
Design
1
2
3
4
5
6
7
14
13
12
11
10
9
V
1A
1Y
2A
2Y
3A
CC
6A
6Y
5A
5Y
4A
4Y
Open-Collector Driver for Indicator Lamps
and Relays
Inputs Fully Compatible With Most TTL
Circuits
3Y
GND
8
description/ordering information
These TTL hex buffers/drivers feature
high-voltage open-collector outputs for interfacing
with high-level circuits (such as MOS) or for
driving high-current loads (such as lamps or
relays) and also are characterized for use as
buffers for driving TTL inputs. The SN5407 and
SN7407 have minimum breakdown voltages of
30 V, and the SN5417 and SN7417 have
minimum breakdown voltages of 15 V. The
maximum sink current is 30 mA for the SN5407
and SN5417 and 40 mA for the SN7407 and
SN7417.
SN5407 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
18
6Y
NC
5A
2A
NC
2Y
4
5
6
7
8
17
16
15 NC
14
NC
3A
5Y
9 10 11 12 13
These devices perform the Boolean function
Y = A in positive logic.
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
Tube
SN7407D
7407
7417
Tape and reel
Tube
SN7407DR
SN7417D
SOIC − D
Tape and reel
SN7417DR
SN7407N
0°C to 70°C
SN7407N
SN7417N
SN7407
PDIP − N
Tube
SN7417N
SN7407NSR
SN7417NSR
SNJ5407J
SNJ5417J
SNJ5407W
SNJ5407FK
SOP − NS
Tape and reel
SN7417
SNJ5407J
SNJ5417J
SNJ5407W
SNJ5407FK
CDIP − J
CFP − W
Tube
Tube
−55°C to 125°C
LCCC − FK Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SDLS032G − DECEMBER 1983 − REVISED MAY 2004
description/ordering information (continued)
These circuits are completely compatible with most TTL families. Inputs are diode clamped to minimize
transmission-line effects, which simplifies design. Typical power dissipation is 145 mW, and average
propagation delay time is 14 ns.
logic diagram, each buffer/driver (positive logic)
A
Y
schematic
V
CC
6 kΩ
3.4 kΩ
1.6 kΩ
Input A
Output Y
100 Ω
1 kΩ
GND
Resistor values shown are nominal.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
Output voltage, V (see Notes 1 and 2): SN5407, SN7407 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
O
SN5417, SN7417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. This is the maximum voltage that should be applied to any output when it is in the off state.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SDLS032G − DECEMBER 1983 − REVISED MAY 2004
recommended operating conditions (see Note 4)
MIN NOM
MAX
5.5
UNIT
SN5407, SN5417
SN7407, SN7417
4.5
4.75
2
5
5
V
CC
Supply voltage
V
5.25
V
V
High-level input voltage
Low-level input voltage
V
V
IH
0.8
30
IL
SN5407, SN7407
SN5417, SN7417
SN5407, SN5417
SN7407, SN7417
SN5407, SN5417
SN7407, SN7417
V
High-level output voltage
Low-level output current
Operating free-air temperature
V
OH
15
30
I
mA
°C
OL
40
−55
0
125
70
T
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
†
PARAMETER
MIN TYP
MAX
−1.5
0.25
0.25
0.4
0.7
0.7
1
UNIT
TEST CONDITIONS
V
IK
V
V
= MIN,
= MIN,
I = −12 mA
V
CC
I
V
V
= 30 V (SN5407, SN7407)
= 15 V (SN5417, SN7417)
OH
I
V
= 2 V
mA
OH
CC
IH
OH
I
I
I
= 16 mA
OL
OL
OL
= 30 mA (SN5407, SN5417)
= 40 mA (SN7407, SN7417)
V
OL
V
CC
= MIN,
V
= 0.8 V
V
IL
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX,
= MAX,
= MAX,
= MAX
= MAX
V = 5.5 V
mA
µA
I
I
V
= 2.4 V
= 0.4 V
40
IH
IH
IL
V
−1.6
41
mA
mA
mA
IL
29
21
CCH
CCL
30
†
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
CC
A
switching characteristics, V
= 5 V, T = 25°C (see Figure 1)
CC
A
FROM
PARAMETER
TO
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
(INPUT)
t
t
t
t
6
10
30
15
26
PLH
PHL
PLH
PHL
Y
R
R
= 110 Ω,
= 150 Ω,
C
C
= 15 pF
= 50 pF
A
A
L
L
L
L
20
Y
ns
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SDLS032G − DECEMBER 1983 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
R
L
From Output
Under Test
Test Point
C
L
(see Note A)
LOAD CIRCUIT
3 V
0 V
1.5 V
1.5 V
Input
t
t
t
PHL
PLH
PHL
V
V
OH
In-Phase
Output
High-Level
Pulse
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
OL
t
t
PLH
w
V
V
OH
Low-Level
Pulse
Out-of-Phase
Output
1.5 V
OL
VOLTAGE WAVEFORMS
PULSE WIDTHS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A.
B. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 7 ns, t ≤ 7 ns.
C includes probe and jig capacitance.
L
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
JM38510/00803BCA
JM38510/00803BDA
M38510/00803BCA
M38510/00803BDA
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
CDIP
CFP
CDIP
CFP
J
14
14
14
14
1
TBD
TBD
TBD
TBD
A42
A42
A42
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
JM38510/
00803BCA
ACTIVE
ACTIVE
ACTIVE
W
J
1
1
1
JM38510/
00803BDA
JM38510/
00803BCA
W
JM38510/
00803BDA
SN5407J
SN5417J
SN7407D
ACTIVE
ACTIVE
ACTIVE
CDIP
CDIP
SOIC
J
J
14
14
14
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
-55 to 125
-55 to 125
0 to 70
SN5407J
SN5417J
7407
D
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
SN7407DE4
SN7407DG4
SN7407DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
7407
7407
7407
7407
7407
50
Green (RoHS
& no Sb/Br)
2500
2500
2500
Green (RoHS
& no Sb/Br)
SN7407DRE4
SN7407DRG4
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN7407J
SN7407N
OBSOLETE
ACTIVE
CDIP
PDIP
J
14
14
TBD
Call TI
Call TI
0 to 70
0 to 70
N
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN7407N
SN7407N3
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
14
14
TBD
Call TI
Call TI
0 to 70
0 to 70
SN7407NE4
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN7407N
SN7407
SN7407
SN7407NSR
ACTIVE
ACTIVE
SO
SO
NS
NS
14
14
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
SN7407NSRE4
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
SN7407NSRG4
SN7417D
ACTIVE
SO
NS
14
14
14
14
14
14
14
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SN7407
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
D
D
D
D
D
D
N
50
50
Green (RoHS
& no Sb/Br)
0 to 70
7417
SN7417DE4
SN7417DG4
SN7417DR
Green (RoHS
& no Sb/Br)
0 to 70
7417
50
Green (RoHS
& no Sb/Br)
0 to 70
7417
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
0 to 70
7417
SN7417DRE4
SN7417DRG4
SN7417N
Green (RoHS
& no Sb/Br)
0 to 70
7417
Green (RoHS
& no Sb/Br)
0 to 70
7417
Pb-Free
(RoHS)
0 to 70
SN7417N
SN7417N3
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
14
14
TBD
Call TI
Call TI
0 to 70
0 to 70
SN7417NE4
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN7417N
SNJ5407FK
SNJ5407J
SNJ5407W
SNJ5417J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
14
1
1
1
1
TBD
TBD
TBD
TBD
POST-PLATE
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
SNJ5407FK
SNJ5407J
SNJ5407W
SNJ5417J
A42
A42
A42
W
J
CDIP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN5407, SN5417, SN7407, SN7417 :
Catalog: SN7407, SN7417
•
Military: SN5407, SN5417
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN7407DR
SN7407DR
SN7407NSR
SN7417DR
SOIC
SOIC
SO
D
D
14
14
14
14
2500
2500
2000
2500
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
6.55
6.5
8.2
6.5
9.05
9.0
2.1
2.1
2.5
2.1
8.0
8.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
NS
D
10.5
9.0
12.0
8.0
SOIC
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN7407DR
SN7407DR
SN7407NSR
SN7417DR
SOIC
SOIC
SO
D
D
14
14
14
14
2500
2500
2000
2500
385.0
333.2
367.0
367.0
388.0
345.9
367.0
367.0
194.0
28.6
38.0
38.0
NS
D
SOIC
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
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harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
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In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
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requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
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Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
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which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
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www.ti.com/audio
amplifier.ti.com
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
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