SN7414N-10 [TI]
IC TTL/H/L SERIES, HEX 1-INPUT INVERT GATE, PDIP14, Gate;
| 型号： | SN7414N-10 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC TTL/H/L SERIES, HEX 1-INPUT INVERT GATE, PDIP14, Gate 栅 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总27页 (文件大小：980K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
SN5414, SN54LS14 . . . J OR W PACKAGE
SN7414 . . . D, N, OR NS PACKAGE
SN74LS14 . . . D, DB, OR N PACKAGE
(TOP VIEW)
Operation From Very Slow Edges
Improved Line-Receiving Characteristics
High Noise Immunity
1A
1Y
2A
2Y
3A
V
CC
1
2
3
4
5
6
7
14
13
12
11
description
6A
6Y
5A
Each circuit functions as an inverter, but because
of the Schmitt action, it has different input
threshold levels for positive-going (V ) and
T+
10 5Y
negative-going (V ) signals.
T–
3Y
GND
4A
4Y
9
8
These circuits are temperature compensated and
can be triggered from the slowest of input ramps
and still give clean, jitter-free output signals.
SN54LS14 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
6Y
NC
5A
NC
2A
NC
2Y
4
5
6
7
8
17
16
15
NC
3A
14 5Y
9 10 11 12 13
NC – No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN7414N
SN7414N
PDIP – N
SOIC – D
Tube
SN74LS14N
SN7414D
SN74LS14N
Tube
7414
Tape and reel
Tube
SN7414DR
0°C to 70°C
SN74LS14D
SN74LS14DR
SN7414NSR
SN74LS14DBR
SN5414J
LS14
Tape and reel
Tape and reel
Tape and reel
Tube
SOP – NS
SN7414
SSOP – DB
LS14
SN5414J
Tube
SNJ5414J
SNJ5414J
SN54LS14J
SNJ54LS14J
SNJ5414W
SNJ54LS14W
SNJ54LS14FK
CDIP – J
Tube
SN54LS14J
SNJ54LS14J
SNJ5414W
–55°C to 125°C
Tube
Tube
CFP – W
Tube
SNJ54LS14W
SNJ54LS14FK
LCCC – FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
logic diagram (positive logic)
2
4
1
3
1A
1Y
2Y
3Y
4Y
5Y
6Y
2A
3A
4A
5A
6A
6
5
9
8
10
12
11
13
Y = A
Pin numbers shown are for the D, DB, J, N, NS, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
schematic
’14
V
CC
100 Ω
6 kΩ
Output Y
Input A
GND
’LS14
V
CC
20 kΩ
Output Y
Input A
GND
Resistor values shown are nominal.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage: ’14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
’LS14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, θ (see Note 2):D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperaturerange, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7
recommended operating conditions
SN5414
MIN NOM
SN7414
UNIT
MAX
5.5
MIN NOM
MAX
5.25
–0.8
16
V
Supply voltage
4.5
5
4.75
5
V
CC
OH
OL
I
I
High-level output current
Low-level output current
Operating free-air temperature
–0.8
16
mA
mA
°C
T
A
–55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN5414
SN7414
‡
PARAMETER
UNIT
TEST CONDITIONS
§
MIN TYP
MAX
2
V
V
V
V
= 5 V
= 5 V
1.5
0.6
1.7
0.9
V
V
T+
CC
1.1
T–
CC
Hysteresis
(V – V
V
CC
= 5 V
0.4
0.8
V
)
T–
T+
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MIN,
= MIN,
= MIN,
= 5 V,
I = –12 mA
–1.5
V
IK
I
V = 0.6 V,
I
I
I
= –0.8 mA
2.4
3.4
0.2
V
OH
OL
OH
V = 2 V,
I
= 16 mA
0.4
V
OL
I
I
I
I
I
V = V
I
–0.43
–0.56
mA
mA
mA
µA
mA
mA
mA
mA
T+
T+
= 5 V,
V = V
I T–
T–
I
= MAX,
= MAX,
= MAX,
= MAX
= MAX
= MAX
V = 5.5 V
I
1
40
V
= 2.4 V
= 0.4 V
IH
IL
IH
IL
V
–0.8
–1.2
–55
36
¶
–18
I
I
I
OS
22
39
CCH
CCL
60
‡
§
¶
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
Not more than one output should be shorted at a time.
CC
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
switching characteristics, V
= 5 V, T = 25°C (see Figure 1)
A
CC
SN5414
SN7414
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
TEST CONDITIONS
UNIT
MIN
TYP
MAX
t
15
15
22
22
PLH
A
Y
R
= 400 Ω,
C
= 15 pF
L
ns
L
t
PHL
recommended operating conditions
SN54LS14
MIN NOM
SN74LS14
UNIT
MAX
5.5
MIN NOM
MAX
5.25
–0.4
8
V
Supply voltage
4.5
5
4.75
5
V
CC
OH
OL
I
I
High-level output current
Low-level output current
Operating free-air temperature
–0.4
4
mA
mA
°C
T
A
–55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LS14
SN74LS14
†
PARAMETER
UNIT
TEST CONDITIONS
‡
‡
MIN TYP
MAX
1.9
1
MIN TYP
MAX
1.9
1
V
T+
V
V
= 5 V
= 5 V
1.4
0.5
1.6
0.8
1.4
0.5
1.6
0.8
V
V
CC
V
T–
CC
Hysteresis
(V – V
V
CC
= 5 V
0.4
0.8
0.4
0.8
V
)
T–
T+
V
V
V
V
= MIN,
= MIN,
I = –18 mA
–1.5
–1.5
V
V
IK
CC
I
V = 0.5 V,
I
I
I
I
= –0.4 mA
2.5
3.4
2.7
3.4
0.25
OH
CC
OH
= 4 mA
0.25
0.4
0.4
0.5
OL
OL
V
OL
V
CC
= MIN,
V = –1.9 V
I
V
= 8 mA
0.35
I
I
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5 V,
V = V
–0.14
–0.18
–0.14
–0.18
mA
mA
mA
µA
T+
I
T+
= 5 V,
V = V
I T–
T–
I
= MAX,
= MAX,
= MAX,
= MAX
= MAX
= MAX
V = 7 V
I
0.1
20
0.1
20
V
= 2.7 V
= 0.4 V
IH
IL
IH
IL
V
–0.4
–100
16
–0.4
–100
16
mA
mA
mA
mA
§
–20
–20
OS
8.6
12
8.6
12
CCH
CCL
21
21
†
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
CC
A
switching characteristics, V
= 5 V, T = 25°C (see Figure 2)
CC
A
FROM
PARAMETER
TO
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(INPUT)
t
15
15
22
22
PLH
A
Y
R
= 2 kΩ,
C
= 15 pF
L
ns
L
t
PHL
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 DEVICES
V
CC
Test
Point
R
L
Test
Point
S1
V
CC
From Output
Under Test
V
CC
(see Note B)
R
L
C
L
(see Note A)
From Output
Under Test
1 kΩ
R
L
(see Note B)
From Output
Under Test
C
Test
Point
C
L
(see Note A)
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.5 V
1.5 V
1.5 V
1.5 V
Pulse
0 V
t
t
h
w
t
su
3 V
0 V
Low-Level
Pulse
Data
Input
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
3 V
0 V
Input
1.5 V
1.5 V
t
t
PLZ
PZL
t
t
PHL
PLH
Waveform 1
(see Notes C
and D)
≈1.5 V
In-Phase
1.5 V
V
OH
Output
(see Note D)
V
OL
+ 0.5 V
1.5 V
1.5 V
1.5 V
V
OL
V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
V
OH
Waveform 2
(see Notes C
and D)
V
OH
– 0.5 V
Out-of-Phase
Output
V
V
OH
1.5 V
1.5 V
≈1.5 V
(see Note D)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open and S2 is closed for t
PLZ PZH
; S1 is closed and S2 is open for t .
PZL
PLH PHL PHZ
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω; t and t ≤ 7 ns for Series
O
r
f
54/74 devices and t and t ≤ 2.5 ns for Series 54S/74S devices.
r
f
F. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
V
CC
Test
Point
R
L
Test
Point
S1
V
CC
From Output
Under Test
V
CC
(see Note B)
R
L
C
L
(see Note A)
From Output
Under Test
5 kΩ
R
L
(see Note B)
From Output
Under Test
C
Test
Point
C
L
(see Note A)
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0 V
t
t
h
w
t
su
3 V
0 V
Low-Level
Pulse
Data
Input
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
3 V
0 V
Control
(low-level
enabling)
1.3 V
1.3 V
3 V
0 V
Input
1.3 V
1.3 V
t
t
PLZ
PZL
t
t
PHL
PLH
Waveform 1
(see Notes C
and D)
≈1.5 V
In-Phase
Output
(see Note D)
1.3 V
V
V
OH
V
OL
+ 0.5 V
1.3 V
1.3 V
1.3 V
V
OL
t
PHZ
OL
t
PZH
t
t
PLH
PHL
V
OH
Waveform 2
(see Notes C
and D)
V
OH
– 0.5 V
Out-of-Phase
Output
(see Note D)
V
V
OH
1.3 V
1.3 V
≈1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open and S2 is closed for t
PLZ PZH
; S1 is closed and S2 is open for t .
PLH PHL PHZ
PZL
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t ≤ 1.5 ns, t ≤ 2.6 ns.
O
r
f
G. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
†
TYPICAL CHARACTERISTICS OF ’14 CIRCUITS
POSITIVE-GOING THRESHOLD VOLTAGE
NEGATIVE-GOING THRESHOLD VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1.70
0.90
V
CC
= 5 V
V
CC
= 5 V
0.89
0.88
0.87
0.86
0.85
0.84
0.83
0.82
0.81
0.80
1.69
1.68
1.67
1.66
1.65
1.64
1.63
1.62
1.61
1.60
–75 –50 –25
0
25
50
75 100 125
0
25
50
75 100 125
–75 –50 –25
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 3
Figure 4
HYSTERESIS
vs
FREE-AIR TEMPERATURE
850
V
CC
= 5 V
840
830
820
810
800
790
780
770
760
750
–75 –50 –25
0
25
50
75 100 125
T
A
– Free-Air Temperature – °C
Figure 5
†
Data for temperatures below 0°C and above 70°C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
†
TYPICAL CHARACTERISTICS OF ’14 CIRCUITS
THRESHOLD VOLTAGES
vs
DISTRIBUTION OF UNITS
FOR HYSTERESIS
SUPPLY VOLTAGE
2.0
V
T
= 5 V
CC
= 25°C
T
= 25°C
A
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
A
Positive-Going Threshold Voltage, V
T+
Negative-Going Threshold Voltage, V
T–
740
800 820 840 860 880 900
4.5
4.75
5
5.25
5.5
760 780
V – V – Hysteresis – mV
T+ T–
V
T+
– V – Hysteresis – mV
T–
Figure 6
Figure 7
OUTPUT VOLTAGE
vs
HYSTERESIS
vs
INPUT VOLTAGE
SUPPLY VOLTAGE
4
3
2
2.0
V
T
A
= 5 V
= 25°C
CC
T
A
= 25°C
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
T–
V
T+
1
0
4.5
4.75
V
5
5.25
5.5
0
0.4
V
0.8
1.2
1.6
2
– Supply Voltage – V
– Supply Voltage – V
CC
CC
Figure 8
Figure 9
†
Data for temperatures below 0°C and above 70°C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
†
TYPICAL CHARACTERISTICS OF ’LS14 CIRCUITS
POSITIVE-GOING THRESHOLD VOLTAGE
NEGATIVE-GOING THRESHOLD VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1.70
0.90
V
= 5 V
CC
V
= 5 V
CC
1.69
1.68
1.67
1.66
1.65
1.64
1.63
1.62
1.61
1.60
0.89
0.88
0.87
0.86
0.85
0.84
0.83
0.82
0.81
0.80
–75 –50 –25
0
25
50
75 100 125
–75 –50 –25
0
25
50
75 100 125
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 10
Figure 11
HYSTERESIS
vs
FREE-AIR TEMPERATURE
DISTRIBUTION OF UNITS
FOR HYSTERESIS
850
V
T
A
= 5 V
= 25°C
CC
V
CC
= 5 V
840
830
820
810
800
790
780
770
760
750
99% ARE
ABOVE
735 mV
720
740 760 780 800 820 840 860 880
–75 –50 –25
0
25
50
75 100 125
T
A
– Free-Air Temperature – °C
V – V – Hysteresis – mV
T+ T–
Figure 12
Figure 13
†
Data for temperatures below 0°C and above 70°C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
†
TYPICAL CHARACTERISTICS OF ’LS14 CIRCUITS
THRESHOLD VOLTAGES AND HYSTERESIS
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
vs
SUPPLY VOLTAGE
2.0
4
3
2
V
T
A
= 5 V
= 25°C
CC
T
= 25°C
A
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
T–
V +
T
Positive-Going Threshold Voltage, V
T+
Negative-Going Threshold Voltage, V
T–
Hysteresis, V – V
T+
T–
1
0
0.8
1.2
1.6
2
4.5
4.75
V
5
5.25
5.5
0
0.4
– Supply Voltage – V
V – Input Voltage – V
I
CC
Figure 14
Figure 15
†
Data for temperatures below 0°C and above 70°C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
TYPICAL APPLICATION DATA
TTL System
V
T+
Input
V
T–
CMOS
Sine-Wave
Oscillator
Output
TTL System Interface
for Slow Input Waveforms
Pulse Shaper
0.1 Hz to 10 MHz
V
T+
330 Ω
V
T–
Input
Input
Output
Multivibrator
Threshold Detector
Open-Collector
Output
Input
A
Input
Output
V
T+
Point A
Output
Pulse Stretcher
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-9665801Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
9665801Q2A
SNJ54LS
14FK
5962-9665801QCA
5962-9665801QDA
5962-9665801VCA
5962-9665801VDA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
CDIP
CFP
J
W
J
14
14
14
14
1
1
TBD
TBD
TBD
TBD
A42
A42
A42
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
5962-9665801QC
A
SNJ54LS14J
5962-9665801QD
A
SNJ54LS14W
25
1
5962-9665801VC
A
SNV54LS14J
W
5962-9665801VD
A
SNV54LS14W
JM38510/31302BCA
M38510/31302BCA
ACTIVE
ACTIVE
CDIP
CDIP
J
J
14
14
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
JM38510/
31302BCA
JM38510/
31302BCA
SN5414J
SN54LS14J
SN7414D
ACTIVE
ACTIVE
ACTIVE
CDIP
CDIP
SOIC
J
J
14
14
14
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
-55 to 125
-55 to 125
0 to 70
SN5414J
SN54LS14J
7414
D
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
SN7414DE4
SN7414DG4
SN7414DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
7414
7414
7414
7414
7414
50
Green (RoHS
& no Sb/Br)
2500
2500
2500
Green (RoHS
& no Sb/Br)
SN7414DRE4
SN7414DRG4
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN7414N
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN7414N
SN7414N3
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
14
14
TBD
Call TI
Call TI
0 to 70
0 to 70
SN7414NE4
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN7414N
SN7414
SN7414
SN7414
LS14
SN7414NSR
SN7414NSRE4
SN7414NSRG4
SN74LS14D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
NS
NS
NS
D
14
14
14
14
14
14
14
14
14
14
14
14
14
2000
2000
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
SO
Green (RoHS
& no Sb/Br)
SO
Green (RoHS
& no Sb/Br)
SOIC
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
Green (RoHS
& no Sb/Br)
SN74LS14DBR
SN74LS14DBRE4
SN74LS14DBRG4
SN74LS14DE4
SN74LS14DG4
SN74LS14DR
DB
DB
DB
D
2000
2000
2000
50
Green (RoHS
& no Sb/Br)
LS14
Green (RoHS
& no Sb/Br)
LS14
Green (RoHS
& no Sb/Br)
LS14
Green (RoHS
& no Sb/Br)
LS14
D
50
Green (RoHS
& no Sb/Br)
LS14
D
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
LS14
SN74LS14DRE4
SN74LS14DRG4
SN74LS14N
D
Green (RoHS
& no Sb/Br)
LS14
D
Green (RoHS
& no Sb/Br)
LS14
N
Pb-Free
(RoHS)
SN74LS14N
SN74LS14N3
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
14
14
TBD
Call TI
Call TI
0 to 70
0 to 70
SN74LS14NE4
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74LS14N
74LS14
SN74LS14NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN74LS14NSRE4
SN74LS14NSRG4
ACTIVE
SO
SO
NS
14
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
74LS14
ACTIVE
NS
2000
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
0 to 70
74LS14
SNJ5414J
SNJ5414W
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
J
14
14
20
1
1
1
TBD
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
SNJ5414J
SNJ5414W
W
FK
SNJ54LS14FK
LCCC
POST-PLATE
5962-
9665801Q2A
SNJ54LS
14FK
SNJ54LS14J
SNJ54LS14W
ACTIVE
ACTIVE
CDIP
CFP
J
14
14
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9665801QC
A
SNJ54LS14J
W
5962-9665801QD
A
SNJ54LS14W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN5414, SN54LS14, SN54LS14-SP, SN7414, SN74LS14 :
Catalog: SN7414, SN74LS14, SN54LS14
•
Military: SN5414, SN54LS14
•
Space: SN54LS14-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN7414DR
SN7414NSR
SOIC
SO
D
14
14
14
14
14
2500
2000
2000
2500
2000
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
6.5
8.2
8.2
6.5
8.2
9.0
10.5
6.6
2.1
2.5
2.5
2.1
2.5
8.0
12.0
12.0
8.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
NS
DB
D
SN74LS14DBR
SN74LS14DR
SN74LS14NSR
SSOP
SOIC
SO
9.0
NS
10.5
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN7414DR
SN7414NSR
SOIC
SO
D
14
14
14
14
14
2500
2000
2000
2500
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
38.0
38.0
38.0
NS
DB
D
SN74LS14DBR
SN74LS14DR
SN74LS14NSR
SSOP
SOIC
SO
NS
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74150N-00
IC TTL/H/L SERIES, 16 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDIP24, Multiplexer/Demultiplexer
TI
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