SN74ABT16244ADLG4 [TI]

16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS; 16位缓冲器/驱动器,具有三态输出
SN74ABT16244ADLG4
型号: SN74ABT16244ADLG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
16位缓冲器/驱动器,具有三态输出

驱动器 输出元件
文件: 总12页 (文件大小:184K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SN54ABT16244, SN74ABT16244A  
16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS073HSEPTEMBER 1991REVISED AUGUST 2005  
FEATURES  
SN54ABT16244. . . WD PACKAGE  
SN74ABT16244A. . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus™ Family  
State-of-the-Art EPIC-IIB™ BiCMOS Design  
Significantly Reduces Power Dissipation  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Y1  
1Y2  
GND  
1Y3  
1Y4  
2OE  
1A1  
1A2  
GND  
1A3  
1A4  
2
Latch-Up Performance Exceeds 500 mA Per  
JESD 70  
3
4
Typical VOLP (Output Ground Bounce) <1 V  
at VCC = 5 V, TA = 25°C  
5
6
Distributed VCC and GND Pin Configuration  
Minimizes High-Speed Switching Noise  
7
V
CC  
V
CC  
8
2Y1  
2Y2  
GND  
2Y3  
2Y4  
3Y1  
3Y2  
GND  
3Y3  
3Y4  
2A1  
2A2  
GND  
2A3  
2A4  
3A1  
3A2  
GND  
3A3  
3A4  
Flow-Through Architecture Optimizes PCB  
Layout  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
High-Drive Outputs (–32-mA IOH, 64-mA IOL)  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
V
CC  
V
CC  
4Y1  
4Y2  
GND  
4Y3  
4Y4  
4OE  
4A1  
4A2  
GND  
4A3  
4A4  
3OE  
DESCRIPTION  
The SN54ABT16244 and SN74ABT16244A are 16-bit  
buffers and line drivers designed specifically to  
improve both the performance and density of 3-state  
memory address drivers, clock drivers, and  
bus-oriented receivers and transmitters. These  
devices can be used as four 4-bit buffers, two 8-bit  
buffers, or one 16-bit buffer. These devices provide  
true outputs and symmetrical OE (active-low  
output-enable) inputs.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54ABT16244 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ABT16244A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(EACH BUFFER)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC-IIB are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1991–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
SN54ABT16244, SN74ABT16244A  
16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS073HSEPTEMBER 1991REVISED AUGUST 2005  
LOGIC SYMBOL(1)  
1
1OE  
EN1  
EN2  
EN3  
EN4  
48  
2OE  
25  
3OE  
24  
4OE  
47  
1A1  
46  
2
3
1
1
1
1
1
2
3
4
1Y1  
1Y2  
1Y3  
1Y4  
2Y1  
2Y2  
2Y3  
2Y4  
3Y1  
3Y2  
3Y3  
3Y4  
4Y1  
4Y2  
4Y3  
4Y4  
1A2  
44  
5
1A3  
43  
6
1A4  
41  
8
2A1  
40  
9
2A2  
38  
11  
12  
13  
14  
16  
17  
19  
20  
22  
23  
2A3  
37  
2A4  
36  
3A1  
35  
3A2  
33  
3A3  
32  
3A4  
30  
4A1  
29  
4A2  
27  
4A3  
26  
4A4  
(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
2
SN54ABT16244, SN74ABT16244A  
16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS073HSEPTEMBER 1991REVISED AUGUST 2005  
LOGIC DIAGRAM (POSITIVE LOGIC)  
1
25  
36  
35  
1OE  
1A1  
3OE  
3A1  
47  
46  
2
3
5
6
13  
14  
16  
17  
1Y1  
1Y2  
1Y3  
1Y4  
3Y1  
3Y2  
3Y3  
3Y4  
1A2  
1A3  
1A4  
3A2  
3A3  
3A4  
44  
43  
33  
32  
48  
41  
24  
30  
2OE  
2A1  
4OE  
4A1  
8
9
19  
20  
22  
23  
2Y1  
2Y2  
2Y3  
2Y4  
4Y1  
4Y2  
4Y3  
4Y4  
40  
38  
37  
29  
27  
26  
2A2  
2A3  
2A4  
4A2  
4A3  
4A4  
11  
12  
Absolute Maximum Ratings(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–0.5  
–0.5  
–0.5  
MAX UNIT  
VCC  
VI  
Supply voltage range  
Input voltage range(2)  
7
7
V
V
V
VO  
Voltage range applied to any output in the high or power-off state  
5.5  
96  
SN54ABT16244  
SN74ABT16244A  
VI < 0  
IO  
Current into any output in the low state  
mA  
128  
IIK  
Input clamp current  
Output clamp current  
–18 mA  
–50 mA  
89  
IOK  
VO < 0  
DGG package  
DGV package  
DL package  
θJA  
Package thermal impedance(3)  
93 °C/W  
94  
Tstg  
Storage temperature range  
–65  
150  
°C  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability  
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
(3) The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD 51.  
3
SN54ABT16244, SN74ABT16244A  
16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS073HSEPTEMBER 1991REVISED AUGUST 2005  
Recommended Operating Conditions(1)  
SN54ABT16244 SN74ABT16244A  
UNIT  
MIN  
4.5  
2
MAX  
MIN  
4.5  
2
MAX  
VCC  
VIH  
VIL  
Supply voltage  
5.5  
5.5  
V
V
High-level input voltage  
Low-level input voltage  
Input voltage  
0.8  
VCC  
–24  
48  
0.8  
VCC  
–32  
64  
V
VI  
0
0
V
IOH  
IOL  
High-level output current  
Low-level output current  
Input transition rise or fall rate  
Operating free-air temperature  
mA  
mA  
t/v  
TA  
Outputs enabled  
10  
10 ns/V  
–55  
125  
–40  
85  
°C  
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
Electrical Characteristics  
over recommended operating free-air temperature range (unless otherwise noted)  
TA = 25°C(1)  
MIN TYP(2)  
SN54ABT16244  
SN74ABT16244A  
PARAMETER  
VIK  
TEST CONDITIONS  
UNIT  
MAX  
MIN  
MAX  
MIN  
MAX  
VCC = 4.5 V,  
II = –18 mA  
IOH = –3 mA  
IOH = –3 mA  
IOH = –24 mA  
IOH = –32 mA  
IOL = 48 mA  
IOL = 64 mA  
–1.2  
–1.2  
–1.2  
V
VCC = 4.5 V,  
VCC = 5 V,  
2.5  
3
2.5  
3
2.5  
3
VOH  
V
2
2(3)  
2
VCC = 4.5 V  
VCC = 4.5 V  
2
0.55  
0.55  
VOL  
V
0.55(3)  
0.55  
Vhys  
II  
100  
mV  
µA  
µA  
µA  
µA  
VCC = 5.5 V, VI = VCC or GND  
±1  
10(4)  
–10(4)  
±1  
10  
±1  
10(4)  
–10(4)  
IOZH  
IOZL  
Ioff  
VCC = 5.5 V,  
VCC = 5.5 V,  
VCC = 0,  
VO = 2.7 V  
VO = 0.5 V  
–10  
VI or VO 5.5 V  
±100  
±100  
VCC = 5.5 V,  
VO = 5.5 V  
ICEX  
Outputs high  
50  
50  
50  
µA  
(5)  
IO  
VCC = 5.5 V,  
VO = 2.5 V  
–50  
–100  
–180  
3
–50  
–180  
2
–50  
–180  
3
mA  
Outputs high  
Outputs low  
VCC = 5.5 V,  
IO = 0,  
VI = VCC or GND  
ICC  
32  
32  
2
32  
mA  
mA  
Outputs disabled  
Outputs enabled  
3
3
VCC = 5.5 V,  
0.05  
1.5  
0.05  
Data  
inputs  
One input at 3.4 V,  
Other inputs at  
VCC or GND  
Outputs disabled  
0.05  
0.05  
1
0.05  
0.05  
(6)  
ICC  
Control  
inputs  
VCC = 5.5 V, One input at 3.4 V,  
Other inputs at VCC or GND  
1.5  
Ci  
VI = 2.5 V or 0.5 V  
VO = 2.5 V or 0.5 V  
3
6
pF  
pF  
Co  
(1) Characteristics for TA = 25°C apply to the SN74ABT16244A only.  
(2) All typical values are at VCC = 5 V.  
(3) On products compliant to MIL-PRF-38535, this parameter does not apply.  
(4) This data-sheet limit may vary among suppliers.  
(5) Not more than one output should be tested at a time, and the duration of the test should not exceed one second.  
(6) This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.  
4
SN54ABT16244, SN74ABT16244A  
16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS073HSEPTEMBER 1991REVISED AUGUST 2005  
Switching Characteristics  
over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF  
(unless otherwise noted) (see Figure 1 )  
SN54ABT16244  
VCC = 5 V,  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
TA = 25°C  
TYP  
2.3  
MIN  
MAX  
MIN  
0.7  
0.5  
0.7  
0.9  
1.7  
1.5  
MAX  
3.2  
3.7  
4
tPLH  
tPHL  
tPZH  
tPZL  
tPHZ  
tPLZ  
0.7  
0.5  
0.7  
0.9  
1.7  
1.5  
3.6  
4.2  
4.9  
6.5  
6
A
Y
Y
Y
ns  
ns  
ns  
2.6  
3
OE  
OE  
3.2  
5.5  
5
3.6  
2.9  
4.7  
5.7  
Switching Characteristics  
over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF  
(unless otherwise noted) (see Figure 1 )  
SN74ABT16244A  
VCC = 5 V,  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
TA = 25°C  
TYP  
2.3  
MIN  
MAX  
MIN  
1
MAX  
3.2  
3.7  
3.8  
4
tPLH  
tPHL  
tPZH  
tPZL  
tPHZ  
tPLZ  
1
1
1
1
1
1
3.5  
4.1  
4.8  
4.8  
4.8  
4.1  
A or B  
OE  
Y
Y
Y
ns  
ns  
ns  
1
2.6  
1
3
1
3.2  
1
3.6  
4.4  
3.7  
OE  
1
2.9  
5
SN54ABT16244, SN74ABT16244A  
16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS073HSEPTEMBER 1991REVISED AUGUST 2005  
PARAMETER MEASUREMENT INFORMATION  
7 V  
Open  
TEST  
/t  
S1  
S1  
500 Ω  
From Output  
Under Test  
t
Open  
7 V  
PLH PHL  
GND  
t
/t  
PLZ PZL  
C = 50 pF  
(see Note A)  
t
/t  
Open  
L
PHZ PZH  
500 Ω  
3 V  
0 V  
LOAD CIRCUIT  
Timing Input  
Data Input  
1.5 V  
t
w
t
t
h
su  
3 V  
0 V  
3 V  
Input  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
3 V  
0 V  
3 V  
0 V  
Output  
Control  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
Input  
t
PZL  
t
t
t
PHL  
PLH  
t
PLZ  
Output  
Waveform 1  
S1 at 7 V  
3.5 V  
V
V
OH  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
Output  
V
V
+ 0.3 V  
− 0.3 V  
OL  
V
OL  
OL  
(see Note B)  
t
PHZ  
t
PHL  
PLH  
t
PZH  
Output  
Waveform 2  
S1 at Open  
(see Note B)  
V
OH  
V
V
OH  
OH  
1.5 V  
1.5 V  
Output  
0 V  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2.5 ns, t 2.5 ns.  
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
6
PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Sep-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
5962-9317401MXA  
ACTIVE  
ACTIVE  
CFP  
WD  
48  
48  
1
TBD  
Call TI  
Level-NC-NC-NC  
74ABT16244ADGGRG4  
TSSOP  
DGG  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
74ABT16244ADGVRE4  
SN74ABT16244ADGGR  
SN74ABT16244ADGVR  
SN74ABT16244ADL  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
TVSOP  
TSSOP  
TVSOP  
SSOP  
SSOP  
SSOP  
SSOP  
CFP  
DGV  
DGG  
DGV  
DL  
48  
48  
48  
48  
48  
48  
48  
48  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74ABT16244ADLG4  
SN74ABT16244ADLR  
SN74ABT16244ADLRG4  
SNJ54ABT16244WD  
DL  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
DL  
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
DL  
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
WD  
1
TBD  
Call TI  
Level-NC-NC-NC  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
MECHANICAL DATA  
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997  
WD (R-GDFP-F**)  
CERAMIC DUAL FLATPACK  
48 LEADS SHOWN  
0.120 (3,05)  
0.075 (1,91)  
0.009 (0,23)  
0.004 (0,10)  
1.130 (28,70)  
0.870 (22,10)  
0.370 (9,40)  
0.250 (6,35)  
0.390 (9,91)  
0.370 (9,40)  
0.370 (9,40)  
0.250 (6,35)  
1
48  
0.025 (0,635)  
A
0.014 (0,36)  
0.008 (0,20)  
24  
25  
NO. OF  
LEADS**  
48  
56  
0.740  
0.640  
(16,26) (18,80)  
A MAX  
A MIN  
0.610 0.710  
(15,49) (18,03)  
4040176/D 10/97  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a ceramic lid using glass frit.  
D. Index point is provided on cap for terminal identification only  
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA  
GDFP1-F56 and JEDEC MO-146AB  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000  
DGV (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
24 PINS SHOWN  
0,23  
0,13  
M
0,07  
0,40  
24  
13  
0,16 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
0°ā8°  
0,75  
1
12  
0,50  
A
Seating Plane  
0,08  
0,15  
0,05  
1,20 MAX  
PINS **  
14  
16  
20  
24  
38  
48  
56  
DIM  
A MAX  
A MIN  
3,70  
3,50  
3,70  
3,50  
5,10  
4,90  
5,10  
4,90  
7,90  
7,70  
9,80  
9,60  
11,40  
11,20  
4073251/E 08/00  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.  
D. Falls within JEDEC: 24/48 Pins – MO-153  
14/16/20/56 Pins – MO-194  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001  
DL (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
48 PINS SHOWN  
0.025 (0,635)  
48  
0.0135 (0,343)  
0.008 (0,203)  
0.005 (0,13)  
M
25  
0.010 (0,25)  
0.005 (0,13)  
0.299 (7,59)  
0.291 (7,39)  
0.420 (10,67)  
0.395 (10,03)  
Gage Plane  
0.010 (0,25)  
0°ā8°  
1
24  
0.040 (1,02)  
0.020 (0,51)  
A
Seating Plane  
0.004 (0,10)  
0.008 (0,20) MIN  
PINS **  
0.110 (2,79) MAX  
28  
48  
0.630  
56  
DIM  
0.380  
(9,65)  
0.730  
A MAX  
A MIN  
(16,00) (18,54)  
0.370  
(9,40)  
0.620  
0.720  
(15,75) (18,29)  
4040048/E 12/01  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).  
D. Falls within JEDEC MO-118  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998  
DGG (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
48 PINS SHOWN  
0,27  
0,17  
M
0,08  
0,50  
48  
25  
6,20  
6,00  
8,30  
7,90  
0,15 NOM  
Gage Plane  
0,25  
1
24  
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
48  
56  
64  
DIM  
A MAX  
12,60  
12,40  
14,10  
13,90  
17,10  
16,90  
A MIN  
4040078/F 12/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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