SN74ABT162823ADLR [TI]
18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS; 18位总线接口触发器具有三态输出
| 型号： | SN74ABT162823ADLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| 文件： | 总10页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊ ꢉ ꢋ ꢄꢌ ꢀꢁ ꢍꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢉꢋ ꢄ
ꢇ ꢊ ꢎꢅꢏ ꢆ ꢅꢐꢀ ꢎꢏꢁꢆ ꢑꢒꢓꢄꢔꢑ ꢓ ꢕꢏ ꢖ ꢎꢓ ꢕꢗ ꢖꢀ
ꢘ ꢏꢆ ꢙ ꢋ ꢎꢀꢆꢄꢆ ꢑ ꢗ ꢐꢆ ꢖꢐ ꢆꢀ
SCBS666B − JULY 1996 − REVISED JUNE 2004
SN54ABT162823A . . . WD PACKAGE
SN74ABT162823A . . . DGG OR DL PACKAGE
(TOP VIEW)
D
D
Members of the Texas Instruments
Widebus Family
Output Ports Have Equivalent 25-Ω Series
Resistors So No External Resistors Are
Required
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CLR
1OE
1Q1
GND
1Q2
1Q3
1CLK
1CLKEN
1D1
GND
1D2
2
D
D
D
D
D
Typical V
(Output Ground Bounce)
OLP
3
<1 V at V
= 5 V, T = 25°C
4
CC
A
5
High-Impedance State During Power Up
and Power Down
6
1D3
7
V
V
I
and Power-Up 3-State Support Hot
CC
CC
off
8
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
Insertion
9
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Flow-Through Architecture Optimizes PCB
Layout
description/ordering information
These 18-bit bus-interface flip-flops feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing wider buffer registers, I/O ports,
bidirectional bus drivers with parity, and working
registers.
V
V
CC
CC
2Q7
2Q8
GND
2Q9
2OE
2CLR
2D7
2D8
GND
2D9
2CLKEN
2CLK
The ’ABT162823A devices can be used as two
9-bit flip-flops or one 18-bit flip-flop. With the
clock-enable (CLKEN) input low, the D-type
flip-flops enter data on the low-to-high transitions
of the clock. Taking CLKEN high disables the
clock buffer, thus latching the outputs. Taking the
clear (CLR) input low causes the Q outputs to go
low independently of the clock.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74ABT162823ADL
SSOP − DL
ABT162823A
Tape and reel
SN74ABT162823ADLR
SN74ABT162823ADGGR
SNJ54ABT162823AWD
−40°C to 85°C
−55°C to 125°C
TSSOP − DGG Tape and reel
CFP − WD Tube
ABT162823A
SNJ54ABT162823AWD
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2004, Texas Instruments Incorporated
ꢐ ꢁ ꢕꢑꢀꢀ ꢗ ꢆꢙ ꢑꢒꢘ ꢏꢀ ꢑ ꢁ ꢗꢆꢑꢚ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢖꢒ ꢗ ꢚ ꢐ ꢔꢆ ꢏꢗ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢊ ꢉꢋ ꢄꢌ ꢀ ꢁꢍ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢉꢋ ꢄ
ꢇꢊ ꢎꢅꢏ ꢆ ꢅ ꢐꢀ ꢎꢏ ꢁꢆ ꢑꢒꢓꢄꢔ ꢑ ꢓꢕ ꢏ ꢖ ꢎꢓꢕꢗ ꢖ ꢀ
ꢘꢏ ꢆ ꢙ ꢋ ꢎꢀꢆꢄꢆ ꢑ ꢗꢐꢆ ꢖꢐ ꢆꢀ
SCBS666B − JULY 1996 − REVISED JUNE 2004
description/ordering information (continued)
A buffered output-enable (OE) input places the nine outputs in either a normal logic state (high or low level) or
a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be
retained or new data can be entered while the outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to
reduce overshoot and undershoot.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE shall be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
FUNCTION TABLE
(each 9-bit flip-flop)
INPUTS
OUTPUT
Q
CLR CLKEN
OE
L
CLK
X
D
X
H
L
L
H
H
H
H
X
X
L
L
H
L
L
↑
L
L
↑
L
L
L
X
X
X
Q
0
0
L
H
X
X
Q
H
X
Z
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊ ꢉ ꢋ ꢄꢌ ꢀꢁꢍ ꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊꢉ ꢋꢄ
ꢇ ꢊ ꢎꢅꢏ ꢆ ꢅꢐꢀ ꢎꢏꢁꢆ ꢑꢒꢓꢄꢔꢑ ꢓ ꢕꢏ ꢖ ꢎꢓ ꢕꢗ ꢖꢀ
ꢘ ꢏꢆ ꢙ ꢋ ꢎꢀꢆꢄꢆ ꢑ ꢗ ꢐꢆ ꢖꢐ ꢆꢀ
SCBS666B − JULY 1996 − REVISED JUNE 2004
logic diagram (positive logic)
2
1OE
1
1CLR
55
1CLKEN
CE
R
56
3
1Q1
C1
1D
1CLK
54
1D1
To Eight Other Channels
27
2OE
28
2CLR
30
2CLKEN
CE
R
29
15
2Q1
C1
1D
2CLK
42
2D1
To Eight Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
O
Current into any output in the low state, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢊ ꢉꢋ ꢄꢌ ꢀ ꢁꢍ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢉꢋ ꢄ
ꢇꢊ ꢎꢅꢏ ꢆ ꢅ ꢐꢀ ꢎꢏ ꢁꢆ ꢑꢒꢓꢄꢔ ꢑ ꢓꢕ ꢏ ꢖ ꢎꢓꢕꢗ ꢖ ꢀ
ꢘꢏ ꢆ ꢙ ꢋ ꢎꢀꢆꢄꢆ ꢑ ꢗꢐꢆ ꢖꢐ ꢆꢀ
SCBS666B − JULY 1996 − REVISED JUNE 2004
recommended operating conditions (see Note 3)
SN54ABT162823A SN74ABT162823A
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
0
V
CC
V
I
CC
−3
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Input transition rise or fall rate
Operating free-air temperature
−12
12
mA
mA
ns/V
µs/V
°C
OH
OL
8
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
−55
200
−40
CC
T
A
125
85
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT162823A SN74ABT162823A
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
= 4.5 V,
I = −18 mA
−1.2
−1.2
−1.2
V
IK
CC
CC
CC
I
= 4.5 V,
= 5 V,
I
I
I
I
I
I
= −1 mA
= −1 mA
= −3 mA
= −12 mA
= 8 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
V
2.4
2*
2.4
2.4
2
V
= 4.5 V
= 4.5 V
CC
CC
0.4
0.8
0.65
0.8
1
V
OL
V
V
V
= 12 mA
0.8*
1
I
I
= 5.5 V,
V = V
I CC
or GND
1
µA
µA
I
CC
CC
V
V
= 0 to 2.1 V,
= 0.5 V to 2.7 V, OE = X
50
50
50
50
50
OZPU
OZPD
O
V
V
= 2.1 V to 0,
= 0.5 V to 2.7 V, OE = X
CC
O
I
50
µA
‡
I
I
I
V
V
V
= 5.5 V,
= 5.5 V,
= 0,
V
V
= 2.7 V
= 0.5 V
10
−10
100
10
10
−10
100
µA
µA
µA
OZH
CC
CC
CC
CC
O
‡
−10
OZL
O
V or V ≤ 4.5 V
I
off
O
V
V
= 5.5 V,
= 5.5 V
I
Outputs high
= 2.5 V
50
50
50
µA
CEX
O
§
I
O
V
CC
= 5.5 V,
V
O
−25
−55 −100
−25
−100
0.5
−25
−100
0.5
mA
Outputs high
Outputs low
0.5
80
V
I
= 5.5 V,
= 0,
CC
O
80
80
mA
I
CC
V = V
I
or GND
CC
Outputs disabled
0.5
0.5
0.5
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
¶
1.5
1.5
1.5
mA
∆I
CC
or GND
CC
V = 2.5 V or 0.5 V
C
C
3.5
9
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
include the input leakage current.
CC
OZL
The parameters I
and I
OZH
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL-voltage level, rather than V or GND.
CC
ꢖ
ꢒ
ꢗ
ꢚ
ꢐ
ꢔ
ꢆ
ꢖ
ꢒ
ꢑ
ꢱ
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ꢝ
ꢥ
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ꢠ
ꢥ
ꢡ
ꢤ
ꢨ
ꢥ
ꢞ
ꢩ
ꢨ
ꢠ
ꢟ
ꢢ
ꢡ
ꢟ ꢤ ꢞ ꢝ ꢰ ꢥ ꢩꢜ ꢦ ꢞ ꢤ ꢠꢧ ꢟꢤ ꢲ ꢤ ꢫ ꢠꢩ ꢣꢤ ꢥ ꢛꢬ ꢔ ꢜꢦ ꢨꢦ ꢡꢛ ꢤꢨ ꢝꢞ ꢛꢝ ꢡ ꢟꢦ ꢛꢦ ꢦꢥ ꢟ ꢠꢛ ꢜꢤꢨ
ꢛ
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ꢤ
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ꢝ
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ꢡ ꢜ ꢦ ꢥ ꢰꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢ ꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠ ꢟꢢꢡ ꢛꢞ ꢮ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢬ
ꢛ
ꢞ
ꢨ
ꢤ
ꢞ
ꢤ
ꢨ
ꢲ
ꢤꢞ
ꢛ
ꢜ
ꢤ
ꢨ
ꢝ
ꢰ
ꢜ
ꢛ
ꢛ
ꢠ
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊ ꢉ ꢋ ꢄꢌ ꢀꢁꢍ ꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊꢉ ꢋꢄ
ꢇ ꢊ ꢎꢅꢏ ꢆ ꢅꢐꢀ ꢎꢏꢁꢆ ꢑꢒꢓꢄꢔꢑ ꢓ ꢕꢏ ꢖ ꢎꢓ ꢕꢗ ꢖꢀ
ꢘ ꢏꢆ ꢙ ꢋ ꢎꢀꢆꢄꢆ ꢑ ꢗ ꢐꢆ ꢖꢐ ꢆꢀ
SCBS666B − JULY 1996 − REVISED JUNE 2004
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V
T
= 5 V,
= 25°C
CC
A
SN54ABT162823A SN74ABT162823A
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
150
150
150
MHz
ns
clock
CLR low
3.3
3.3
1.6
2
3.3
3.3
2
3.3
3.3
1.6
2
w
CLK high or low
CLR inactive
Data
2
t
ns
ns
Setup time before CLK↑
Hold time after CLK↑
su
h
CLKEN low
Data
2.8
1.2
0.6
2.8
1.2
0.6
2.8
1.2
0.6
t
CLKEN low
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT162823A SN74ABT162823A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
150
2.3
2.8
2.8
1.7
3
TYP
MAX
MIN
150
2.3
2.8
2.8
1.7
3
MAX
MIN
150
2.3
2.8
2.8
1.7
3
MAX
f
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
4.6
4.6
5
6.2
6.1
6.3
5
8.4
7.1
7.5
6.7
7
CLK
CLR
Q
Q
7.2
ns
3.8
5
5.8
5.9
7
Q
Q
ns
ns
OE
OE
6.1
6.1
6.7
7.2
2.6
1.9
4.8
4.6
2.6
1.9
7.3
2.6
1.9
6.6
9
10.2
ꢐ ꢁ ꢕꢑꢀꢀ ꢗ ꢆꢙ ꢑꢒꢘ ꢏꢀ ꢑ ꢁ ꢗꢆꢑꢚ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢖꢒ ꢗ ꢚ ꢐ ꢔꢆ ꢏꢗ ꢁ
ꢛ
ꢚ
ꢄ
ꢆ
ꢄ
ꢝ
ꢥ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢡ
ꢢ
ꢨ
ꢨ
ꢤ
ꢥ
ꢛ
ꢦ
ꢞ
ꢠ
ꢧ
ꢩ
ꢢ
ꢪ
ꢫ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢟ
ꢦ
ꢤ
ꢬ
ꢖ
ꢨ
ꢠ
ꢟ
ꢢ
ꢡ
ꢛ
ꢞ
ꢡ
ꢠ
ꢥ
ꢧ
ꢠ
ꢨ
ꢣ
ꢛ
ꢠ
ꢞ
ꢩ
ꢤ
ꢡ
ꢝ
ꢧ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢞ
ꢩ
ꢤ
ꢨ
ꢛ
ꢜ
ꢤ
ꢛ
ꢤ
ꢨ
ꢣ
ꢞ
ꢠ
ꢧ
ꢆ
ꢤ
ꢭ
ꢦ
ꢞ
ꢏ
ꢥ
ꢞ
ꢛ
ꢨ
ꢢ
ꢣ
ꢤꢥ
ꢛ
ꢞ
ꢞꢛ
ꢦ
ꢥ
ꢟ
ꢦ
ꢨ
ꢟ
ꢮ
ꢦ
ꢨ
ꢨ
ꢦ
ꢥ
ꢛ
ꢯ
ꢬ
ꢖ
ꢨ
ꢠ
ꢟ
ꢢ
ꢡ
ꢛ
ꢝ
ꢠ
ꢥ
ꢩꢦ ꢨ ꢦ ꢣ ꢤ ꢛ ꢤ ꢨ ꢞ ꢬ
ꢩ
ꢨ
ꢠ
ꢡ
ꢤ
ꢞ
ꢞ
ꢝ
ꢥ
ꢰ
ꢟ
ꢠ
ꢤꢞ
ꢥ
ꢠ
ꢛ
ꢥ
ꢤ
ꢡꢤ
ꢞ
ꢞ
ꢦꢨ
ꢝ
ꢫ
ꢯ
ꢝ
ꢥ
ꢡ
ꢫ
ꢢ
ꢟ
ꢤ
ꢛ
ꢤ
ꢞꢛ
ꢝ
ꢥ
ꢰ
ꢠ
ꢧ
ꢦ
ꢫ
ꢫ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢊ ꢉꢋ ꢄꢌ ꢀ ꢁꢍ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢉꢋ ꢄ
ꢇꢊ ꢎꢅꢏ ꢆ ꢅ ꢐꢀ ꢎꢏ ꢁꢆ ꢑꢒꢓꢄꢔ ꢑ ꢓꢕ ꢏ ꢖ ꢎꢓꢕꢗ ꢖ ꢀ
ꢘꢏ ꢆ ꢙ ꢋ ꢎꢀꢆꢄꢆ ꢑ ꢗꢐꢆ ꢖꢐ ꢆꢀ
SCBS666B − JULY 1996 − REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION
7 V
TEST
S1
Open
S1
500 Ω
From Output
Under Test
t
/t
PLH PHL
Open
7 V
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
74ABT162823ADGGRE4
74ABT162823ADLRG4
SN74ABT162823ADGGR
SN74ABT162823ADL
SN74ABT162823ADLG4
SN74ABT162823ADLR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
56
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
TSSOP
SSOP
SSOP
SSOP
DL
DGG
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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