SN74ABT16600DGGR [TI]
ABT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, TSSOP-56;
| 型号： | SN74ABT16600DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ABT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, TSSOP-56 信息通信管理 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT16600, SN74ABT16600
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS209B – JUNE 1992 – REVISED JANUARY 1997
SN54ABT16600 . . . WD PACKAGE
SN74ABT16600 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
OEAB
LEAB
A1
GND
A2
1
56 CLKENAB
55 CLKAB
54 B1
UBT (Universal Bus Transceiver)
2
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
3
4
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
B2
B3
5
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
6
A3
7
V
V
CC
A4
CC
8
B4
B5
B6
GND
B7
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
9
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 5 V, T = 25°C
CC
A
Flow-Through Architecture Optimizes PCB
Layout
B8
B9
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
B10
B11
B12
GND
B13
B14
B15
description
V
V
CC
CC
These 18-bit universal bus transceivers combine
D-type latches and D-type flip-flops to allow data
flow in transparent, latched, clocked, and
clock-enabled modes.
A16
A17
GND
A18
OEBA
LEBA
B16
B17
GND
B18
CLKBA
CLKENBA
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. The clock can be controlled by the
clock-enable (CLKENAB and CLKENBA) inputs.
For A-to-B data flow, the device operates in the
transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held
at a high or low logic level. If LEAB is low, the
A-bus data is stored in the latch/flip-flop on the
high-to-low transition of CLKAB. Output enable
OEAB is active low. When OEAB is low, the
outputs are active. When OEAB is high, the
outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16600, SN74ABT16600
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS209B – JUNE 1992 – REVISED JANUARY 1997
description (continued)
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16600 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16600 is characterized for operation from –40°C to 85°C.
†
FUNCTION TABLE
INPUTS
OUTPUT
B
LEAB
A
X
L
CLKENAB OEAB
CLKAB
X
X
X
H
H
L
H
L
L
L
L
L
L
L
L
X
H
H
L
L
L
L
L
L
X
X
X
X
X
↓
Z
L
H
X
X
L
H
‡
B
0
‡
B
0
L
L
↓
H
X
X
H
‡
§
L
H
L
B
0
0
L
B
†
‡
§
A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, CLKBA, and CLKENBA.
Output level before the indicated steady-state input conditions were
established
Output level before the indicated steady-state input conditions were
established, provided that CLKAB was low before LEAB went low
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16600, SN74ABT16600
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS209B – JUNE 1992 – REVISED JANUARY 1997
logic diagram (positive logic)
1
OEAB
56
CLKENAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
29
CLKENBA
27
OEBA
CE
3
A1
54
1D
C1
B1
CLK
CE
1D
C1
CLK
To 17 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT16600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT16600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16600, SN74ABT16600
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS209B – JUNE 1992 – REVISED JANUARY 1997
recommended operating conditions (see Note 3)
SN54ABT16600 SN74ABT16600
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
0
V
CC
V
I
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
48
–32
64
mA
mA
ns/V
°C
OH
OL
∆t/∆v
Outputs enabled
10
10
T
–55
125
–40
85
A
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT16600 SN74ABT16600
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
V
V
V
V
OL
0.55*
0.55
100
mV
µA
hys
Control inputs
A or B ports
±1
±20
±1
±1
±20
I
I
V
V
= 5.5 V,
V = V
I
or GND
CC
CC
±20
I
off
= 0,
V or V ≤ 4.5 V
±100
±100
µA
µA
CC
CC
I
O
V
V
= 5.5 V,
= 5.5 V
I
Outputs high
50
50
50
CEX
O
‡
I
I
I
V
V
V
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
V
V
= 2.5 V
= 2.7 V
= 0.5 V
–50
–100
–180
10
–10
3
–50
–180
10
–10
3
–50
–180
10
–10
3
mA
µA
µA
O
CC
CC
CC
O
O
O
§
OZH
§
OZL
Outputs high
Outputs low
V
I
= 5.5 V,
= 0,
CC
O
I
A or B ports
36
3
36
3
36
3
mA
CC
V = V
or GND
CC
I
Outputs disabled
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
¶
50
50
50
µA
∆I
CC
or GND
CC
Control inputs V = 2.5 V or 0.5 V
C
C
3
9
pF
pF
i
I
A or B ports
V
O
= 2.5 V or 0.5 V
io
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
The parameters I and I include the input leakage current.
OZH
OZL
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16600, SN74ABT16600
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS209B – JUNE 1992 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT16600 SN74ABT16600
UNIT
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
0
150
0
150
MHz
ns
clock
LEAB or LEBA high
2.5
3
2.5
3
w
CLKAB or CLKBA high or low
A before CLKAB↓ or B before CLKBA↓
A before LEAB↓ or B before LEBA↓
CLKEN before CLK↓
3
3
t
Setup time
Hold time
2.5
2.5
0
2.5
2.5
0
ns
ns
su
h
A after CLKAB↓ or B after CLKBA↓
A after LEAB↓ or B after LEBA↓
CLKEN after CLK↓
t
2
2
1
1
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT16600 SN74ABT16600
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
150
1.5
1.5
2
TYP
MAX
MIN
150
1.5
1.5
2
MAX
MIN
150
1.5
1.5
2
MAX
f
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
2.5
3.2
3.2
3.4
3.5
3.5
3.4
3.8
4.5
3.4
3.6
4.5
4.5
4.5
4.7
4.3
4.6
4.7
5.4
4.7
4.2
5.1
5.6
5.4
5.4
5.2
5.3
5.6
6.6
5.8
4
4.9
5
A or B
B or A
B or A
B or A
B or A
B or A
LEAB or LEBA
ns
ns
ns
ns
2
2
2
5
2
2
2
5.3
5
CLKAB or CLKBA
OEAB or OEBA
OEAB or OEBA
2
2
2
1.5
2
1.5
2
1.5
2
5.1
5.4
6.2
5.4
2
2
2
1.5
1.5
1.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16600, SN74ABT16600
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS209B – JUNE 1992 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
SN74ABT16600DL
OBSOLETE
OBSOLETE
SSOP
SSOP
DL
56
56
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
SN74ABT16600DLG4
DL
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2014
Addendum-Page 2
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