SN74ABT32245PZ [TI]
36-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS;
| 型号： | SN74ABT32245PZ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 36-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 信息通信管理 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT32245, SN74ABT32245
36-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS228C – JUNE 1992 – APRIL 1995
• Members of the Texas Instruments
• Distributed V
and GND Pin Configuration
CC
Widebus+ Family
Minimizes High-Speed Switching Noise
• High-Drive Outputs (–32-mA I
• State-of-the-Art EPIC-ΙΙB BiCMOS Design
,
OH
Significantly Reduces Power Dissipation
64-mA I
)
OL
• Latch-Up Performance Exceeds 500 mA
• Bus-Hold Inputs Eliminate the Need for
Per JEDEC Standard JESD-17
External Pullup Resistors
• Typical V
(Output Ground Bounce)
• Packaged in 100-Pin Plastic Thin Quad
Flat (PZ) Package With 14 × 14-mm Body
Using 0.5-mm Lead Pitch
OLP
< 0.8 V at V
= 5 V, T = 25°C
CC
A
SN74ABT32245 . . . PZ PACKAGE
(TOP VIEW)
1009998 9796 959493 92 9190 89 8887 86 8584 83 8281 8079 7877 76
1A9
2A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1B9
2B1
GND
2B2
2B3
2B4
2B5
GND
2B6
2B7
2B8
2B9
GND
2A2
2A3
2A4
2A5
GND
2A6
2A7
2A8
2A9
V
V
CC
CC
3A1
3A2
3A3
3A4
GND
3A5
3A6
3A7
3A8
GND
3A9
4A1
3B1
3B2
3B3
3B4
GND
3B5
3B6
3B7
3B8
GND
3B9
4B1
26 272829 3031 32 33 343536 3738 3940 4142 43 4445 46 474849 50
description
The ′ABT32245 are 36-bit (quad 9-bit) noninverting 3-state transceivers designed for synchronous two-way
communication between data buses. The control-function implementation minimizes external timing
requirements.
These devices can be used as four 9-bit transceivers, two18-bit transceivers, or one 36-bit transceiver. They
allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic
level at the direction-control (DIR) inputs. The output-enable (OE) inputs can be used to disable the device so
that the buses are effectively isolated.
Widebus+ and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT32245, SN74ABT32245
36-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS228C – JUNE 1992 – APRIL 1995
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
The SN54ABT32245 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT32245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 9-bit section)
INPUTS
OPERATION
DIR
L
OE
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT32245, SN74ABT32245
36-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS228C – JUNE 1992 – APRIL 1995
logic diagram (positive logic)
40
14
90
1DIR
3DIR
3A1
89
84
39
1OE
1B1
3OE
One of Nine
Channels
One of Nine
Channels
92
1A1
62
3B1
To Eight Other Channels
To Eight Other Channels
86
36
25
2DIR
2A1
4DIR
4A1
87
74
37
2OE
2B1
4OE
One of Nine
Channels
One of Nine
Channels
2
51
4B1
To Eight Other Channels
To Eight Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V
. . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT32245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT32245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Maximum power dissipation at T = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
A
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils.
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology
Data Book, literature number SCBD002B.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT32245, SN74ABT32245
36-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS228C – JUNE 1992 – APRIL 1995
recommended operating conditions
SN54ABT32245
SN74ABT32245
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
0
V
CC
V
I
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
–24
48
–32
64
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
Operating free-air temperature
125
85
A
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT32245, SN74ABT32245
36-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS228C – JUNE 1992 – APRIL 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ABT32245
SN74ABT32245
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
2
V
V
= 4.5 V
CC
2
0.55
0.55
0.55
V
OL
= 4.5 V
V
CC
Control
inputs
V
V
= 0 to 5.5 V,
V = V
or GND
or GND
±1
±1
CC
I
CC
CC
I
I
µA
µA
I
A or B ports
= 2.1 V to 5.5 V, V = V
±20
±20
CC
I
V = 0.8 V
I
100
100
A or B ports
V
= 4.5 V
I(hold)
CC
CC
V = 2 V
I
–100
–100
V
= 0 to 2.1 V,
V
O
= 0.5 V to 2.7 V,
‡
I
I
±50
±50
±50
±50
µA
µA
OZPU
OE = X
V
= 2.1 V to 0,
V
O
= 0.5 V to 2.7 V,
CC
OE = X
‡
OZPD
§
I
I
I
I
I
V
V
V
V
V
= 2.1 V to 5.5 V,
= 2.1 V to 5.5 V,
= 0,
V
V
= 2.7 V,
= 0.5 V,
OE ≥ 2 V
OE ≥ 2 V
10
–10
±100
50
10
–10
±100
50
µA
µA
µA
µA
mA
OZH
CC
CC
CC
CC
CC
O
§
OZL
O
V or V ≤ 4.5 V
I
off
O
= 5.5 V,
V
O
V
O
= 5.5 V
Outputs high
CEX
¶
= 5.5 V,
= 2.5 V
–50
–100
–180
3
–50
–100
–180
3
O
Outputs high
Outputs low
V
I
= 5.5 V,
= 0,
CC
O
I
20
20
mA
mA
CC
V = V
I
or GND
CC
Outputs disabled
2
2
V
= 5.5 V,
One input at 3.4 V,
CC
Other inputs at V
#
1
1
∆I
CC
or GND
CC
Control
inputs
C
C
V = 2.5 V or 0.5 V
3.5
9.5
3.5
9.5
pF
pF
i
I
A or B ports
V
O
= 2.5 V or 0.5 V
io
†
‡
§
¶
#
All typical values are at V
This parameter is specified by characterization.
= 5 V, T = 25°C.
A
CC
The parameters I
and I
include the input leakage current.
OZL
OZH
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT32245, SN74ABT32245
36-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS228C – JUNE 1992 – APRIL 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT32245
SN74ABT32245
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.7
1.7
1.6
2.7
1.3
2
TYP
3.2
3.3
4.2
5.2
3.9
4.4
MAX
4.4
4.6
6.1
7
MIN
1.7
1.7
1.6
2.7
1.3
2
MAX
5.3
5.3
7.6
8.2
6.7
7.2
MIN
1.7
1.7
1.6
2.7
1.3
2
MAX
5
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
A or B
B or A
B or A
B or A
ns
ns
ns
5.2
7.3
8.1
6.5
6.9
OE
OE
6.1
6.6
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT32245, SN74ABT32245
36-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS228C – JUNE 1992 – APRIL 1995
PARAMETER MEASUREMENT INFORMATION
7 V
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
7 V
PLH PHL
/t
C
= 50 pF
L
t
500 Ω
PLZ PZL
/t
(see Note A)
Open
PHZ PZH
LOAD CIRCUIT FOR OUTPUTS
3 V
0 V
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 7 V
V
V
3.5 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
t
PZH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
C includes probe and jig capacitance.
L
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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