SN74ABT5403DWRG4 [TI]
ABT SERIES, 12-BIT DRIVER, INVERTED OUTPUT, PDSO28, PLASTIC, SO-28;
| 型号： | SN74ABT5403DWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ABT SERIES, 12-BIT DRIVER, INVERTED OUTPUT, PDSO28, PLASTIC, SO-28 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总9页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT5403, SN74ABT5403
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS236B – JUNE 1992 – REVISED JANUARY 1997
SN54ABT5403 . . . JT PACKAGE
SN74ABT5403 . . . DW PACKAGE
(TOP VIEW)
Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Y1
Y2
Y3
Y4
Y5
Y6
GND
Y7
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
(Output Ground Bounce) < 1 V
OLP
at V
= 5 V, T = 25°C
CC
A
Typical V
(Output Undershoot) < 0.5 V at
OLV
V
= 5 V, T = 25°C
V
CC
CC
A
Y8
D8
Package Options Include Plastic
Small-Outline (DW) Package, Ceramic Chip
Carriers (FK), and DIPs (JT)
Y9 10
19 D9
Y10
Y11
D10
D11
11
12
18
17
Y12 13
OE1 14
16 D12
15 OE2
description
These 12-bit buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters.
SN54ABT5403 . . . FK PACKAGE
(TOP VIEW)
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1or OE2)inputishigh, all12outputsareinthe
high-impedance state. These devices provide
inverted data.
4
3
2
1
28 27 26
25
5
D3
D2
D1
Y1
Y2
Y3
Y4
D10
D11
D12
OE2
OE1
Y12
Y11
6
24
23
22
21
20
19
7
8
The outputs, which are designed to source or sink
up to 12 mA, include equivalent 25-Ω series
resistors to reduce overshoot and undershoot.
9
10
11
12 13 14 15 16 17 18
To ensure the high-impedance state during power
up or power down, OE should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
The SN54ABT5403 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT5403 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE1
L
OE2
L
D
L
H
L
L
L
H
X
X
H
X
Z
Z
X
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT5403, SN74ABT5403
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS236B – JUNE 1992 – REVISED JANUARY 1997
†
logic diagram (positive logic)
logic symbol
14
&
OE1
14
15
OE1
EN
OE2
15
OE2
28
1
Y1
D1
28
1
2
D1
D2
Y1
1
27
26
25
24
23
22
20
19
18
17
16
Y2
3
D3
Y3
To 11 Other Channels
4
D4
Y4
5
D5
Y5
6
D6
Y6
8
D7
Y7
9
D8
Y8
10
11
12
13
D9
Y9
D10
D11
D12
Y10
Y11
Y12
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the DW and JT packages.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT5403, SN74ABT5403
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS236B – JUNE 1992 – REVISED JANUARY 1997
recommended operating conditions (see Note 3)
SN54ABT5403 SN74ABT5403
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–12
12
–12
12
mA
mA
ns/V
°C
OH
OL
∆t/∆v
Outputs enabled
10
10
T
–55
125
–40
85
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT5403 SN74ABT5403
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
= 4.5 V,
= 5 V,
I
I
I
I
I
I
= –1 mA
= –1 mA
= –3 mA
= –12 mA
= 8 mA
3.35
3.85
3.7
4.2
3.3
3.8
3
3.35
3.85
3.1
OH
OH
OH
OH
OL
OL
V
OH
V
= 4.5 V
= 4.5 V
CC
CC
2.6
2.6
0.8
0.65
0.8
V
V
V
V
OL
= 12 mA
100
mV
µA
µA
µA
µA
hys
I
I
I
I
V
V
V
V
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 0,
V = V or GND
I CC
±1
50
±1
50
±1
50
I
CC
CC
CC
CC
CC
V
= 2.7 V
= 0.5 V
OZH
OZL
off
O
O
V
–50
±100
–50
–50
±100
V or V ≤ 4.5 V
I
O
V
V
= 5.5 V,
= 5.5 V
I
Outputs high
50
50
50
µA
CEX
O
I
I
V
= 5.5 V,
= 5.5 V,
V
V
= 2.5 V
= 0
–25
–50
–45
–100
–200
50
–25
–50
–100
–200
50
–25
–50
–100
–200
50
mA
mA
µA
O
CC
CC
O
‡
V
OS
O
Outputs high
Outputs low
5
36
1
V
I
= 5.5 V,
= 0,
CC
O
I
45
45
45
mA
µA
CC
V = V
I
or GND
CC
Outputs disabled
50
50
50
V
= 5.5 V,
CC
Outputs enabled
Outputs disabled
1.5
0.05
1.5
1.5
0.05
1.5
1.5
0.05
1.5
One input at 3.4 V,
Other inputs at
Data inputs
§
∆I
CC
mA
V
CC
or GND
V
CC
= 5.5 V, One input at 3.4 V,
or GND
Control inputs
Other inputs at V
CC
V = 2.5 V or 0.5 V
C
C
3
8
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
†
‡
§
All typical values are at V
= 5 V.
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT5403, SN74ABT5403
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS236B – JUNE 1992 – REVISED JANUARY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT5403 SN74ABT5403
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
2
TYP
4.5
4.4
5.7
4.4
3.6
4.2
MAX
6.1
5.2
6.6
5.5
4.4
5.4
MIN
2
MAX
7
MIN
2
MAX
6.9
5.7
8.5
6.8
5.2
6.9
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Y
Y
Y
ns
ns
ns
1.5
2.5
2
1.5
2.5
2
5.9
8.6
6.9
5.5
7.4
1.5
2.5
2
OE
OE
1.5
1.5
1.5
1.5
1.5
1.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT5403, SN74ABT5403
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS236B – JUNE 1992 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
7 V
PLH PHL
/t
C
= 50 pF
L
t
500 Ω
PLZ PZL
/t
(see Note A)
Open
PHZ PZH
LOAD CIRCUIT
3 V
0 V
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 7 V
V
V
3.5 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
t
PZH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 n
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
PACKAGING INFORMATION
Orderable Device
SN74ABT5403DWR
SN74ABT5403DWRE4
SN74ABT5403DWRG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
28
28
28
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
DW
DW
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74ABT5403DWR
SOIC
DW
28
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 28
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 49.0
SN74ABT5403DWR
1000
Pack Materials-Page 2
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