SN74ABT574ADWR [TI]
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS; 八路边沿触发D型触发器具有三态输出
| 型号： | SN74ABT574ADWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| 文件： | 总20页 (文件大小：761K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢂ ꢇ ꢃ ꢈ ꢀꢁꢇ ꢃ ꢄ ꢅꢆ ꢂꢇ ꢃꢄ
ꢉ ꢊꢆꢄꢋ ꢌꢍ ꢎꢌ ꢏꢆꢐ ꢑꢎ ꢎꢌ ꢐꢌꢍ ꢍꢏꢆ ꢒꢓ ꢌ ꢔ ꢋꢑ ꢓ ꢏꢔ ꢋꢉ ꢓꢀ
ꢕ ꢑꢆ ꢖ ꢗ ꢏꢀꢆꢄꢆ ꢌ ꢉ ꢘꢆ ꢓ ꢘꢆꢀ
SCBS191F − JANUARY 1991 − REVISED SEPTEMBER 2003
D
Typical V
(Output Ground Bounce)
D
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD 17
OLP
<1 V at V
= 5 V, T = 25°C
CC
A
D
High-Drive Outputs (−32-mA I , 64-mA I
)
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
OH
OL
D
I
Supports Partial-Power-Down Mode
off
Operation
SN54ABT574 . . . J OR W PACKAGE
SN74ABT574A . . . DB, DW, N, NS,
OR PW PACKAGE
SN74ABT574A . . . RGY PACKAGE
(TOP VIEW)
SN54ABT574 . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
1
20
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
3
2
1
20 19
18
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
1D
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
2Q
3Q
4Q
5Q
6Q
1Q
2Q
3Q
4Q
3D
4D
5D
6D
7D
4
5
6
7
8
17
16
15
14
15 5Q
14 6Q
9 10 11 12 13
13
12
11
7Q
8Q
CLK
10
11
GND
description/ordering information
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube
SN74ABT574AN
SN74ABT574AN
AB574A
QFN − RGY
Tape and reel SN74ABT574ARGYR
Tube SN74ABT574ADW
SOIC − DW
ABT574A
Tape and reel SN74ABT574ADWR
Tape and reel SN74ABT574ANSR
Tape and reel SN74ABT574ADBR
SOP − NS
ABT574A
AB574A
−40°C to 85°C
SSOP − DB
Tube
SN74ABT574APW
TSSOP − PW
AB574A
AB574A
Tape and reel SN74ABT574APWR
SN74ABT574AGQNR
VFBGA − GQN
VFBGA − ZQN (Pb-free)
CDIP − J
Tape and reel
SN74ABT574AZQNR
Tube
Tube
Tube
SNJ54ABT574J
SNJ54ABT574W
SNJ54ABT574FK
SNJ54ABT574J
SNJ54ABT574W
SNJ54ABT574FK
CFP − W
−55°C to 125°C
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
ꢉ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢯꢑ ꢋꢏ ꢓꢐ ꢔ ꢏꢗꢰꢂ ꢗꢂꢈ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢂꢇ ꢃꢈ ꢀꢁꢇ ꢃ ꢄꢅ ꢆꢂ ꢇ ꢃ ꢄ
ꢉꢊ ꢆꢄ ꢋ ꢌꢍ ꢎꢌꢏ ꢆꢐ ꢑꢎ ꢎꢌ ꢐꢌ ꢍ ꢍꢏꢆ ꢒ ꢓꢌ ꢔꢋ ꢑ ꢓꢏꢔ ꢋ ꢉ ꢓꢀ
ꢕꢑ ꢆ ꢖ ꢗ ꢏꢀꢆꢄꢆ ꢌ ꢉꢘꢆ ꢓ ꢘꢆꢀ
SCBS191F − JANUARY 1991 − REVISED SEPTEMBER 2003
description/ordering information (continued)
The eight flip-flops of the SN54ABT574 and SN74ABT574A are edge-triggered D-type flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
SN74ABT574A . . . GQN OR ZQN PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
1
1D
2
3
4
A
B
C
D
E
A
B
C
D
E
OE
3Q
4D
7Q
8D
V
1Q
2Q
4Q
6Q
8Q
CC
3D
2D
5Q
5D
7D
6D
GND
CLK
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
H or L
X
X
X
Q
0
H
Z
logic diagram (positive logic)
1
OE
11
CLK
C1
19
1Q
2
1D
1D
To Seven Other Channels
Pin numbers shown are for the DB, DW, FK, J, N, NS, PW, RGY, and W packages.
2
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ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢂ ꢇ ꢃ ꢈ ꢀꢁ ꢇꢃ ꢄꢅ ꢆꢂ ꢇꢃ ꢄ
ꢉ ꢊꢆꢄꢋ ꢌꢍꢎ ꢌ ꢏꢆꢐ ꢑꢎ ꢎꢌ ꢐꢌꢍ ꢍꢏꢆ ꢒꢓ ꢌ ꢔ ꢋꢑ ꢓ ꢏꢔ ꢋꢉ ꢓꢀ
ꢕ ꢑꢆ ꢖ ꢗ ꢏꢀꢆꢄꢆ ꢌ ꢉ ꢘꢆ ꢓꢘ ꢆꢀ
SCBS191F − JANUARY 1991 − REVISED SEPTEMBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT574A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
(see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 2): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
(see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
(see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
SN54ABT574 SN74ABT574A
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
0
V
CC
V
I
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−24
48
−32
64
5
mA
mA
ns/V
°C
OH
OL
∆t/∆v
Outputs enabled
5
T
−55
125
−40
85
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢂꢇ ꢃꢈ ꢀꢁꢇ ꢃ ꢄꢅ ꢆꢂ ꢇ ꢃ ꢄ
ꢉꢊ ꢆꢄ ꢋ ꢌꢍ ꢎꢌꢏ ꢆꢐ ꢑꢎ ꢎꢌ ꢐꢌ ꢍ ꢍꢏꢆ ꢒ ꢓꢌ ꢔꢋ ꢑ ꢓꢏꢔ ꢋ ꢉ ꢓꢀ
ꢕꢑ ꢆ ꢖ ꢗ ꢏꢀꢆꢄꢆ ꢌ ꢉꢘꢆ ꢓ ꢘꢆꢀ
SCBS191F − JANUARY 1991 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT574 SN74ABT574A
A
PARAMETER
TEST CONDITIONS
I = −18 mA
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
IK
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
−1.2
−1.2
−1.2
V
CC
CC
CC
I
I
I
I
I
I
I
= −3 mA
= −3 mA
= −24 mA
= −32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
V
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
1
V
V
V
V
OL
0.55*
0.55
1
100
mV
µA
µA
µA
µA
µA
mA
µA
mA
µA
hys
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 0,
V = V
I CC
or GND
1
I
‡
10
‡
10
‡
10
V
O
V
O
= 2.7 V
= 0.5 V
OZH
OZL
off
‡
−10
‡
−10
‡
−10
V or V ≤ 4.5 V
100
50
500
50
100
50
I
O
= 5.5 V,
= 5.5 V,
V
= 5.5 V
Outputs high
CEX
O
O
§
V
= 2.5 V
−50 −100 −180
−50 −180
−50
−180
250
30
O
Outputs high
Outputs low
1
24
250
30
250
30
V
= 5.5 V, I = 0,
O
CC
I
CC
V = V
I
or GND
CC
Outputs disabled
0.5
250
250
250
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
¶
1.5
1.5
1.5
mA
∆I
CC
or GND
CC
V = 2.5 V or 0.5 V
C
C
3.5
6.5
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
CC
This data-sheet limit may vary among suppliers.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V or GND.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT574
V
T
= 5 V,
= 25°C
CC
A
UNIT
MIN
MAX
MIN
MAX
f
t
Clock frequency
150
150
MHz
ns
clock
Pulse duration, CLK high or low
3.3
1.5
2
3.3
1.5
2
w
High
t
t
ns
ns
Setup time, data before CLK↑
Hold time, data after CLK↑
su
Low
High or low
2
2
h
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢂ ꢇ ꢃ ꢈ ꢀꢁ ꢇꢃ ꢄꢅ ꢆꢂ ꢇꢃ ꢄ
ꢉ ꢊꢆꢄꢋ ꢌꢍꢎ ꢌ ꢏꢆꢐ ꢑꢎ ꢎꢌ ꢐꢌꢍ ꢍꢏꢆ ꢒꢓ ꢌ ꢔ ꢋꢑ ꢓ ꢏꢔ ꢋꢉ ꢓꢀ
ꢕ ꢑꢆ ꢖ ꢗ ꢏꢀꢆꢄꢆ ꢌ ꢉ ꢘꢆ ꢓꢘ ꢆꢀ
SCBS191F − JANUARY 1991 − REVISED SEPTEMBER 2003
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN74ABT574A
V
T
= 5 V,
= 25°C
CC
A
UNIT
MIN
MAX
MIN
MAX
f
t
Clock frequency
150
150
MHz
ns
clock
Pulse duration, CLK high or low
3.3
1
3.3
1
w
High
t
t
ns
ns
Setup time, data before CLK↑
Hold time, data after CLK↑
su
Low
1.5
1.5
†
1.8
†
1.8
High or low
h
†
This data-sheet limit may vary among suppliers.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN54ABT574
V
T
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
CC
A
PARAMETER
UNIT
= 25°C
TYP
200
3.9
MIN
MAX
MIN
150
2.2
3
MAX
f
t
t
t
t
t
t
150
2.2
3
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
6.2
7
7
7.4
5.8
7.2
7.2
6.9
CLK
OE
Q
Q
Q
4.8
1
3.3
5
1
ns
ns
2.5
2.4
2
4.7
5.9
6.2
5.8
2.5
2.4
2
4.9
OE
4
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN74ABT574A
= 5 V,
V
T
FROM
(INPUT)
TO
(OUTPUT)
CC
A
PARAMETER
UNIT
= 25°C
TYP
200
3.9
MIN
MAX
MIN
MAX
f
t
t
t
t
t
t
150
2.2
3
150
2.2
3
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
6.2
6.6
4.3
5.9
6.2
5.8
6.8
7.1
5.1
6.7
7
CLK
OE
Q
Q
Q
4.8
1
3.3
1
ns
ns
†
†
2.1
2.1
4.7
2.4
2
4.9
2.4
2
OE
4
6.5
†
This data-sheet limit may vary among suppliers.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢂꢇ ꢃꢈ ꢀꢁꢇ ꢃ ꢄꢅ ꢆꢂ ꢇ ꢃ ꢄ
ꢉꢊ ꢆꢄ ꢋ ꢌꢍ ꢎꢌꢏ ꢆꢐ ꢑꢎ ꢎꢌ ꢐꢌ ꢍ ꢍꢏꢆ ꢒ ꢓꢌ ꢔꢋ ꢑ ꢓꢏꢔ ꢋ ꢉ ꢓꢀ
ꢕꢑ ꢆ ꢖ ꢗ ꢏꢀꢆꢄꢆ ꢌ ꢉꢘꢆ ꢓ ꢘꢆꢀ
SCBS191F − JANUARY 1991 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
7 V
TEST
S1
Open
S1
500 Ω
From Output
Under Test
t
/t
PLH PHL
Open
7 V
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
t
t
PZL
PLZ
PLH
PHL
PHL
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
PHZ
OL
V
OL
OL
(see Note B)
t
t
PZH
t
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9322001Q2A
5962-9322001QRA
5962-9322001QSA
SN74ABT574ADBLE
SN74ABT574ADBR
ACTIVE
ACTIVE
FK
J
20
20
20
20
20
1
1
1
None
None
None
None
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Call TI
ACTIVE
W
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
2000
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74ABT574ADW
SN74ABT574ADWR
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
20
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SN74ABT574AGQNR
SN74ABT574AN
ACTIVE
ACTIVE
VFBGA
PDIP
GQN
N
20
20
1000
20
None
SNPB
Level-1-240C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74ABT574ANSR
SN74ABT574APW
ACTIVE
ACTIVE
SO
NS
20
20
2000
70
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
TSSOP
PW
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SN74ABT574APWLE
SN74ABT574APWR
OBSOLETE TSSOP
PW
PW
20
20
None
Call TI
Call TI
ACTIVE
ACTIVE
ACTIVE
TSSOP
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SN74ABT574ARGYR
SN74ABT574AZQNR
QFN
RGY
ZQN
20
20
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
VFBGA
1000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
SNJ54ABT574FK
SNJ54ABT574J
SNJ54ABT574W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
1
1
1
None
None
None
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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