SN74ABT652ADBE4 [TI]
IC ABT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, PLASTIC, SSOP-24, Bus Driver/Transceiver;
| 型号： | SN74ABT652ADBE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC ABT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, PLASTIC, SSOP-24, Bus Driver/Transceiver 输入元件 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总13页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCBS070D − JULY 1991 − REVISED JULY 1994
SN54ABT652 . . . JT PACKAGE
SN74ABT652 . . . DB, DW, OR NT PACKAGE
(TOP VIEW)
• State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
1
24
23
22
21
20
19
18
17
16
15
14
13
CLKAB
SAB
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
2
CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
3
• Latch-Up Performance Exceeds 500 mA
4
Per JEDEC Standard JESD-17
5
6
• Typical V
(Output Ground Bounce)
OLP
CC
7
< 1 V at V
= 5 V, T = 25°C
A
8
• High-Drive Outputs (−32-mA I
,
OH
9
64-mA I
)
OL
10
11
12
• Package Options Include Plastic
Small-Outline ((DW)) and Shrink
B8
Small-Outline (DB) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs
SN54ABT652 . . . FK PACKAGE
(TOP VIEW)
description
These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
4
3
2 1 28 27 26
5
25
24
23
22
21
20
19
A1
A2
A3
NC
A4
A5
A6
OEBA
B1
B2
NC
B3
B4
6
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. The circuitry used for select control
eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between
stored and real-time data. A low input selects
real-time data, and a high input selects stored
data. Figure 1 illustrates the four fundamental
bus-management functions that can be performed
with the ′ABT652.
7
8
9
10
11
B5
12 13 14 15 16 17 18
NC − No internal connection
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by
simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other
data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to V
through a
CC
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
The SN74ABT652 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
ꢏ ꢁꢎ ꢑꢀꢀ ꢌ ꢆꢗ ꢑꢐꢖ ꢒꢀ ꢑ ꢁ ꢌꢆꢑ ꢔ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣ ꢤꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢚꢐ ꢌ ꢔ ꢏ ꢍꢆ ꢒꢌ ꢁ
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2−1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢂꢈ ꢉ ꢊ ꢀ ꢁꢋ ꢃ ꢄꢅꢆ ꢇ ꢂ ꢈ
ꢌꢍ ꢆꢄ ꢎꢊ ꢅ ꢏꢀ ꢊ ꢆꢐꢄ ꢁꢀ ꢍꢑ ꢒ ꢓꢑ ꢐꢀ ꢊꢄꢁ ꢔꢊ ꢐꢑꢕ ꢒ ꢀꢆ ꢑꢐꢀ
ꢖꢒ ꢆ ꢗ ꢊꢘ ꢙꢀ ꢆꢄꢆꢑ ꢊ ꢌ ꢏꢆ ꢚꢏꢆ ꢀ
SCBS070D − JULY 1991 − REVISED JULY 1994
description (continued)
The SN54ABT652 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74ABT652 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
†
DATA I/O
INPUTS
CLKAB
OPERATION OR FUNCTION
OEAB
OEBA
CLKBA
SAB
X
SBA
X
A1 THRU A8
Input
B1 THRU B8
Input
L
L
H
H
H
H
X
L
H or L
H or L
Isolation
↑
↑
X
X
Input
Input
Store A and B data
‡
X
H
L
↑
H or L
X
X
Input
Unspecified
Store A, hold B
‡
X
↑
↑
X
Input
Output
Input
Store A in both registers
Hold A, store B
‡
H or L
↑
X
X
X
X
L
X
Unspecified
‡
X
L
↑
X
↑
X
Output
Output
Output
Input
Input
Store B in both registers
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
L
L
H
X
X
Input
L
L
X
H or L
X
Input
H
H
H
H
X
Output
Output
H or L
X
H
Input
Stored A data to B bus and
stored B data to A bus
H
L
H or L
H or L
H
H
Output
Output
†
‡
The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are
always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs.
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered in order to load both registers.
2−2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCBS070D − JULY 1991 − REVISED JULY 1994
3
21
1
23
2
22
SBA
L
3
21
1
23
2
22
SBA
X
CLKAB CLKBA SAB
CLKAB CLKBA SAB
OEAB OEBA
L
OEAB OEBA
H
L
X
X
X
H
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
3
21
1
23
2
22
SBA
X
3
21
1
23
2
22
SBA
H
CLKAB CLKBA SAB
CLKAB CLKBA SAB
OEAB OEBA
OEAB OEBA
X
L
L
H
X
H
X
↑
↑
X
X
X
H
L
L
L
H
↑
X
X
X
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
Pin numbers shown are for the DB, DW, JT, and NT packages.
2−3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢂꢈ ꢉ ꢊ ꢀ ꢁꢋ ꢃ ꢄꢅꢆ ꢇ ꢂ ꢈ
ꢌꢍ ꢆꢄ ꢎꢊ ꢅ ꢏꢀ ꢊ ꢆꢐꢄ ꢁꢀ ꢍꢑ ꢒ ꢓꢑ ꢐꢀ ꢊꢄꢁ ꢔꢊ ꢐꢑꢕ ꢒ ꢀꢆ ꢑꢐꢀ
ꢖꢒ ꢆ ꢗ ꢊꢘ ꢙꢀ ꢆꢄꢆꢑ ꢊ ꢌ ꢏꢆ ꢚꢏꢆ ꢀ
SCBS070D − JULY 1991 − REVISED JULY 1994
†
logic symbol
21
OEBA
EN1 [BA]
EN2 [AB]
3
OEAB
CLKBA
SBA
23
22
1
C4
G5
CLKAB
SAB
C6
G7
2
20
4D
2
B1
5
5
≥1
4
A1
1
1
6D
7
7
≥1
1
5
19
18
17
16
15
14
13
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
6
7
8
9
10
11
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, and NT packages.
2−4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢌ ꢍꢆꢄꢎꢊꢅ ꢏꢀꢊ ꢆꢐꢄ ꢁꢀꢍꢑ ꢒꢓꢑ ꢐꢀꢊꢄꢁꢔ ꢊꢐꢑꢕ ꢒ ꢀ ꢆꢑ ꢐ
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ꢖ ꢒꢆ ꢗꢊ ꢘ ꢙꢀꢆꢄꢆ ꢑꢊꢌ ꢏ ꢆꢚ ꢏꢆ
SCBS070D − JULY 1991 − REVISED JULY 1994
logic diagram (positive logic)
21
OEBA
3
OEAB
23
CLKBA
22
SBA
1
CLKAB
2
SAB
One of Eight
Channels
1D
C1
4
A1
20
B1
1D
C1
To Seven Other Channels
Pin numbers shown are for the DB, DW, JT, and NT packages.
2−5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢂꢈ ꢉ ꢊ ꢀ ꢁꢋ ꢃ ꢄꢅꢆ ꢇ ꢂ ꢈ
ꢌꢍ ꢆꢄ ꢎꢊ ꢅ ꢏꢀ ꢊ ꢆꢐꢄ ꢁꢀ ꢍꢑ ꢒ ꢓꢑ ꢐꢀ ꢊꢄꢁ ꢔꢊ ꢐꢑꢕ ꢒ ꢀꢆ ꢑꢐꢀ
ꢖꢒ ꢆ ꢗ ꢊꢘ ꢙꢀ ꢆꢄꢆꢑ ꢊ ꢌ ꢏꢆ ꢚꢏꢆ ꢀ
SCBS070D − JULY 1991 − REVISED JULY 1994
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V
. . . . . . . . . . . . . −0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . 0.65 W
A
DW package . . . . . . . . . . . . . . . . . . . 1.7 W
NT package . . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the NT package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
SN54ABT652 SN74ABT652
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−24
48
−32
64
5
mA
mA
ns/V
°C
OH
OL
∆t/∆v
5
T
−55
125
−40
85
A
NOTE 3: Unused or floating pins (input or I/O) must be held high or low.
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ꢡ ꢜꢦ ꢥ ꢰꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠꢟ ꢢꢡꢛ ꢞ ꢮ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢬ
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2−6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
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ꢌ ꢍꢆꢄꢎꢊꢅ ꢏꢀꢊ ꢆꢐꢄ ꢁꢀꢍꢑ ꢒꢓꢑ ꢐꢀꢊꢄꢁꢔ ꢊꢐꢑꢕ ꢒ ꢀ ꢆꢑ ꢐ
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ꢖ ꢒꢆ ꢗꢊ ꢘ ꢙꢀꢆꢄꢆ ꢑꢊꢌ ꢏ ꢆꢚ ꢏꢆ
SCBS070D − JULY 1991 − REVISED JULY 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT652 SN74ABT652
A
PARAMETER
TEST CONDITIONS
I = −18 mA
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
IK
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
−1.2
−1.2
−1.2
V
CC
CC
CC
I
I
I
I
I
I
I
= −3 mA
= −3 mA
= −24 mA
= −32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
V
2
2
V
CC
= 4.5 V
2*
2
0.55
0.55*
1
0.55
V
OL
V
V
= 4.5 V
= 5.5 V,
V
CC
0.55
1
Control inputs
A or B ports
1
100
50
CC
I
I
µA
V = V
I CC
or GND
100
50
100
50
‡
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 0,
V
V
= 2.7 V
= 0.5 V
µA
µA
µA
µA
mA
µA
mA
µA
OZH
O
‡
−50
100
50
−50
−50
100
50
OZL
off
O
V or V ≤ 4.5 V
I
O
= 5.5 V,
= 5.5 V,
V
= 5.5 V
Outputs high
50
CEX
O
O
§
V
= 2.5 V
−50 −100 −180
−50 −180
−50 −180
O
Outputs high
Outputs low
250
30
250
30
250
30
V
= 5.5 V,
I
O
= 0,
CC
I
CC
V = V
I
or GND
CC
Outputs disabled
250
250
250
V
= 5.5 V,
One input at 3.4 V,
or GND
CC
Other inputs at V
¶
1.5
1.5
1.5
mA
∆I
CC
CC
V = 2.5 V or 0.5 V
C
C
Control inputs
A or B ports
7
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
12
io
* On products compliant to MIL-STD-883, Class B, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
include the input leakage current.
CC
OZL
The parameters I
and I
OZH
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
V
T
= 5 V,
= 25°C
CC
A
SN54ABT652 SN74ABT652
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
t
t
Clock frequency
125
125
125
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
4
4
4
w
3.5
0
3.5
0
3.5
0
ns
su
h
ns
ꢚ
ꢐ
ꢌ
ꢔ
ꢏ
ꢍ
ꢆ
ꢚ
ꢐ
ꢑ
ꢓ
ꢒ
ꢑ
ꢖ
ꢝ
ꢥ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢡ
ꢠ
ꢥ
ꢡ
ꢤ
ꢨ
ꢥ
ꢞ
ꢩ
ꢨ
ꢠ
ꢟ
ꢢ
ꢟꢤ ꢞ ꢝ ꢰꢥ ꢩꢜ ꢦ ꢞ ꢤ ꢠꢧ ꢟꢤ ꢱ ꢤ ꢫꢠ ꢩꢣꢤ ꢥꢛꢬ ꢍ ꢜꢦ ꢨꢦ ꢡꢛ ꢤꢨ ꢝꢞ ꢛꢝ ꢡ ꢟꢦ ꢛꢦ ꢦꢥ ꢟ ꢠꢛ ꢜꢤꢨ
ꢡ
ꢛ
ꢞ
ꢝ
ꢥ
ꢛ
ꢜ
ꢤ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢱ
ꢤ
ꢠ
ꢨ
ꢞ
ꢩ
ꢤ
ꢡ
ꢝ
ꢧ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢞ
ꢦ
ꢨ
ꢤ
ꢟ
ꢤ
ꢞ
ꢝ
ꢰ
ꢥ
ꢰ
ꢠ
ꢦ
ꢫ
ꢞ
ꢬ
ꢆ
ꢤ
ꢭ
ꢦ
ꢞ
ꢒ
ꢥ
ꢞ
ꢛ
ꢨ
ꢢ
ꢣ
ꢡ ꢜꢦ ꢥ ꢰꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠꢟ ꢢꢡꢛ ꢞ ꢮ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢬ
ꢤ
ꢥ
ꢛ
ꢞ
ꢨ
ꢤ
ꢞ
ꢤ
ꢨ
ꢱ
ꢤ
ꢞ
ꢛ
ꢜ
ꢤ
ꢨ
ꢝ
ꢰ
ꢜ
ꢛ
ꢛ
ꢠ
2−7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢂꢈ ꢉ ꢊ ꢀ ꢁꢋ ꢃ ꢄꢅꢆ ꢇ ꢂ ꢈ
ꢌꢍ ꢆꢄ ꢎꢊ ꢅ ꢏꢀ ꢊ ꢆꢐꢄ ꢁꢀ ꢍꢑ ꢒ ꢓꢑ ꢐꢀ ꢊꢄꢁ ꢔꢊ ꢐꢑꢕ ꢒ ꢀꢆ ꢑꢐꢀ
ꢖꢒ ꢆ ꢗ ꢊꢘ ꢙꢀ ꢆꢄꢆꢑ ꢊ ꢌ ꢏꢆ ꢚꢏꢆ ꢀ
SCBS070D − JULY 1991 − REVISED JULY 1994
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 2)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT652 SN74ABT652
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
125
2.2
1.7
1.5
1.5
1.5
1.5
1.3
2.5
1.5
1.5
1.8
2.9
1.5
1.5
TYP
200
5.3
5.9
4.4
4.4
4.6
5.4
3.3
4.5
6.2
5
MIN
MIN
125
2.2
1.7
1.5
1.5
1.5
1.5
1.3
2.5
1.5
1.5
1.8
2.9
1.5
1.5
MAX
MIN
125
2.2
1.7
1.5
1.5
1.5
1.5
1.3
2.5
1.5
1.5
1.8
2.9
1.5
1.5
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
6.8
7.4
5.7
5.7
5.9
6.7
4.6
6.8
7.7
6.3
6.1
6.5
5.7
5.3
8.2
8.8
7
7.8
8.4
6.7
6.7
6.9
7.7
5.8
8.5
8.2
6.8
6.5
7.4
6.9
6.2
CLK
A or B
B or A
B or A
ns
ns
ns
ns
ns
ns
7
7.4
8
†
B or A
SAB or SBA
6
OEBA
A
A
B
B
8.9
8.3
7.1
6.9
7.6
7.1
6.6
OEBA
3.8
4.9
4.5
4.1
OEAB
OEAB
†
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
ꢚ
ꢐ
ꢌ
ꢔ
ꢏ
ꢍ
ꢆ
ꢚ
ꢐ
ꢑ
ꢓ
ꢒ
ꢑ
ꢖ
ꢝ
ꢥ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢡ
ꢠ
ꢥ
ꢡ
ꢤ
ꢨ
ꢥ
ꢞ
ꢩ
ꢨ
ꢠ
ꢟ
ꢢ
ꢟꢤ ꢞ ꢝ ꢰꢥ ꢩꢜ ꢦ ꢞ ꢤ ꢠꢧ ꢟꢤ ꢱ ꢤ ꢫꢠ ꢩꢣꢤ ꢥꢛꢬ ꢍ ꢜꢦ ꢨꢦ ꢡꢛ ꢤꢨ ꢝꢞ ꢛꢝ ꢡ ꢟꢦ ꢛꢦ ꢦꢥ ꢟ ꢠꢛ ꢜꢤꢨ
ꢡ
ꢛ
ꢞ
ꢝ
ꢥ
ꢛ
ꢜ
ꢤ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢱ
ꢤ
ꢠ
ꢨ
ꢞ
ꢩ
ꢤ
ꢡ
ꢝ
ꢧ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢞ
ꢦ
ꢨ
ꢤ
ꢟ
ꢤ
ꢞ
ꢝ
ꢰ
ꢥ
ꢰ
ꢠ
ꢦ
ꢫ
ꢞ
ꢬ
ꢆ
ꢤ
ꢭ
ꢦ
ꢞ
ꢒ
ꢥ
ꢞ
ꢛ
ꢨ
ꢢ
ꢣ
ꢡ ꢜꢦ ꢥ ꢰꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠꢟ ꢢꢡꢛ ꢞ ꢮ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢬ
ꢤ
ꢥ
ꢛ
ꢞ
ꢨ
ꢤ
ꢞ
ꢤ
ꢨ
ꢱ
ꢤꢞ
ꢛ
ꢜ
ꢤ
ꢨ
ꢝ
ꢰ
ꢜ
ꢛ
ꢛ
ꢠ
2−8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢂ
ꢈ
ꢉ
ꢊ
ꢀ
ꢁ
ꢋ
ꢌ ꢍꢆꢄꢎꢊꢅ ꢏꢀꢊ ꢆꢐꢄ ꢁꢀꢍꢑ ꢒꢓꢑ ꢐꢀꢊꢄꢁꢔ ꢊꢐꢑꢕ ꢒ ꢀ ꢆꢑ ꢐ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢂ
ꢈ
ꢀ
ꢀ
ꢖ ꢒꢆ ꢗꢊ ꢘ ꢙꢀꢆꢄꢆ ꢑꢊꢌ ꢏ ꢆꢚ ꢏꢆ
SCBS070D − JULY 1991 − REVISED JULY 1994
PARAMETER MEASUREMENT INFORMATION
7 V
S1
500 Ω
Open
GND
From Output
Under Test
TEST
S1
t
t
/t
Open
7 V
PLH PHL
/t
C
= 50 pF
L
t
500 Ω
PLZ PZL
/t
(see Note A)
Open
PHZ PZH
LOAD CIRCUIT FOR OUTPUTS
3 V
0 V
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Input
(see Note B)
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 7 V
V
V
3.5 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
− 0.3 V
OL
V
OL
OL
(see Note C)
t
PHZ
t
PLH
t
t
PZH
PHL
Output
Waveform 2
S1 at Open
(see Note C)
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
[ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
2−9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
2−10
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ABT652DWR
SOIC
DW
24
2000
330.0
24.4
10.75 15.7
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 24
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
SN74ABT652DWR
2000
Pack Materials-Page 2
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