SN74ABT7819A-12PN [TI]
512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY; 512 】 18 】 2主频双向先入先出存储器
| 型号： | SN74ABT7819A-12PN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY |
| 文件： | 总21页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
Member of the Texas Instruments
Widebus Family
Microprocessor Interface Control Logic
Programmable Almost-Full/Almost-Empty
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
Flag
Fast Access Times of 9 ns With a 50-pF
Load and Simultaneous Switching Data
Outputs
Read and Write Operations Synchronized
to Independent System Clocks
Two Separate 512 × 18 Clocked FIFOs
Data Rates up to 100 MHz
Buffering Data in Opposite Directions
Advanced BiCMOS Technology
IRA and ORA Synchronized to CLKA
IRB and ORB Synchronized to CLKB
Package Options Include 80-Pin Plastic
Quad Flatpack (PH) and 80-Pin Thin Plastic
Quad Flatpack (PN)
PH PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RSTA
PENA
AF/AEA
HFA
RSTB
PENB
AF/AEB
HFB
IRB
GND
B0
B1
IRA
GND
A0
A1
9
V
V
B2
CC
A2
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A3
GND
A4
A5
GND
A6
A7
GND
A8
B3
GND
B4
B5
GND
B6
B7
GND
B8
A9
B9
V
V
CC
CC
A10
A11
B10
B11
GND
GND
25 26 27 28 29 30 3132 33 34 35 36 37 38 39 40
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
PN PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AF/AEA
HFA
IRA
AF/AEB
HFB
IRB
2
3
4
GND
A0
GND
B0
5
6
A1
B1
7
V
V
CC
B2
CC
A2
8
9
A3
B3
10
11
12
13
14
15
16
17
18
19
20
GND
A4
GND
B4
A5
B5
GND
A6
GND
B6
A7
B7
GND
A8
GND
B8
A9
B9
V
V
CC
B10
CC
A10
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ABT7819A is a high-speed, low-power, BiCMOS, bidirectional, clocked FIFO memory.
Twoindependent512×18dual-portSRAMFIFOs(FIFOA, FIFOB)onthechipbufferdatainoppositedirections.
Each FIFO has flags to indicate empty and full conditions, a half-full flag, and a programmable
almost-full/almost-empty flag.
The SN74ABT7819A is a clocked FIFO, which means each port employs a synchronous interface. All data
transfersthroughaportaregatedtothelow-to-hightransitionofacontinuous(free-running)portclockbyenable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The state of the A0–A17 outputs is controlled by the port-A chip select (CSA) and the port-A write/read select
(W/RA). When both CSA and W/RA are low, the outputs are active. The A0–A17 outputs are in the
high-impedance state when either CSA or W/RA is high. Data is written to FIFOA–B from port A on the
low-to-high transition of the port-A clock (CLKA) input when CSA is low, W/RA is high, the port-A write enable
(WENA) is high, and the port-A input-ready (IRA) flag is high. Data is read from FIFOB–A to the A0–A17 outputs
on the low-to-high transition of CLKA when CSA is low, W/RA is low, the port-A read enable (RENA) is high,
and the port-A output-ready (ORA) flag is high.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
description (continued)
The state of the B0–B17 outputs is controlled by the port-B chip select (CSB) and the port-B write/read select
(W/RB). When both CSB and W/RB are low, the outputs are active. The B0–B17 outputs are in the
high-impedance state when either CSB or W/RB is high. Data is written to FIFOB–A from port B on the
low-to-high transition of the port-B clock (CLKB) when CSBis low, W/RB is high, the port-B write enable (WENB)
is high, and the port-B input-ready (IRB) flag is high. Data is read from FIFOA–B to the B0–B17 outputs on the
low-to-high transition of CLKB when CSB is low, W/RB is low, the port-B read enable (RENB) is high, and the
port-B output-ready (ORB) flag is high.
The setup- and hold-time constraints for the chip selects (CSA, CSB) and write/read selects (W/RA, W/RB)
enable write and read operations on memory and are not related to the high-impedance control of the data
outputs. If a port read enable (RENA or RENB) and write enable (WENA or WENB) are set low during a clock
cycle, the chip select and write/read select can switch at any time during the cycle to change the state of the
data outputs.
The input-ready (IR) and output-ready (OR) flags of a FIFO are two-stage synchronized to the port clocks for
use as reliable control signals. CLKA synchronizes the status of the input-ready flag of FIFOA–B (IRA) and the
output-ready flag of FIFOB–A (ORA). CLKB synchronizes the status of the input-ready flag of FIFOB–A (IRB)
and the output-ready flag of FIFOA–B (ORB). When the IR flag of a port is low, the FIFO receiving input from
the port is full and writes are disabled to its array. When the OR flag of a port is low, the FIFO that outputs data
to the port is empty and reads from its memory are disabled. The first word loaded to an empty memory is sent
to the FIFO output register at the same time its OR flag is asserted (high). When the memory is read empty and
the OR flag is forced low, the last valid data remains on the FIFO outputs until the OR flag is asserted (high)
again. In this way, a high on the OR flag indicates new data is present on the FIFO outputs.
The SN74ABT7819A is characterized for operation from 0°C to 70°C.
Function Tables
PORT A
SELECT INPUTS
A0–A17
PORT-A OPERATION
CLKA
CSA W/RA WENA
RENA
X
↑
H
L
L
X
H
L
X
H
X
X
X
H
High Z
High Z
Active
None
Write A0–A17 to FIFOA–B
Read FIFOB–A to A0–A17
↑
PORT B
SELECT INPUTS
B0–B17
PORT-B OPERATION
CLKB
CSB W/RB WENB
RENB
X
↑
H
L
L
X
H
L
X
H
X
X
X
H
High Z
High Z
Active
None
Write B0–B17 to FIFOB–A
Read FIFOA–B to B0–B17
↑
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
†
logic symbol
Φ
76
69
CLKA
Clock A
&
Clock B
&
CLKB
FIFO 512 × 18 × 2
SN74ABT7819A
65
66
80
79
CSA
CSB
OE1
OE2
W/RB
W/RA
&
&
&
&
Write
Enable
FIFOA–B
Write
Enable
FIFOB–A
77
75
68
70
WENA
RENA
WENB
RENB
Read
Enable
FIFOB–A
Read
Enable
FIFOA–B
1
2
64
63
Reset FIFOA–B
RSTA
PENA
Reset FIFOB–A
RSTB
PENB
Program Enable
Program Enable
FIFOA–B
FIFOB–A
5
60
IRA
Input-Ready
Port A
Input–Ready
IRB
Port B
74
4
71
61
62
ORA
HFA
Output-Ready
Port A
Half-Full
Output–Ready
ORB
Port B
Half–Full
FIFOB–A
HFB
FIFOA–B
3
AF/AEA
Almost-Full/Empty
FIFOA–B
Almost–Full/Empty
FIFOB–A
AF/AEB
7
58
57
55
54
52
51
49
48
46
A0
A1
A2
A3
A4
A5
A6
A7
A8
0
0
B0
B1
B2
B3
B4
B5
B6
B7
B8
8
10
11
13
14
16
17
19
1
2
20
22
23
25
26
28
29
31
45
43
42
40
39
37
36
34
Data
Data
A9
A10
A11
A12
A13
A14
A15
A16
B9
B10
B11
B12
B13
B14
B15
B16
32
33
A17
17
17
B17
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Terminal numbers are for the PH package.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
functional block diagram
PENA
RENA
Port-A
Control
Logic
WENA
CSA
W/RA
CLKA
RSTA
Read
Pointer
512 × 18
Dual-Port SRAM
18
Register
Register
FIFOB–A
18
18
Write
Pointer
Flag
IRB
ORA
Logic
FIFOB–A
AF/AEB
HFB
8
A0–A17
B0–B17
8
IRA
AF/AEA
HFA
Flag
Logic
FIFOA–B
ORB
Write
Pointer
512 × 18
Dual-Port SRAM
FIFOA–B
18
Register
Register
Read
Pointer
RSTB
CLKB
CSB
W/RB
WENB
RENB
Port-B
Control
Logic
PENB
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
enable logic diagram (positive logic)
CSA
W/RA
WENA
WEN FIFOA–B
A0–A17 (output enable)
REN FIFOB–A
RENA
CSB
W/RB
WENB
WEN FIFOB–A
B0–B17 (output enable)
REN FIFOA–B
RENB
Terminal Functions
†
TERMINAL
I/O
DESCRIPTION
NAME
NO.
7, 8, 10, 11,
13, 14, 16, 17,
19, 20, 22, 23,
25, 26, 28, 29,
31, 32
A0–A17
I/O
Port-A data. The 18-bit bidirectional data port for side A.
FIFOA–B almost-full/almost-empty flag. Depth offsets can be programmed for AF/AEA or the default
value of 128 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEA is
high when X or fewer words or (512 – Y) or more words are stored in FIFOA–B. AF/AEA is forced high
when FIFOA–B is reset.
AF/AEA
AF/AEB
3
O
O
FIFOB–A almost-full/almost-empty flag. Depth offsets can be programmed for AF/AEB or the default
value of 128 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEB is
high when X or fewer words or (512 – Y) or more words are stored in FIFOB–A. AF/AEB is forced high
when FIFOB–A is reset.
62
58, 57, 55, 54,
52, 51, 49, 48,
46, 45, 43, 42,
40, 39, 37, 36,
34, 33
B0–B17
I/O
Port-B data. The 18-bit bidirectional data port for side B.
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A to its
low-to-high transition and can be asynchronous or coincident to CLKB.
CLKA
CLKB
76
69
I
I
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B to its
low-to-high transition and can be asynchronous or coincident to CLKA.
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to either write data from
A0–A17 to FIFOA–B or read data from FIFOB–A to A0–A17. The A0–A17 outputs are in the
high-impedance state when CSA is high.
80
65
I
I
CSA
CSB
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to either write data from
B0–B17 to FIFOB–A or read data from FIFOA–B to B0–B17. The B0–B17 outputs are in the
high-impedance state when CSB is high.
†
Terminal numbers are for the PH package.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
Terminal Functions (Continued)
†
TERMINAL
I/O
DESCRIPTION
NAME
NO.
FIFOA–B half-full flag. HFA is high when FIFOA–B contains 256 or more words and is low when
FIFOA–B contains 255 or fewer words. HFA is set low after FIFOA–B is reset.
HFA
4
O
O
FIFOB–A half-full flag. HFB is high when FIFOB–A contains 256 or more words and is low when
FIFOB–A contains 255 or fewer words. HFB is set low after FIFOB–A is reset.
HFB
IRA
61
5
Port-A input-ready flag. IRA is synchronized to the low-to-high transition of CLKA. When IRA is low,
FIFOA–B is full and writes to its array are disabled. IRA is set low during a FIFOA–B reset and is set high
on the second low-to-high transition of CLKA after reset.
O
O
Port-B input-ready flag. IRB is synchronized to the low-to-high transition of CLKB. When IRB is low,
FIFOB–A is full and writes to its array are disabled. IRB is set low during a FIFOB–A reset and is set high
on the second low-to-high transition of CLKB after reset.
IRB
60
74
Port-A output-ready flag. ORA is synchronized to the low-to-high transition of CLKA. When ORA is low,
FIFOB–A is empty and reads from its array are disabled. The last valid word remains on the FIFOB–A
outputs when ORA is low. Ready data is present for the A0–A17 outputs when ORA is high. ORA is set
low during a FIFOB–A reset and goes high on the third low-to-high transition of CLKA after the first word
is loaded to an empty FIFOB–A.
ORA
O
O
Port-B output-ready flag. ORB is synchronized to the low-to-high transition of CLKB. When ORB is low,
FIFOA–B is empty and reads from its array are disabled. The last valid word remains on the FIFOA–B
outputs when ORB is low. Ready data is present for the B0–B17 outputs when ORB is high. ORB is set
low during a FIFOA–B reset and goes high on the third low-to-high transition of CLKB after the first word
is loaded to an empty FIFOA–B.
ORB
71
AF/AEAprogram enable. After FIFOA–B is reset and before a word is written to its array, thebinaryvalue
on A0–A7 is latched as an AF/AEA offset when PENA is low and CLKA is high.
2
I
I
I
I
I
I
I
I
PENA
PENB
RENA
RENB
AF/AEBprogram enable. After FIFOB–A is reset and before a word is written to its array, thebinaryvalue
on B0–B7 is latched as an AF/AEB offset when PENB is low and CLKB is high.
63
75
70
1
Port-A read enable. A high level on RENA enables data to be read from FIFOB–A on the low-to-high
transition of CLKA when CSA is low, W/RA is low, and ORA is high.
Port-B read enable. A high level on RENB enables data to be read from FIFOA–B on the low-to-high
transition of CLKB when CSB is low, W/RB is low, and ORB is high.
FIFOA–B reset. To reset FIFOA–B, four low-to-high transitions of CLKA and four low-to-high transitions
of CLKB must occur while RSTA is low. This sets HFA low, IRA low, ORB low, and AF/AEA high.
RSTA
RSTB
WENA
WENB
FIFOB–A reset. To reset FIFOB–A, four low-to-high transitions of CLKA and four low-to-high transitions
of CLKB must occur while RSTB is low. This sets HFB low, IRB low, ORA low, and AF/AEB high.
64
77
68
Port-A write enable. A high level on WENA enables data on A0–A17 to be written into FIFOA–B on the
low-to-high transition of CLKA when W/RA is high, CSA is low, and IRA is high.
Port-B write enable. A high level on WENB enables data on B0–B17 to be written into FIFOB–A on the
low-to-high transition of CLKB when W/RB is high, CSB is low, and IRB is high.
Port-Awrite/readselect. AhighonW/RAenablesA0–A17datatobewrittentoFIFOA–Bonalow-to-high
transition of CLKA when WENA is high, CSA is low, and IRA is high. A low on W/RA enables data to be
readfromFIFOB–Aonalow-to-hightransitionofCLKAwhenRENAishigh, CSAislow, andORAishigh.
The A0–A17 outputs are in the high-impedance state when W/RA is high.
79
66
I
I
W/RA
W/RB
Port-Bwrite/readselect. AhighonW/RBenablesB0–B17datatobewrittentoFIFOB–Aonalow-to-high
transition of CLKB when WENB is high, CSB is low, and IRB is high. A low on W/RB enables data to be
readfromFIFOA–Bonalow-to-hightransitionofCLKBwhenRENBishigh, CSBislow, andORBishigh.
The B0–B17 outputs are in the high-impedance state when W/RB is high.
†
Terminal numbers are for the PH package.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
CLKA
CLKB
RSTA
IRA
1
1
2
3
4
1
2
2
3
4
ORB
HFA
AF/AEA
NOTE: FIFOB–A is reset in the same manner.
Figure 1. Reset Cycle for FIFOA–B
CLKA
IRA
1
0
CSA
W/RA
WENA
†
†
†
†
Word 4
Word 1
Word 2
Word 3
A0–A17
†
Written to FIFOA–B
Figure 2. Write Timing – Port A
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
CLKB
1
0
IRB
CSB
W/RB
WENB
†
†
†
†
Word 4
Word 1
Word 2
Word 3
B0–B17
†
Written to FIFOB–A
Figure 3. Write Timing – Port B
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
CLKA
CSA
1
0
1
0
W/RA
WENA
t
su
A0–A17
CLKB
ORB
W1
1
2
3
t
t
pd
pd
CSB
W/RB
RENB
t
pd
B0–B17
W1 From FIFOA–B
NOTE: Operation of FIFOB–A is identical to that of FIFOA–B.
Figure 4. ORB-Flag Timing and First Data-Word Fall Through When FIFOA–B Is Empty
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
CLKB
CSB
1
0
1
0
W/RB
RENB
B0–B17
From FIFOA–B
CLKA
1
2
IRA
t
t
pd
pd
1
0
CSA
WENA
W/RA
1
0
To
FIFOA–B
A0–A17
NOTE: Operation of FIFOB–A is identical to that of FIFOA–B.
Figure 5. Write-Cycle and IRA-Flag Timing When FIFOA–B Is Full
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
CLKA
ORA
1
0
CSA
W/RA
RENA
t
t
t
pd
dis
en
†
†
†
†
Word 4
Word 1
Word 2
Word 3
A0–A17
†
Read from FIFOB–A
Figure 6. Read Timing – Port A
CLKB
ORB
1
0
CSB
W/RB
RENB
t
t
t
pd
dis
en
‡
‡
‡
‡
Word 4
Word 1
Word 2
Word 3
B0–B17
‡
Read from FIFOA–B
Figure 7. Read Timing – Port B
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLKA
WENA
IRA
W1
WX+1
WX+2
W256
W257
W512–Y
W513–Y
W513
A0–A17
CLKB
RENB
ORB
B0–B17
W1
W2
WY+1
WY+2
W257
W258
W512–X
W513–X
AF/AEA
HFA
NOTES: A. CSA, CSB = 0, W/RA = 1, W/RB = 0
B. X is the almost-empty offset and Y is the almost-full offset for AF/AEA.
C. HFB and AF/AEB function in the same manner for FIFOB–A.
Figure 8. FIFOA–B (HFA, AF/AEA) Asynchronous Flag Timing
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
offset values for AF/AE
TheAF/AEflagof eachFIFO hastwoprogrammablelimits: thealmost-emptyoffset value (X) and the almost-full
offset value (Y). They can be programmed from the input of the FIFO after it is reset and before a word is written
to its memory. An AF/AE flag is high when its FIFO contains X or fewer words or (512 – Y) or more words.
To program the offset values for AF/AEA, PENA is brought low after FIFOA–B is reset and only when CLKA is
low. On the following low-to-high transition of CLKA, the binary value on A0–A7 is stored as the almost-empty
offset value (X) and the almost-full offset value (Y). Holding PENA low for another low-to-high transition of CLKA
reprograms Y to the binary value on A0–A7 at the time of the second CLKA low-to-high transition.
During the first two CLKA cycles used for offset programming, PENA can be brought high only when CLKA is
low. PENA can be brought high at any time after the second CLKA pulse used for offset programming returns
low. A maximum value of 255 can be programmed for either X or Y (see Figure 9). To use the default values
ofX=Y=128, PENAmustbetiedhigh. NodataisstoredinFIFOA–BwhiletheAF/AEAoffsetsareprogrammed.
The AF/AEB flag is programmed in the same manner, with PENB enabling CLKB to program the offset values
taken from B0–B7.Figure 8
RESET
CLKA
3
4
IRA
PENA
CSA
W/RA
WENA
A0–A7
X and Y
Y
Figure 9. Programming X and Y Separately for AF/AEA
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
I
CC
Voltage range applied to any output in the high state or power-off state, V
. . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Package thermal impedance, θ (see Note 2): PH package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72°C/W
JA
PN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51–7.
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
V
IL
0
V
V
I
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–12
24
5
mA
mA
ns/V
°C
OH
OL
∆t/∆v
T
0
70
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
–1.2
V
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
I
I
I
I
= –3 mA
= –3 mA
= –12 mA
= 24 mA
2.5
3
OH
OH
OH
OL
V
OH
OL
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
2
0.5
V
I
I
I
I
V = V or GND
I CC
±1
50
µA
µA
µA
mA
I
§
V
O
V
O
V
O
= 2.7 V
= 0.5 V
= 2.5 V
OZH
§
–50
–180
15
OZL
¶
–40
–100
O
Outputs high
Outputs low
V
= 5.5 V, I = 0,
O
CC
I
95
mA
CC
V = V
or GND
I
CC
Outputs disabled
15
C
C
Control inputs
A or B ports
V = 2.5 V or 0.5 V
12
14
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
io
‡
§
¶
All typical values are at V
= 5 V, T = 25°C.
A
OZL
CC
and I
The parameters I
include the input leakage current.
OZH
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 10)
’7819A-10
MIN MAX
100
’7819A-12
MIN MAX
80
’7819A-15
MIN MAX
67
’7819A-20
MIN MAX
50
’7819A-30
MIN MAX
33.3
UNIT
f
t
Clock frequency
Pulse
MHz
ns
clock
CLKA, CLKB high or low
4.5
2
6
6
4
5
3
3
0
0
0
0
0
2
3
4.5
3
6
6
4
5
3
3
0
0
0
0
0
2
3
6
4
6
6
4
5
4
4
0
0
0
0
0
2
3
8
5
7
7
5
5
5
5
0
0
0
0
0
2
4
11
5
7
7
5
6
5
5
0
0
0
0
0
2
4
w
duration
A0–A17 before CLKA↑ and
B0–B17 before CLKB↑
CSA before CLKA↑ and
CSB before CLKB↑
W/RA before CLKA↑ and
W/RB before CLKB↑
Setup
time
WENA before CLKA↑ and
WENB before CLKB↑
t
su
ns
RENA before CLKA↑ and
RENB before CLKB↑
PENA before CLKA↑ and
PENB before CLKB↑
RSTA or RSTB low before
†
first CLKA↑ and CLKB↑
A0–A17 after CLKA↑ and
B0–B17 after CLKB↑
CSA after CLKA↑ and
CSB after CLKB↑
W/RA after CLKA↑ and
W/RB after CLKB↑
Hold
time
WENA after CLKA↑ and
WENB after CLKB↑
t
h
ns
RENA after CLKA↑ and
RENB after CLKB↑
PENA after CLKA low and
PENB after CLKB low
RSTA or RSTB low after
fourth CLKA↑ and CLKB↑
†
†
To permit the clock pulse to be utilized for reset purposes
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 10)
L
’7819A-10
’7819A-12
’7819A-15
’7819A-20
’7819A-30
FROM
(INPUT) (OUTPUT)
TO
PARAMETER
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
CLKA
or
CLKB
f
100
80
67
50
33.3
MHz
max
CLKA↑
CLKB↑
CLKA↑
CLKB↑
CLKA↑
CLKB↑
CLKA↑
CLKB↑
CLKA↑
CLKB↑
RSTA
CLKA↑
CLKB↑
RSTB
CLKA↑
CLKB↑
RSTA
CLKA↑
CLKB↑
RSTB
CSA
A0–A17
B0–B17
A0–A17
B0–B17
IRA
3
3
6
6
5
5
8
8
4
4
9
9
4
4
10
10
4
4
12
12
4
4
14
14
t
t
ns
ns
pd
‡
pd
4
4
9
9
4
4
9
9
4
4
10
10
10
10
17
17
14
17
17
14
17
17
14
17
17
14
9
4
4
12
12
12
12
18
18
15
18
18
15
18
18
15
18
18
15
10
10
10
10
10
10
10
10
4
4
14
14
14
14
20
20
16
20
20
16
20
20
16
20
20
16
11
11
11
11
11
11
11
11
IRB
ORA
3.5
3.5
8
9
3.5
3.5
8
9
3.5
3.5
8
3.5
3.5
8
3.5
3.5
8
t
pd
ns
ORB
9
9
17
17
12
17
17
12
17
17
12
17
17
12
8
17
17
12
17
17
12
17
17
12
17
17
12
8
AF/AEA
AF/AEA
AF/AEB
8
8
8
8
8
t
t
4
4
4
4
4
ns
ns
PLH
8
8
8
8
8
pd
8
8
8
8
8
AF/AEB
HFA
4
4
4
4
4
t
t
PLH
8
8
8
8
8
8
8
8
8
8
ns
HFA
HFB
HFB
4
4
4
4
4
PHL
8
8
8
8
8
t
t
8
8
8
8
8
PLH
ns
ns
4
4
4
4
4
PHL
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
A0–A17
B0–B17
A0–A17
B0–B17
W/RA
CSB
8
8
9
t
en
8
8
9
W/RB
CSA
8
8
9
8
8
9
W/RA
CSB
8
8
9
t
ns
dis
8
8
9
W/RB
8
8
9
†
‡
All typical values are at V
CC
= 5 V, T = 25°C.
A
This parameter is measured with a 30-pF load (see Figure 11).
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
PARAMETER MEASUREMENT INFORMATION
7 V
PARAMETER
S1
S1
t
Open
Closed
Open
Closed
Open
Open
PZH
t
t
t
en
dis
pd
t
500 Ω
PZL
t
PHZ
From Output
Under Test
Test
Point
t
PLZ
PLH
PHL
t
t
C
= 50 pF
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
1.5 V
3 V
0 V
Input
1.5 V
1.5 V
3 V
0 V
Timing
Input
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
3 V
0 V
Data
Input
3 V
0 V
1.5 V
1.5 V
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
≈3.5 V
Output
Waveform 1
S1 at 7 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OL
OH
t
t
t
t
PLH
PHL
PZH
PHZ
V
Output
Waveform 2
S1 at Open
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
≈0 V
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTE A: C includes probe and jig capacitance.
L
Figure 10. Load Circuit and Voltage Waveforms
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7819A
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
V
= 5 V
= 25°C
= 500 Ω
CC
T
A
typ + 6
typ + 4
R
L
typ + 2
typ
typ – 2
0
50
100
150
200
250
300
C
– Load Capacitance – pF
L
Figure 11
SUPPLY CURRENT
vs
CLOCK FREQUENCY
160
140
T
C
= 75°C
= 0 pF
A
L
V
CC
= 5.5 V
120
100
80
V
CC
= 5 V
V
CC
= 4.5 V
60
40
20
10 15 20 25 30 35 40 45 50 55 60 65 70
f
– Clock Frequency – MHz
clock
Figure 12
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74ABT7819A-10PH
SN74ABT7819A-10PN
SN74ABT7819A-12PH
SN74ABT7819A-12PN
SN74ABT7819A-15PH
SN74ABT7819A-15PN
SN74ABT7819A-20PH
SN74ABT7819A-20PN
SN74ABT7819A-30PH
SN74ABT7819A-30PN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
QFP
PH
80
80
80
80
80
80
80
80
80
80
66
119
66
None
None
None
None
None
None
None
None
None
None
A42
CU NIPDAU Level-3-220C-168 HR
A42 Level-3-220C-168 HR
CU NIPDAU Level-3-220C-168 HR
A42 Level-3-220C-168 HR
CU NIPDAU Level-3-220C-168 HR
A42 Level-3-220C-168 HR
CU NIPDAU Level-3-220C-168 HR
A42 Level-3-220C-168 HR
CU NIPDAU Level-3-220C-168 HR
Level-3-220C-168 HR
LQFP
QFP
PN
PH
LQFP
QFP
PN
119
66
PH
LQFP
QFP
PN
119
66
PH
LQFP
QFP
PN
119
66
PH
LQFP
PN
119
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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