SN74ABT7820-15PH [TI]
512 x 18 x 2 bidirectional asynchronous FIFO memory 80-QFP 0 to 70;
| 型号： | SN74ABT7820-15PH |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 512 x 18 x 2 bidirectional asynchronous FIFO memory 80-QFP 0 to 70 时钟 先进先出芯片 信息通信管理 内存集成电路 |
| 文件： | 总15页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
Member of the Texas Instruments
Widebus Family
Empty, Full, and Half-Full Flags
Fast Access Times of 12 ns With a 50-pF
Load and Simultaneous Switching Data
Outputs
Advanced BiCMOS Technology
Independent Asynchronous Inputs and
Outputs
Supports Clock Rates up to 67 MHz
Two Separate 512 × 18 FIFOs Buffering
Data in Opposite Directions
Package Options Include 80-Pin Quad Flat
(PH) and 80-Pin Thin Quad Flat (PN)
Packages
Programmable Almost-Full/Almost-Empty
Flags
PH PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
2
3
4
5
6
7
64
63
RSTA
PENA
AF/AEA
HFA
FULLA
GND
RSTB
PENB
AF/AEB
HFB
FULLB
GND
B0
62
61
60
59
58
57
56
55
54
53
A0
A1
8
9
B1
V
V
B2
CC
A2
CC
10
11
12
13
14
15
A3
GND
A4
A5
GND
A6
A7
GND
A8
B3
GND
B4
B5
GND
B6
B7
GND
B8
52
51
50
49
48
47
16
17
18
19
20
21
22
23
24
46
45
44
A9
B9
V
V
CC
CC
43
42
41
A10
A11
B10
B11
GND
GND
25 26 27 28 29 30 3132 33 34 35 36 37 38 39 40
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
PN PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AF/AEA
HFA
AF/AEB
HFB
1
2
3
4
60
59
58
57
FULLA
GND
A0
FULLB
GND
5
6
56 B0
A1
B1
55
54
53
7
8
9
V
V
CC
B2
CC
A2
A3
B3
52
51
50
GND
A4
GND
B4
10
11
49
48
47
46
A5
B5
12
13
14
15
16
17
18
19
GND
A6
GND
B6
A7
B7
45
44
GND
A8
GND
B8
43
42
41
A9
B9
V
V
CC
B10
CC
A10
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ABT7820 is arranged as two 512 × 18-bit FIFOs for high speed and fast access times. It
processes data at rates up to 67 MHz with access times of 12 ns in a bit-parallel format.
The SN74ABT7820 consists of bus-transceiver circuits, two 512 × 18 FIFOs, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable inputs
(GAB and GBA) control the transceiver functions. The SAB and SBA control inputs select whether real-time or
stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the eight
fundamental bus-management functions that can be performed with the SN74ABT7820.
The SN74ABT7820 is characterized for operation from 0°C to 70°C.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
FIFO A
FIFO A
Out
In
Out
In
Bus A
Bus B
Bus B
Bus B
Bus A
Bus A
Bus A
Bus A
Bus B
FIFO B
Out
FIFO B
Out
In
In
SAB SBA GAB GBA
SAB SBA GAB GBA
L
X
H
L
X
X
L
L
FIFO A
FIFO A
In
Out
In
Out
Bus A
Bus B
FIFO B
Out
FIFO B
Out
In
In
SAB SBA GAB GBA
SAB SBA GAB GBA
X
L
L
H
H
L
H
H
FIFO A
FIFO A
Out
In
Out
In
Bus A
Bus B
FIFO B
Out
FIFO B
Out
In
In
SAB SBA GAB GBA
SAB SBA GAB GBA
H
X
H
L
L
H
H
H
FIFO A
FIFO A
In Out
In
Out
Bus B
Bus A
Bus B
FIFO B
Out
FIFO B
Out
In
In
SAB SBA GAB GBA
SAB SBA GAB GBA
X
H
L
H
H
H
H
H
Figure 1. Bus-Management Functions
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
SELECT-MODE CONTROL TABLE
CONTROL
OPERATION
SBA
L
SAB
L
A BUS
B BUS
Real-time B-to-A bus
FIFO B-to-A bus
Real-time A-to-B bus
Real-time A-to-B bus
FIFO A-to-B bus
FIFO A-to-B bus
H
L
L
H
Real-time B-to-A bus
FIFO B-to-A bus
H
H
OUTPUT-ENABLE CONTROL TABLE
OPERATION
CONTROL
GBA
GAB
A BUS
B BUS
L
H
L
L
L
Isolation/input to A bus
A bus enabled
Isolation/input to B bus
Isolation/input to B bus
B bus enabled
H
H
Isolation/input to A bus
A bus enabled
H
B bus enabled
Figure 1. Bus-Management Functions (Continued)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
†
logic symbol
Φ
FIFO
512 × 18 × 2
SN74ABT7820
66
79
SAB
SBA
1
0
MODE
65
80
GAB
GBA
EN1
EN2
1
64
63
68
RSTA
RESET A
RESET B
PROG ENB
LDCKB
RSTB
2
PENA
PROG ENA
PENB
LDCKB
77
LDCKA
UNCKA
FULLA
EMPTYA
AF/AEA
LDCKA
69
5
76
60
75
62
UNCKB
UNCKA
FULLA
UNCKB
FULLB
FULLB
EMPTYB
AF/AEB
70
3
EMPTYA
EMPTYB
ALMOST FULL/
ALMOST EMPTY A
ALMOST FULL/
ALMOST EMPTY B
4
61
HFA
HALF-FULL A
HALF-FULL B
HFB
7
58
57
55
54
52
51
A0
A1
0
0
B0
B1
B2
B3
B4
8
10
11
13
14
A2
A3
A4
A5
B5
16
17
19
20
22
23
25
26
28
29
31
32
49
48
46
A6
B6
B7
B8
B9
B10
A7
A8
45
43
42
40
A Data
B Data
A9
A10
A11
A12
A13
A14
A15
A16
A17
B11
B12
B13
B14
39
37
36
34
33
B15
B16
B17
17
17
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the PH package.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
logic diagram (positive logic)
SAB
SBA
Φ
FIFO B
512 × 18
RSTB
HFB
AF/AEB
PENB
EMPTYB
UNCKB
FULLB
LDCKB
[1]
[2]
[3]
[4]
B0
Q
D
GBA
1 of 18 Channels
[15]
[16]
[17]
[18]
To Other Channels
GAB
Φ
FIFO A
512 × 18
RSTA
PENA
HFA
AF/AEA
EMPTYA
UNCKA
FULLA
LDCKA
[1]
[2]
[3]
[4]
Q
A0
D
1 of 18 Channels
[15]
[16]
[17]
[18]
To Other Channels
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
Terminal Functions
TERMINAL
I/O
DESCRIPTION
A0–A17
I/O
Port-A data. The 18-bit bidirectional data port for side A.
FIFO A almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AEA or the default value of 128 can
be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEA is high when FIFO A contains X or
fewer words or (512 – Y) or more words. AF/AEA is set high after FIFO A is reset.
AF/AEA
AF/AEB
O
O
FIFO B almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AEB or the default value of 128 can
be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEB is high when FIFO B contains
X or fewer words or (512 – Y) or more words. AF/AEB is set high after FIFO B is reset.
B0–B17
EMPTYA
I/O
O
Port-B data. The 18-bit bidirectional data port for side B.
FIFO A empty flag. EMPTYA is low when FIFO A is empty and high when FIFO A is not empty. EMPTYA is set low after
FIFO A is reset.
FIFO B empty flag. EMPTYB is low when FIFO B is empty and high when FIFO B is not empty. EMPTYB is set low after
FIFO B is reset.
EMPTYB
O
FULLA
FULLB
GAB
O
O
I
FIFO A full flag. FULLA is low when FIFO A is full and high when FIFO A is not full. FULLA is set high after FIFO A is reset.
FIFO B full flag. FULLB is low when FIFO B is full and high when FIFO B is not full. FULLB is set high after FIFO B is reset.
Port-B output enable. B0–B17 outputs are active when GAB is high and in the high-impedance state when GAB is low.
Port-A output enable. A0–A17 outputs are active when GBA is high and in the high-impedance state when GBA is low.
GBA
I
FIFO A half-full flag. HFA is high when FIFO A contains 256 or more words and is low when FIFO A contains 255 or fewer
words. HFA is set low after FIFO A is reset.
HFA
O
O
I
FIFO B half-full flag. HFB is high when FIFO B contains 256 or more words and is low when FIFO B contains 255 or fewer
words. HFB is set low after FIFO B is reset.
HFB
FIFO A load clock. Data is written into FIFO A on a low-to-high transition of LDCKA when FULLA is high. The first word
written into an empty FIFO A is sent directly to the FIFO A data outputs.
LDCKA
LDCKB
PENA
PENB
FIFO B load clock. Data is written into FIFO B on a low-to-high transition of LDCKB when FULLB is high. The first word
written into an empty FIFO B is sent directly to the FIFO B data outputs.
I
FIFO A program enable. After reset and before a word is written into FIFO A, the binary value on A0–A7 is latched as
an AF/AEA offset value when PENA is low and LDCKA is high.
I
FIFO B program enable. After reset and before a word is written into FIFO B, the binary value on B0–B7 is latched as
an AF/AEB offset value when PENB is low and LDCKB is high.
I
RSTA
RSTB
I
I
FIFO A reset. A low level on RSTA resets FIFO A forcing EMPTYA low, HFA low, FULLA high, and AF/AEA high.
FIFO B reset. A low level on RSTB resets FIFO B forcing EMPTYB low, HFB low, FULLB high, and AF/AEB high.
Port-B read select. SAB selects the source of B0–B17 read data. A low level selects real-time data from A0–A17. A high
level selects the FIFO A output.
SAB
SBA
I
I
Port-A read select. SBA selects the source of A0–A17 read data. A low level selects real-time data from B0 – B17. A high
level selects the FIFO B output.
UNCKA
UNCKB
I
I
FIFO A unload clock. Data is read from FIFO A on a low-to-high transition of UNCKA when EMPTYA is high.
FIFO B unload clock. Data is read from FIFO B on a low-to-high transition of UNCKB when EMPTYB is high.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RSTA
1
0
PENA
LDCKA
Word
1
Word
129
Word
256
Word
384
Word
512
Word
2
Don’t Care
A0 – A17
UNCKA
Word
2
Word
129
Word
130
Word
257
Word
258
Word
384
Word
385
Word
512
Word 1
Invalid
Q0 – Q17
EMPTYA
FULLA
HFA
AF/AEA
Set X = Y = 128
Empty + X Half-Full Full – Y
Full
Full – Y
Half-Full
Empty + X
Empty
†
SAB = GAB = H, GBA = L
Operation of FIFO B is identical to that of FIFO A.
†
Figure 2. Timing Diagram for FIFO A
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
offset values for AF/AEFigure 2
The AF/AE flag of each FIFO has two programmable limits: the almost-empty offset value (X) and the almost-full
offset value (Y). The offsets of a flag can be programmed from the input of its FIFO after it is reset and before
any data is written to its memory. An AF/AE flag is high when its FIFO contains X or fewer words or (512 – Y)
or more words.
To program the offset values for AF/AEA, program enable (PENA) can be brought low after FIFO A is reset and
only when LDCKA is low. On the following low-to-high transition of LDCKA, the binary value on A0–A7 is stored
as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PENA low for another
low-to-high transition of LDCKA reprograms Y to the binary value on A0–A7 at the time of the second LDCKA
low-to-high transition.
PENA can be brought back high only when LDCKA is low during the first two LDCKA cycles. PENA can be
brought high at any time after the second LDCKA pulse returns low. A maximum value of 255 can be
programmed for either X or Y (see Figure 3). To use the default values of X = Y = 128 for AF/AEA, PENA must
be tied high. No data is stored in the FIFO when its AF/AE offsets are programmed. The AF/AEB flag is
programmed in the same manner. PENB enables LDCKB to program the AF/AEB offset values taken from
B0–B7.
RSTA
LDCKA
1
2
PENA
X and Y
Y
Word 1
A0–A17
EMPTYA
Figure 3. Programming X and Y Separately for AF/AEA
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
I
CC
Voltage range applied to any output in the high state or power-off state, V
. . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Package thermal impedance, θ (see Note 2): PH package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
JA
PN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
V
IL
0
0
V
V
I
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–12
24
5
mA
mA
ns/V
°C
OH
OL
∆t/∆v
T
A
70
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = – 18 mA
–1.2
V
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
I
I
I
I
= – 3 mA
= – 3 mA
= – 12 mA
= 24 mA
2.5
3
OH
OH
OH
OL
V
OH
OL
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
2
0.55
±5
V
I
I
I
I
V = V or GND
I CC
µA
µA
µA
mA
I
‡
V
O
V
O
V
O
= 2.7 V
= 0.5 V
= 2.5 V
50
OZH
‡
–50
–180
15
OZL
§
–40
–100
O
Outputs high
or GND Outputs low
Outputs disabled
I
V
CC
= 5.5 V,
I
O
= 0,
V = V
I CC
95
mA
CC
15
C
Control inputs V = 2.5 V or 0.5 V
6
pF
i
I
C
C
Flags
V
= 2.5 V or 0.5 V
= 2.5 V or 0.5 V
4
8
pF
pF
o
O
O
A or B ports
V
io
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
OZL
CC
The parameters I
and I
include the input leakage current.
OZH
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 4)
’ABT7820-15
’ABT7820-20
’ABT7820-25
’ABT7820-30
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
Clock frequency
LDCKA, LDCKB high
67
50
40
33
MHz
clock
w
4
4
4
4
6
6
6
6
6
8
9
9
11
11
11
11
12
LDCKA, LDCKB low
UNCKA, UNCKB high
UNCKA, UNCKB low
RSTA, RSTB low
Pulse
duration
t
9
ns
ns
ns
9
10
A0–A17 before LDCKA↑ and
B0–B17 before LDCKB↑
3
5
3
0
2
3
4
5
3
0
2
3
4
5
4
0
2
4
4
5
4
0
2
4
PENA before LDCKA↑ and
PENB before LDCKB↑
t
su
Setup time
LDCKA inactive before RSTA high
and LDCKB inactive before RSTB high
A0–A17 after LDCKA↑ and
B0–B17 after LDCKB↑
PENA after LDCKA low and
PENB after LDCKB low
t
h
Hold time
LDCKA inactive after RSTA high and
LDCKB inactive after RSTB high
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 5)
L
’ACT7820-15
’ACT7820-20
’ACT7820-25
’ACT7820-30
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
LDCK, UNCK
67
50
40
33.3
MHz
max
pd
LDCKA↑,
LDCKB↑
4
14
12
4
4
15
4
4
18
15
4
4
20
17
t
B/A
B/A
ns
ns
UNCKA↑,
UNCKB↑
4
4
9
8
13.5
UNCKA↑,
UNCKB↑
‡
t
t
pd
LDCKA↑,
LDCKB↑
14
4
15
4
17
4
19
PLH
EMPTYA,
EMPTYB
ns
UNCKA↑,
UNCKB↑
t
t
t
4
6
6
6
8
8
8
2
13
16
13
15
20
16
16
12
4
6
6
6
8
8
8
2
14
16
14
15
20
17
17
14
4
6
6
6
8
8
8
2
16
18
16
17
22
18
18
16
4
6
6
6
8
8
8
2
18
20
18
19
22
20
20
18
PHL
PHL
PHL
RSTA low,
RSTB low
EMPTYA,
EMPTYB
ns
ns
LDCKA↑,
LDCKB↑
FULLA,
FULLB
UNCKA↑,
UNCKB↑
FULLA,
FULLB
t
ns
ns
PLH
pd
RSTA low,
RSTB low
LDCKA↑,
LDCKB↑
AF/AEA,
AF/AEB
t
UNCKA↑,
UNCKB↑
RSTA low,
RSTB low
AF/AEA,
AF/AEB
t
t
ns
ns
PLH
LDCKA↑,
LDCKB↑
HFA, HFB
HFA, HFB
B/A
8
8
2
15
15
12
8
8
2
15
15
14
8
8
2
17
17
16
8
8
2
19
19
18
PLH
UNCKA, UNCKB
t
ns
RSTA low,
RSTB low
PHL
pd
§
SAB/SBA
2
2
2
2
10
9
2
2
2
2
11
10
8
2
2
2
2
12
11
10
13
2
2
2
2
14
13
12
14
t
ns
A/B
t
t
GBA/GAB
GBA/GAB
A/B
A/B
6.5
11
ns
ns
en
12
dis
†
‡
§
All typical values are at 5 V, T = 25°C.
This parameter is measured with a 30-pF load (see Figure 5).
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
A
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
7 V
PARAMETER
S1
S1
t
Open
Closed
Open
PZH
t
t
t
en
dis
pd
t
500 Ω
PZL
t
PHZ
From Output
Under Test
Test
Point
t
Closed
Open
PLZ
PLH
PHL
t
t
C
= 50 pF
Open
500 Ω
L
(see Note A)
LOAD CIRCUIT
t
w
3 V
0 V
Input
1.5 V
1.5 V
3 V
0 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
3 V
0 V
Data
Input
3 V
0 V
1.5 V
1.5 V
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
≈ 3.5 V
Output
Waveform 1
S1 at 7 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OH
t
PHZ
t
PLH
t
PZH
t
PHL
V
Output
Waveform 2
S1 at Open
V
OH
V
OH
1.5 V
Output
1.5 V
1.5 V
≈ 0 V
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTE A: C includes probe and jig capacitance.
L
Figure 4. Load Circuit and Voltage Waveforms
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
V
= 5 V
= 25°C
= 500 Ω
CC
T
A
typ + 6
typ + 4
R
L
typ + 2
typ
typ – 2
0
50
100
150
200
250
300
C
– Load Capacitance – pF
L
Figure 5
SUPPLY CURRENT
vs
CLOCK FREQUENCY
160
140
T
C
= 75°C
= 0 pF
A
L
V
CC
= 5.5 V
120
100
80
V
CC
= 5 V
V
CC
= 4.5 V
60
40
20
10 15 20 25 30 35 40 45 50 55 60 65 70
f
– Clock Frequency – MHz
clock
Figure 6
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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