SN74ABT8646DLR [TI]
SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND RESISTERS; 八进制总线收发器和电阻扫描测试设备
| 型号： | SN74ABT8646DLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND RESISTERS |
| 文件： | 总32页 (文件大小：537K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢃ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢈ
ꢀꢋ ꢄꢁ ꢆ ꢌꢀꢆ ꢍꢌꢎ ꢏ ꢋꢌ ꢀ ꢐꢏ ꢆꢑ
ꢒ ꢋꢆꢄꢓ ꢅꢔꢀ ꢆ ꢕꢄꢁꢀ ꢋꢌꢏ ꢎꢌꢕꢀ ꢄꢁꢍ ꢕꢌ ꢖ ꢏꢀ ꢆꢌ ꢕ ꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
SN54ABT8646 . . . JT PACKAGE
SN74ABT8646 . . . DL OR DW PACKAGE
(TOP VIEW)
D
D
Members of the Texas Instruments
SCOPE Family of Testability Products
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLKAB
SAB
DIR
A1
A2
A3
GND
A4
A5
CLKBA
SBA
OE
2
3
D
D
Functionally Equivalent to ’F646 and
’ABT646 in the Normal-Function Mode
4
B1
B2
B3
B4
5
SCOPE Instruction Set
6
− IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, CLAMP,
and HIGHZ
7
8
V
CC
9
B5
B6
B7
B8
TDI
TCK
− Parallel-Signature Analysis at Inputs
With Masking Option
− Pseudorandom Pattern Generation From
Outputs
− Sample Inputs/Toggle Outputs
− Binary Count From Outputs
− Even-Parity Opcodes
10
11
12
13
14
A6
A7
A8
TDO
TMS
D
D
D
Two Boundary-Scan Cells Per I/O for
Greater Flexibility
SN54ABT8646 . . . FK PACKAGE
(TOP VIEW)
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DL) Packages, Ceramic Chip
Carriers (FK), and Standard Ceramic DIPs
(JT)
4
3
2 1 28 27 26
5
25
24
23
22
21
20
19
B7
B8
OE
SBA
CLKBA
CLKAB
SAB
6
7
TDI
TCK
TMS
TDO
A8
8
9
10
11
description
DIR
A1
The ’ABT8646 and scan-test devices with octal
bus transceivers and registers are members of the
Texas Instruments SCOPE testability
12 13 14 15 16 17 18
integrated-circuit family. This family of devices
supports IEEE Standard 1149.1-1990 boundary
scan to facilitate testing of complex circuit-board
assemblies. Scan access to the test circuitry is
accomplished via the 4-wire test access port
(TAP) interface.
In the normal mode, these devices are functionally equivalent to the ’F646 and ’ABT646 octal bus transceivers
and registers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing
at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in normal mode does
not affect the functional operation of the SCOPE octal bus transceivers and registers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and EPIC-ΙΙB are trademarks of Texas Instruments.
ꢗ
ꢗ
ꢕ
ꢒ
ꢧ
ꢍ
ꢢ
ꢞ
ꢔ
ꢋ
ꢠ
ꢆ
ꢡ
ꢫ
ꢏ
ꢛ
ꢒ
ꢙ
ꢜ
ꢁ
ꢚ
ꢍ
ꢄ
ꢆ
ꢄ
ꢘ
ꢙ
ꢣ
ꢢ
ꢚ
ꢛ
ꢡ
ꢡ
ꢜ
ꢝ
ꢞ
ꢞ
ꢙ
ꢟ
ꢟ
ꢘ
ꢘ
ꢤ
ꢛ
ꢛ
ꢜ
ꢙ
ꢙ
ꢛ
ꢘ
ꢠ
ꢠ
ꢤ
ꢠ
ꢡ
ꢢ
ꢜ
ꢜ
ꢣ
ꢣ
ꢙ
ꢟ
ꢞ
ꢝ
ꢠ
ꢠ
ꢠ
ꢙ
ꢛ
ꢚ
ꢤ
ꢢ
ꢥ
ꢠ
ꢠ
ꢦ
ꢘ
ꢡ
ꢞ
ꢠ
ꢟ
ꢘ
ꢟ
ꢬ
ꢛ
ꢜ
ꢙ
ꢢ
ꢧ
ꢞ
ꢙ
ꢧ
ꢟ
ꢟ
ꢣ
ꢠ
ꢣ
ꢨ
Copyright 2004, Texas Instruments Incorporated
ꢒ ꢙ ꢤ ꢜ ꢛꢧ ꢢꢡ ꢟꢠ ꢡꢛ ꢝꢤ ꢦꢘ ꢞꢙ ꢟ ꢟꢛ ꢮꢏ ꢓꢯ ꢗꢕ ꢰ ꢯꢱꢇꢂ ꢱꢂꢉ ꢞꢦꢦ ꢤꢞ ꢜ ꢞ ꢝꢣ ꢟꢣꢜ ꢠ ꢞ ꢜ ꢣ ꢟꢣ ꢠꢟꢣ ꢧ
ꢜ
ꢛ
ꢡ
ꢟ
ꢛ
ꢜ
ꢝ
ꢟ
ꢛ
ꢠ
ꢤ
ꢘ
ꢚ
ꢘ
ꢡ
ꢣ
ꢜ
ꢟ
ꢩ
ꢟ
ꢣ
ꢜ
ꢛ
ꢚ
ꢆ
ꢣ
ꢪ
ꢞ
ꢏ
ꢙ
ꢝ
ꢣ
ꢠ
ꢟ
ꢞ
ꢙ
ꢧ
ꢜꢧ
ꢞ
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ
ꢜ
ꢞ
ꢙ
ꢟ
ꢬ
ꢨ
ꢗ
ꢜ
ꢛ
ꢧ
ꢟ
ꢘ
ꢛ
ꢡ
ꢣ
ꢠ
ꢘ
ꢙ
ꢭ
ꢧ
ꢛ
ꢣ
ꢛ
ꢟ
ꢙ
ꢣ
ꢡ
ꢣ
ꢠ
ꢞ
ꢜ
ꢘ
ꢦ
ꢘ
ꢙ
ꢡ
ꢦ
ꢢ
ꢢ ꢙꢦ ꢣꢠꢠ ꢛ ꢟꢩꢣ ꢜ ꢫꢘ ꢠꢣ ꢙ ꢛꢟꢣ ꢧꢨ ꢒ ꢙ ꢞꢦ ꢦ ꢛ ꢟꢩꢣ ꢜ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢠ ꢉ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛ ꢙ
ꢟ
ꢤ
ꢜ
ꢛ
ꢡ
ꢣ
ꢠ
ꢠ
ꢘ
ꢙ
ꢭ
ꢧ
ꢛꢣ
ꢠ
ꢙ
ꢛ
ꢟ
ꢙ
ꢣ
ꢡ
ꢣ
ꢠ
ꢠ
ꢞ
ꢜ
ꢘ
ꢦ
ꢬ
ꢘ
ꢙ
ꢡ
ꢦ
ꢢ
ꢧ
ꢣ
ꢟ
ꢣ
ꢠ
ꢘ
ꢙ
ꢭ
ꢛ
ꢚ
ꢞ
ꢦ
ꢦ
ꢤ
ꢞ
ꢜ
ꢞ
ꢝ
ꢣ
ꢟ
ꢣ
ꢜ
ꢠ
ꢨ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢃ ꢈ
ꢀ ꢋꢄ ꢁ ꢆ ꢌꢀ ꢆ ꢍ ꢌ ꢎꢏ ꢋ ꢌꢀ ꢐ ꢏ ꢆꢑ
ꢒꢋ ꢆꢄ ꢓ ꢅ ꢔꢀ ꢆ ꢕꢄ ꢁꢀ ꢋꢌ ꢏ ꢎꢌ ꢕꢀ ꢄꢁ ꢍ ꢕꢌ ꢖꢏ ꢀꢆ ꢌꢕꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
description (continued)
Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the
transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR
is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating both
buses.
Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is
clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data
is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for
presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB
and SAB, respectively. Figure 1 shows the four fundamental bus-management functions that can be performed
with the ’ABT8646.
In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.
Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO),
test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions
such as parallel-signature analysis (PSA) on data inputs and pseudorandom pattern generation (PRPG) from
data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54ABT8646 is characterized for operation over the full military temperature range of −55°C to 125°C.
The SN74ABT8646 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OE
X
X
H
H
L
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1−A8
Input
B1−B8
†
†
↑
X
Unspecified
Store A, B unspecified
†
†
X
X
↑
X
X
Unspecified
Input
Store B, A unspecified
X
↑
H or L
X
↑
H or L
X
X
X
Input
Input
Store A and B data
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
X
X
X
Input disabled
Output
Input disabled
Input
L
X
L
L
L
X
H or L
X
X
H
Output
Input disabled
Output
L
H
H
X
L
X
Input
L
H or L
X
H
X
Input disabled
Output
†
The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at
the bus pins is stored on every low-to-high transition of the clock inputs.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢃ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢈ
ꢀꢋ ꢄꢁ ꢆ ꢌꢀꢆ ꢍꢌꢎ ꢏ ꢋꢌ ꢀ ꢐꢏ ꢆꢑ
ꢒ ꢋꢆꢄꢓ ꢅꢔꢀ ꢆ ꢕꢄꢁꢀ ꢋꢌꢏ ꢎꢌꢕꢀ ꢄꢁꢍ ꢕꢌ ꢖ ꢏꢀ ꢆꢌ ꢕ ꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
26
OE
L
3
1
28
2
27
SBA
L
26
3
DIR
H
1
28
2
27
SBA
X
DIR CLKAB CLKBA SAB
CLKAB CLKBA SAB
OE
L
L
X
X
X
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
26
3
1
28
2
27
26
OE
L
3
1
28
2
27
SBA
H
DIR CLKAB CLKBA SAB
SBA
X
DIR
L
CLKAB CLKBA SAB
OE
X
X
X
X
X
↑
↑
X
X
X
↑
X
X
H or L
X
X
H
X
H
X
X
L
H
H or L
X
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Pin numbers shown are for the DL, DW, and JT packages.
Figure 1. Bus-Management Functions
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢃ ꢈ
ꢀ ꢋꢄ ꢁ ꢆ ꢌꢀ ꢆ ꢍ ꢌ ꢎꢏ ꢋ ꢌꢀ ꢐ ꢏ ꢆꢑ
ꢒ
ꢋ
ꢆ
ꢄ
ꢓ
ꢅ
ꢔ
ꢀ
ꢆ
ꢕ
ꢄ
ꢁ
ꢀ
ꢋ
ꢌ
ꢏ
ꢎ
ꢌ
ꢕ
ꢀ
ꢄ
ꢁ
ꢍ
ꢕ
ꢌ
ꢖ
ꢏ
ꢀ
ꢆ
ꢌ
ꢕ
ꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
functional block diagram
Boundary-Scan Register
26
OE
3
DIR
28
CLKBA
27
SBA
1
CLKAB
2
SAB
C1
1D
4
25
A1
B1
C1
1D
One of Eight Channels
Bypass Register
Boundary-Control
Register
V
CC
13
TDO
16
Instruction Register
TDI
V
CC
14
TMS
TCK
TAP
Controller
15
Pin numbers shown for the DL, DW, and JT packages.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢃ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢈ
ꢀꢋ ꢄꢁ ꢆ ꢌꢀꢆ ꢍꢌꢎ ꢏ ꢋꢌ ꢀ ꢐꢏ ꢆꢑ
ꢒ ꢋꢆꢄꢓ ꢅꢔꢀ ꢆ ꢕꢄꢁꢀ ꢋꢌꢏ ꢎꢌꢕꢀ ꢄꢁꢍ ꢕꢌ ꢖ ꢏꢀ ꢆꢌ ꢕ ꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
Terminal Functions
TERMINAL
NAME
DESCRIPTION
A1−A8
B1−B8
Normal-function A-bus I/O ports. See function table for normal-mode logic.
Normal-function B-bus I/O ports. See function table for normal-mode logic.
Normal-function clock inputs. See function table for normal-mode logic.
CLKAB, CLKBA
DIR
Normal-function direction-control input. See function table for normal-mode logic.
Ground
GND
OE
Normal-function output-enable input. See function table for normal-mode logic.
Normal-function select inputs. See function table for normal-mode logic.
SAB, SBA
Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous
to TCK. Data is captured on the rising edge of TCK, and outputs change on the falling edge of TCK.
TCK
TDI
Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data
through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.
TDO
TMS
Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS input directs the device through
its TAP controller states. An internal pullup forces TMS to a high level if left unconnected.
V
CC
Supply voltage
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢃ ꢈ
ꢀ ꢋꢄ ꢁ ꢆ ꢌꢀ ꢆ ꢍ ꢌ ꢎꢏ ꢋ ꢌꢀ ꢐ ꢏ ꢆꢑ
ꢒꢋ ꢆꢄ ꢓ ꢅ ꢔꢀ ꢆ ꢕꢄ ꢁꢀ ꢋꢌ ꢏ ꢎꢌ ꢕꢀ ꢄꢁ ꢍ ꢕꢌ ꢖꢏ ꢀꢆ ꢌꢕꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
test architecture
Serial-test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Standard
1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 2 shows the TAP-controller state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the
device contains an 8-bit instruction register and three test-data registers: a 40-bit boundary-scan register, an
11-bit boundary-control register, and a 1-bit bypass register.
Test-Logic-Reset
TMS = H
TMS = L
TMS = H
TMS = H
TMS = H
Run-Test/Idle
Select-DR-Scan
TMS = L
Select-IR-Scan
TMS = L
TMS = L
TMS = H
TMS = H
Capture-DR
TMS = L
Capture-IR
TMS = L
Shift-DR
Shift-IR
TMS = L
TMS = L
TMS = H
TMS = H
TMS = H
Exit1-IR
TMS = H
Exit1-DR
TMS = L
TMS = L
Pause-DR
TMS = H
Pause-IR
TMS = H
Exit2-IR
TMS = L
TMS = L
TMS = L
TMS = L
Exit2-DR
TMS = H
TMS = H
Update-IR
Update-DR
TMS = H
TMS = L
TMS = H
TMS = L
Figure 2. TAP-Controller State Diagram
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢃ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢈ
ꢀꢋ ꢄꢁ ꢆ ꢌꢀꢆ ꢍꢌꢎ ꢏ ꢋꢌ ꢀ ꢐꢏ ꢆꢑ
ꢒ ꢋꢆꢄꢓ ꢅꢔꢀ ꢆ ꢕꢄꢁꢀ ꢋꢌꢏ ꢎꢌꢕꢀ ꢄꢁꢍ ꢕꢌ ꢖ ꢏꢀ ꢆꢌ ꢕ ꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
state diagram description
The TAP controller is a synchronous finite-state machine that provides test control signals throughout the
device. The state diagram shown in Figure 2 is in accordance with IEEE Standard 1149.1-1990. The TAP
controller proceeds through its states, based on the level of TMS at the rising edge of TCK.
As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive
TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers also can be reset to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuited.
For the ’ABT8646, the instruction register is reset to the binary value 11111111, which selects the BYPASS
instruction. Each bit in the boundary-scan register is reset to logic 0. The boundary-control register is reset to
the binary value 00000000010, which selects the PSA test operation, with no input masking.
Run-Test/Idle
The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic actively can be running a test or can be idle.
The test operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least-significant bit of the selected data register.
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢃ ꢈ
ꢀ ꢋꢄ ꢁ ꢆ ꢌꢀ ꢆ ꢍ ꢌ ꢎꢏ ꢋ ꢌꢀ ꢐ ꢏ ꢆꢑ
ꢒꢋ ꢆꢄ ꢓ ꢅ ꢔꢀ ꢆ ꢕꢄ ꢁꢀ ꢋꢌ ꢏ ꢎꢌ ꢕꢀ ꢄꢁ ꢍ ꢕꢌ ꢖꢏ ꢀꢆ ꢌꢕꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.
On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the
high-impedance state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, then such update
occurs on the falling edge of TCK, following entry to the Update-DR state.
Capture-IR
When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK upon, which the TAP controller exits the Capture-IR state.
For the ’ABT8646, the status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and,
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to
the logic level present in the least-significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.
On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the
high-impedance state.
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss
of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢃ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢈ
ꢀꢋ ꢄꢁ ꢆ ꢌꢀꢆ ꢍꢌꢎ ꢏ ꢋꢌ ꢀ ꢐꢏ ꢆꢑ
ꢒ ꢋꢆꢄꢓ ꢅꢔꢀ ꢆ ꢕꢄꢁꢀ ꢋꢌꢏ ꢎꢌꢕꢀ ꢄꢁꢍ ꢕꢌ ꢖ ꢏꢀ ꢆꢌ ꢕ ꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
register overview
With the exception of the bypass register, any test register can be thought of as a serial-shift register with a
shadow latch on each bit. The bypass register differs in that it contains only a shift register. During the
appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register
can be parallel loaded from a source specified by the current instruction. During the appropriate shift state
(Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted
in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from
the shift register.
instruction register description
The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation
to be performed, which of the three data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.
Table 3 lists the instructions supported by the ’ABT8646. The even-parity feature specified for SCOPE devices
is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are defined for
SCOPE devices but are not supported by this device default to BYPASS.
During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated,
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 11111111, which selects the BYPASS instruction. The IR order of scan is shown in Figure 3.
Bit 7
Parity
(MSB)
Bit 0
(LSB)
TDI
TDO
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Figure 3. Instruction Register Order of Scan
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢃ ꢈ
ꢀ ꢋꢄ ꢁ ꢆ ꢌꢀ ꢆ ꢍ ꢌ ꢎꢏ ꢋ ꢌꢀ ꢐ ꢏ ꢆꢑ
ꢒꢋ ꢆꢄ ꢓ ꢅ ꢔꢀ ꢆ ꢕꢄ ꢁꢀ ꢋꢌ ꢏ ꢎꢌ ꢕꢀ ꢄꢁ ꢍ ꢕꢌ ꢖꢏ ꢀꢆ ꢌꢕꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
data register description
boundary-scan register
The boundary-scan register (BSR) is 40 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin, two BSCs for each normal-function I/O pin (one for input data and one for output data),
and one BSC for each of the internally decoded output-enable signals (OEA and OEB). The BSR is used 1) to
store test data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the
device output pins, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic
and/or externally at the device input pins.
The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or
in Test-Logic-Reset, the value of each BSC is reset to logic 0.
When external data is to be captured, the BSCs for signals OEA and OEB capture logic values determined by
OEA + OE • DIR, and OEB + OE • DIR
the following positive-logic equations:
externally, these BSCs control the drive state (active or high-impedance) of their respective outputs.
. When data is to be applied
The BSR order of scan is from TDI through bits 39−0 to TDO. Table 1 shows the BSR bits and their associated
device pin signals.
Table 1. Boundary-Scan Register Configuration
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
39
38
37
36
35
34
33
32
OEB
OEA
DIR
31
30
29
28
27
26
25
24
A8-I
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
23
22
21
20
19
18
17
16
A8-O
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
15
14
13
12
11
10
9
B8-I
B7-I
B6-I
B5-I
B4-I
B3-I
B2-I
B1-I
7
6
5
4
3
2
1
0
B8-O
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B1-O
OE
CLKAB
CLKBA
SAB
SBA
8
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢃ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢈ
ꢀꢋ ꢄꢁ ꢆ ꢌꢀꢆ ꢍꢌꢎ ꢏ ꢋꢌ ꢀ ꢐꢏ ꢆꢑ
ꢒ ꢋꢆꢄꢓ ꢅꢔꢀ ꢆ ꢕꢄꢁꢀ ꢋꢌꢏ ꢎꢌꢕꢀ ꢄꢁꢍ ꢕꢌ ꢖ ꢏꢀ ꢆꢌ ꢕ ꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
boundary-control register
The boundary-control register (BCR) is 11 bits long. The BCR is used in the context of the RUNT instruction to
implement additional test operations not included in the basic SCOPE instruction set. Such operations include
PRPG, PSA with input masking, and binary count up (COUNT). Table 4 shows the test operations that are
decoded by the BCR.
During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
reset to the binary value 00000000010, which selects the PSA test operation with no input masking.
The BCR order of scan is from TDI through bits 10−0 to TDO. Table 2 shows the BCR bits and their associated
test control signals.
Table 2. Boundary-Control Register Configuration
TEST
CONTROL
SIGNAL
TEST
CONTROL
SIGNAL
TEST
CONTROL
SIGNAL
BCR BIT
NUMBER
BCR BIT
NUMBER
BCR BIT
NUMBER
10
9
MASK8
MASK7
MASK6
MASK5
6
5
4
3
MASK4
MASK3
MASK2
MASK1
2
1
OPCODE2
OPCODE1
OPCODE0
−−
8
0
7
−−
bypass register
The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
thereby reducing the number of bits per test pattern that must be applied to complete a test operation. During
Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4.
TDI
TDO
Bit 0
Figure 4. Bypass Register Order of Scan
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢃ ꢈ
ꢀ ꢋꢄ ꢁ ꢆ ꢌꢀ ꢆ ꢍ ꢌ ꢎꢏ ꢋ ꢌꢀ ꢐ ꢏ ꢆꢑ
ꢒꢋ ꢆꢄ ꢓ ꢅ ꢔꢀ ꢆ ꢕꢄ ꢁꢀ ꢋꢌ ꢏ ꢎꢌ ꢕꢀ ꢄꢁ ꢍ ꢕꢌ ꢖꢏ ꢀꢆ ꢌꢕꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
instruction-register opcode description
The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of
each instruction.
Table 3. Instruction-Register Opcodes
†
BINARY CODE
BIT 7 → BIT 0
MSB → LSB
SELECTED DATA
REGISTER
SCOPE OPCODE
DESCRIPTION
MODE
00000000
10000001
10000010
00000011
10000100
00000101
00000110
10000111
10001000
00001001
00001010
10001011
00001100
10001101
10001110
00001111
All others
EXTEST/INTEST
Boundary scan
Bypass scan
Boundary scan
Bypass
Test
Normal
Normal
Test
‡
BYPASS
SAMPLE/PRELOAD
INTEST/EXTEST
Sample boundary
Boundary scan
Boundary scan
Bypass
Boundary scan
‡
BYPASS
BYPASS
HIGHZ
Bypass scan
Normal
Normal
Modified test
Test
‡
Bypass scan
Bypass
Control boundary to high impedance
Control boundary to 1/0
Bypass scan
Bypass
CLAMP
Bypass
‡
BYPASS
Bypass
Normal
Test
RUNT
Boundary run test
Bypass
READBN
READBT
CELLTST
TOPHIP
SCANCN
SCANCT
BYPASS
Boundary read
Boundary scan
Boundary scan
Boundary scan
Bypass
Normal
Test
Boundary read
Boundary self test
Boundary toggle outputs
Boundary-control register scan
Boundary-control register scan
Bypass scan
Normal
Test
Boundary control
Boundary control
Bypass
Normal
Test
Normal
†
‡
Bit 7 is used to maintain even parity in the 8-bit instruction.
The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the ’ABT8646.
boundary scan
This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is
selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scanned
into the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned into
the output BSCs is applied to the device output pins. The device operates in the test mode.
bypass scan
This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is
selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the
normal mode.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢃ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢈ
ꢀꢋ ꢄꢁ ꢆ ꢌꢀꢆ ꢍꢌꢎ ꢏ ꢋꢌ ꢀ ꢐꢏ ꢆꢑ
ꢒ ꢋꢆꢄꢓ ꢅꢔꢀ ꢆ ꢕꢄꢁꢀ ꢋꢌꢏ ꢎꢌꢕꢀ ꢄꢁꢍ ꢕꢌ ꢖ ꢏꢀ ꢆꢌ ꢕ ꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
control boundary to high impedance
This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device
input pins remain operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input
BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device
output pins. The device operates in the test mode.
boundary run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up
(PSA/COUNT).
boundary read
The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.
boundary self test
The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output BSCs is toggled on each rising edge of
TCK in Run-Test/Idle, updated in the shadow latches, and applied to the associated device output pins on each
falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and is applied to the
inputs of the normal on-chip logic. Data appearing at the device input pins is not captured in the input BSCs.
The device operates in the test mode.
boundary-control-register scan
The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This
operation must be performed before a boundary-run test operation to specify which test operation is to
be executed.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢃ ꢈ
ꢀ ꢋꢄ ꢁ ꢆ ꢌꢀ ꢆ ꢍ ꢌ ꢎꢏ ꢋ ꢌꢀ ꢐ ꢏ ꢆꢑ
ꢒꢋ ꢆꢄ ꢓ ꢅ ꢔꢀ ꢆ ꢕꢄ ꢁꢀ ꢋꢌ ꢏ ꢎꢌ ꢕꢀ ꢄꢁ ꢍ ꢕꢌ ꢖꢏ ꢀꢆ ꢌꢕꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 2−0 as shown in Table 4. The selected test operation is performed
while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control Register Opcodes
BINARY CODE
BIT 2 → BIT 0
MSB → LSB
DESCRIPTION
X00
X01
X10
011
111
Sample inputs/toggle outputs (TOPSIP)
Pseudorandom pattern generation/16-bit mode (PRPG)
Parallel-signature analysis/16-bit mode (PSA)
Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)
Simultaneous PSA and binary count up/8-bit mode (PSA/COUNT)
In general, while the control input BSCs (bits 39−32) are not included in the sample, toggle, PSA, PRPG, or
COUNT algorithms, the output-enable BSCs (bits 39−38 of the BSR) do control the drive state (active or high
impedance) of the selected device output pins. These BCR instructions are valid only when the device is
operating in one direction of data flow (that is, OEA ≠ OEB). Otherwise, the bypass instruction is operated.
PSA input masking
Bits 10−3 of the BCR specify device input pins to be masked from PSA operations. Bit 10 selects masking for
device input pin A8 during A-to-B data flow or for device input pin B8 during B-to-A data flow. Bit 3 selects
masking for device input pins A1 or B1 during A-to-B or B-to-A data flow, respectively. Bits intermediate to 10
and 3 mask corresponding device input pins, in order, from most significant to least significant, as indicated in
Table 3. When the mask bit that corresponds to a particular device input has a logic 1 value, the device input
pin is masked from any PSA operation, i.e., the state of the device input pin is ignored and has no effect on the
generated signature. Otherwise, when a mask bit has a logic 0 value, the corresponding device input is not
masked from the PSA operation.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input pins is captured in the shift-register elements of the selected BSCs
on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied
to the inputs of the normal on-chip logic. Data in the shift-register elements of the selected output BSCs is
toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output
pins on each falling edge of TCK.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢃ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢈ
ꢀꢋ ꢄꢁ ꢆ ꢌꢀꢆ ꢍꢌꢎ ꢏ ꢋꢌ ꢀ ꢐꢏ ꢆꢑ
ꢒ ꢋꢆꢄꢓ ꢅꢔꢀ ꢆ ꢕꢄꢁꢀ ꢋꢌꢏ ꢎꢌꢕꢀ ꢄꢁꢍ ꢕꢌ ꢖ ꢏꢀ ꢆꢌ ꢕ ꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
pseudorandom pattern generation (PRPG)
A pseudorandom pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge
of TCK. This data also is updated in the shadow latches of the selected input BSCs and applied to the inputs
of the normal on-chip logic. Figures 5 and 6 show the 16-bit linear-feedback shift-register algorithms through
which the patterns are generated. An initial seed value should be scanned into the BSR before performing this
operation. A seed value of all zeroes does not produce additional patterns.
A8-I
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
=
B8-O
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B2-I
B1-O
B1-I
Figure 5. 16-Bit PRPG Configuration (OEA = 0, OEB = 1)
B8-I
B7-I
B6-I
B5-I
B4-I
B3-I
=
A8-O
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
Figure 6. 16-Bit PRPG Configuration (OEA=1, OEB= 0)
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢃ ꢈ
ꢀ ꢋꢄ ꢁ ꢆ ꢌꢀ ꢆ ꢍ ꢌ ꢎꢏ ꢋ ꢌꢀ ꢐ ꢏ ꢆꢑ
ꢒꢋ ꢆꢄ ꢓ ꢅ ꢔꢀ ꢆ ꢕꢄ ꢁꢀ ꢋꢌ ꢏ ꢎꢌ ꢕꢀ ꢄꢁ ꢍ ꢕꢌ ꢖꢏ ꢀꢆ ꢌꢕꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
parallel-signature analysis (PSA)
Data appearing at the selected device input pins is compressed into a 16-bit parallel signature in the
shift-register elements of the selected BSCs on each rising edge of TCK. This data is updated in the shadow
latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow
latches of the selected output BSCs remains constant and is applied to the device outputs. Figures 7 and 8 show
the 16-bit linear-feedback shift-register algorithms through which the signature is generated. An initial seed
value should be scanned into the BSR before performing this operation.
A8-I
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
=
=
B8-O
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B2-I
B1-O
B1-I
Figure 7. 16-Bit PSA Configuration (OEA = 0, OEB = 1)
B8-I
B7-I
B6-I
B5-I
B4-I
B3-I
=
=
A8-O
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
Figure 8. 16-Bit PSA Configuration (OEA = 1, OEB = 0)
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢃ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢈ
ꢀꢋ ꢄꢁ ꢆ ꢌꢀꢆ ꢍꢌꢎ ꢏ ꢋꢌ ꢀ ꢐꢏ ꢆꢑ
ꢒ ꢋꢆꢄꢓ ꢅꢔꢀ ꢆ ꢕꢄꢁꢀ ꢋꢌꢏ ꢎꢌꢕꢀ ꢄꢁꢍ ꢕꢌ ꢖ ꢏꢀ ꢆꢌ ꢕ ꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the selected device input pins is compressed into an 8-bit parallel signature in the
shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the
shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same
time, an 8-bit pseudorandom pattern is generated in the shift-register elements of the selected output BSCs on
each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins on
each falling edge of TCK. Figures 9 and 10 show the 8-bit linear-feedback shift-register algorithms through
which the signature and patterns are generated. An initial seed value should be scanned into the BSR before
performing this operation. A seed value of all zeroes does not produce additional patterns.
A8-I
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
=
=
B8-O
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B2-I
B1-O
B1-I
Figure 9. 8-Bit PSA/PRPG Configuration (OEA = 0, OEB = 1)
B8-I
B7-I
B6-I
B5-I
B4-I
B3-I
=
=
A8-O
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
Figure 10. 8-Bit PSA/PRPG Configuration (OEA = 1, OEB = 0)
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢃ ꢈ
ꢀ ꢋꢄ ꢁ ꢆ ꢌꢀ ꢆ ꢍ ꢌ ꢎꢏ ꢋ ꢌꢀ ꢐ ꢏ ꢆꢑ
ꢒꢋ ꢆꢄ ꢓ ꢅ ꢔꢀ ꢆ ꢕꢄ ꢁꢀ ꢋꢌ ꢏ ꢎꢌ ꢕꢀ ꢄꢁ ꢍ ꢕꢌ ꢖꢏ ꢀꢆ ꢌꢕꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
simultaneous PSA and binary count up (PSA/COUNT)
Data appearing at the selected device input pins is compressed into an 8-bit parallel signature in the
shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the
shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same
time, an 8-bit binary count-up pattern is generated in the shift-register elements of the selected output BSCs
on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins
on each falling edge of TCK. In addition, the shift-register elements of the opposite output BSCs count carries
out of the selected output BSCs, extending the count to 16 bits. Figures 11 and 12 show the 8-bit linear-feedback
shift-register algorithms through which the signature is generated. An initial seed value should be scanned into
the BSR before performing this operation.
A8-I
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
MSB
B8-O
LSB
=
=
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B2-I
B1-O
B1-I
Figure 11. 8-Bit PSA/COUNT Configuration (OEA = 0, OEB = 1)
B8-I
B7-I
B6-I
B5-I
B4-I
B3-I
MSB
A8-O
LSB
=
=
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
Figure 12. 8-Bit PSA/COUNT Configuration (OEA = 1, OEB = 0)
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢃ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢈ
ꢀꢋ ꢄꢁ ꢆ ꢌꢀꢆ ꢍꢌꢎ ꢏ ꢋꢌ ꢀ ꢐꢏ ꢆꢑ
ꢒ ꢋꢆꢄꢓ ꢅꢔꢀ ꢆ ꢕꢄꢁꢀ ꢋꢌꢏ ꢎꢌꢕꢀ ꢄꢁꢍ ꢕꢌ ꢖ ꢏꢀ ꢆꢌ ꢕ ꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
timing description
All test operations of the ’ABT8646 are synchronous to TCK. Data on the TDI, TMS, and normal-function inputs
is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling
edge of TCK. The TAP controller is advanced through its states (as shown in Figure 2) by changing the value
of TMS on the falling edge of TCK and then applying a rising edge to TCK.
A simple timing example is shown in Figure 13. In this example, the TAP controller begins in the
Test-Logic-Reset state and is advanced through its states as necessary to perform one instruction-register scan
and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO
is used to output serial data. The TAP controller then is returned to the Test-Logic-Reset state. Table 5 details
the operation of the test circuitry during each TCK cycle.
Table 5. Explanation of Timing Example
TCK
CYCLE(S)
TAP STATE
AFTER TCK
DESCRIPTION
TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.
1
Test-Logic-Reset
2
3
4
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the
Capture-IR state.
5
6
Capture-IR
Shift-IR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned
out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next
TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.
7−13
Shift-IR
14
15
16
Exit1-IR
Update-IR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.
Select-DR-Scan
The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the
Capture-DR state.
17
18
Capture-DR
Shift-DR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
19−20
21
Shift-DR
Exit1-DR
The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
In general, the selected data register is updated with the new data on the falling edge of TCK.
22
Update-DR
23
Select-DR-Scan
Select-IR-Scan
Test-Logic-Reset
24
25
Test operation completed
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢃ ꢈ
ꢀ ꢋꢄ ꢁ ꢆ ꢌꢀ ꢆ ꢍ ꢌ ꢎꢏ ꢋ ꢌꢀ ꢐ ꢏ ꢆꢑ
ꢒ
ꢋ
ꢆ
ꢄ
ꢓ
ꢅ
ꢔ
ꢀ
ꢆ
ꢕ
ꢄ
ꢁ
ꢀ
ꢋ
ꢌ
ꢏ
ꢎ
ꢌ
ꢕ
ꢀ
ꢄ
ꢁ
ꢍ
ꢕ
ꢌ
ꢖ
ꢏ
ꢀ
ꢆ
ꢌ
ꢕ
ꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TCK
TMS
TDI
TDO
TAP
Controller
State
3-State (TDO) or Don’t Care (TDI)
Figure 13. Timing Example
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Input voltage range, V (I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
I
Voltage range applied to any output in the high state or power-off state, V
. . . . . . . . . . . . . . −0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT8646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT8646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . . . . . . . . . 0.7 W
A
DW package . . . . . . . . . . . . . . . . . . 1.7 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢃ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢈ
ꢀꢋ ꢄꢁ ꢆ ꢌꢀꢆ ꢍꢌꢎ ꢏ ꢋꢌ ꢀ ꢐꢏ ꢆꢑ
ꢋꢆꢄꢓ ꢅꢔꢀ ꢆ ꢕꢄꢁꢀ ꢋꢌꢏ ꢎꢌꢕꢀ ꢄꢁꢍ ꢕꢌ ꢖ ꢏꢀ ꢆꢌ ꢕ ꢀ
ꢒ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
recommended operating conditions (see Note 3)
SN54ABT8646 SN74ABT8646
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−24
48
−32
64
mA
mA
ns/V
°C
OH
OL
∆t/∆v
10
10
T
−55
125
−40
85
A
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢃ ꢈ
ꢀ ꢋꢄ ꢁ ꢆ ꢌꢀ ꢆ ꢍ ꢌ ꢎꢏ ꢋ ꢌꢀ ꢐ ꢏ ꢆꢑ
ꢒꢋ ꢆꢄ ꢓ ꢅ ꢔꢀ ꢆ ꢕꢄ ꢁꢀ ꢋꢌ ꢏ ꢎꢌ ꢕꢀ ꢄꢁ ꢍ ꢕꢌ ꢖꢏ ꢀꢆ ꢌꢕꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT8646 SN74ABT8646
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = −18 mA
−1.2
−1.2
−1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= −3 mA
= −3 mA
= −24 mA
= −32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
1
V
OL
V
V
0.55*
0.55
1
CLK, DIR,
OE, S, TCK
1
I
I
V
CC
= 5.5 V, V = V
I
or GND
CC
µA
CC
A or B ports
TDI, TMS
TDI, TMS
100
10
100
10
100
10
I
I
I
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 0,
V = V
I
µA
µA
µA
µA
µA
µA
µA
µA
mA
IH
V = GND
I
−40
−160
50
−40
−160
50
−40
−160
50
IL
‡
V
= 2.7 V
= 0.5 V
OZH
O
O
‡
V
−50
100
50
−50
−50
100
50
OZL
off
V or V ≤ 4.5 V
I
O
= 0 to 2 V,
= 2 V to 0,
= 5.5 V,
= 5.5 V,
V
O
V
O
V
O
V
O
= 0.5 V or 2.7 V
50
50
OZPU
OZPD
CEX
= 0.5 V or 2.7 V
= 5.5 V
50
50
Outputs high
A or B ports
50
50
50
§
= 2.5 V
−50 −100 −180
−50
−180
2
−50
−180
2
O
Outputs high
Outputs low
0.9
30
2
38
2
V
I
= 5.5 V,
= 0,
CC
O
38
38
I
mA
CC
V = V
I
or GND
CC
Outputs disabled
0.9
2
2
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
¶
1.5
1.5
1.5
mA
∆I
CC
or GND
CC
Control inputs V = 2.5 V or 0.5 V
C
C
C
3
10
8
pF
pF
pF
i
I
A or B ports
TDO
V
= 2.5 V or 0.5 V
= 2.5 V or 0.5 V
io
o
O
O
V
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
include the input leakage current.
CC
OZL
The parameters I
and I
OZH
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V or GND.
CC
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢃ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢈ
ꢀꢋ ꢄꢁ ꢆ ꢌꢀꢆ ꢍꢌꢎ ꢏ ꢋꢌ ꢀ ꢐꢏ ꢆꢑ
ꢒ ꢋꢆꢄꢓ ꢅꢔꢀ ꢆ ꢕꢄꢁꢀ ꢋꢌꢏ ꢎꢌꢕꢀ ꢄꢁꢍ ꢕꢌ ꢖ ꢏꢀ ꢆꢌ ꢕ ꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 14)
SN54ABT8646 SN74ABT8646
UNIT
MIN
0
MAX
MIN
0
MAX
f
t
t
t
Clock frequency
Pulse duration
Setup time
CLKAB or CLKBA
100
100
MHz
ns
clock
CLKAB or CLKBA high or low
A before CLKAB↑ or B before CLKBA↑
A after CLKAB↑ or B after CLKBA↑
3
3
w
4.7
0
4.5
0
ns
su
h
Hold time
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 14)
SN54ABT8646 SN74ABT8646
UNIT
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
Pulse duration
TCK
50
50
MHz
ns
clock
TCK high or low
5
5
w
A, B, CLK, DIR, OE, or S before TCK↑
TDI before TCK↑
7
5
6
6
t
Setup time
Hold time
ns
ns
su
h
TMS before TCK↑
6
6
A, B, CLK, DIR, OE, or S after TCK↑
TDI after TCK↑
0
0
0
0
t
TMS after TCK↑
0
0
t
t
Delay time
Rise time
Power up to TCK↑
50*
1*
50
1
ns
d
V
CC
power up
µs
r
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢃ ꢈ
ꢀ ꢋꢄ ꢁ ꢆ ꢌꢀ ꢆ ꢍ ꢌ ꢎꢏ ꢋ ꢌꢀ ꢐ ꢏ ꢆꢑ
ꢒꢋ ꢆꢄ ꢓ ꢅ ꢔꢀ ꢆ ꢕꢄ ꢁꢀ ꢋꢌ ꢏ ꢎꢌ ꢕꢀ ꢄꢁ ꢍ ꢕꢌ ꢖꢏ ꢀꢆ ꢌꢕꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 14)
SN54ABT8646
V
T
= 5 V,
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
CC
A
PARAMETER
UNIT
MIN
MAX
MIN
100
2
TYP
130
3.7
3.5
4.4
4.3
4.8
4.7
4.4
4.8
4.4
5.2
6
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLKAB or CLKBA
A or B
100
2
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
4.5
4.6
5.3
5.2
6
5.5
5.8
6.3
6.7
7.5
7.8
6.6
8.1
6.7
7.6
8.9
8.1
8.6
8.3
B or A
B or A
B or A
B or A
B or A
B or A
B or A
2
2
3
3
CLKAB or CLKBA
ns
ns
ns
ns
ns
ns
2.5
2
2.5
2
SAB or SBA
2
5.9
5.4
6.2
5.4
6.2
7.9
6.6
7.7
6.2
2
2.5
3
2.5
3
DIR
OE
DIR
OE
2.5
3
2.5
3
3
3
3
5.2
5.9
5.2
3
2
2.8
3
3
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 14)
SN74ABT8646
V
T
= 5 V,
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
CC
A
PARAMETER
UNIT
MIN
MAX
MIN
100
2
TYP
130
3.7
3.5
4.4
4.3
4.8
4.7
4.4
4.8
4.4
5.2
6
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLKAB or CLKBA
A or B
100
2
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
4.5
4.4
5.3
5.2
6
5.2
5.5
6
B or A
B or A
B or A
B or A
B or A
B or A
B or A
2
2
3
3
CLKAB or CLKBA
ns
ns
ns
ns
ns
ns
2.5
2
2.5
2
6.2
7.3
7.4
6.5
7.1
6.5
7.5
8.6
7.9
7.9
7.4
SAB or SBA
2
5.9
5.3
6.2
5.4
6.2
7
2
2.5
3
2.5
3
DIR
OE
DIR
OE
2.5
3
2.5
3
3
3
3
5.2
5.9
5.2
6.2
6.9
6.2
3
3
3
3
3
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢃ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢈ
ꢀꢋ ꢄꢁ ꢆ ꢌꢀꢆ ꢍꢌꢎ ꢏ ꢋꢌ ꢀ ꢐꢏ ꢆꢑ
ꢒ ꢋꢆꢄꢓ ꢅꢔꢀ ꢆ ꢕꢄꢁꢀ ꢋꢌꢏ ꢎꢌꢕꢀ ꢄꢁꢍ ꢕꢌ ꢖ ꢏꢀ ꢆꢌ ꢕ ꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 14)
SN54ABT8646
V
T
= 5 V,
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
CC
A
PARAMETER
UNIT
MIN
MAX
MIN
50
3.5
3
TYP
90
8
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
TCK
50
3.5
3
MHz
ns
max
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
9.5
10
13.4
12
TCK↓
A or B
TDO
7.7
4.3
4.2
8.2
9
2.5
2.5
4.5
4.5
2.5
2.5
3.5
3
5.5
5.5
9.7
11.2
5.5
6
2.5
2.5
4.5
4.5
2.5
2.5
3.5
3
7
TCK↓
TCK↓
TCK↓
TCK↓
TCK↓
ns
ns
ns
ns
ns
7
12.5
13.5
7
A or B
TDO
4.3
4.9
8.4
8
7.5
14.5
13.5
9
13
A or B
TDO
10.5
7
3
5.9
5
3
3
6.5
3
8
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 14)
SN74ABT8646
V
T
= 5 V,
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
CC
A
PARAMETER
UNIT
MIN
MAX
MIN
50
3.5
3
TYP
90
8
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
TCK
50
3.5
3
MHz
ns
max
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
9.5
9
12
11.5
6.5
6.5
12
TCK↓
A or B
TDO
7.7
4.3
4.2
8.2
9
2.5
2.5
4.5
4.5
2.5
2.5
3.5
3
5.5
5.5
9.5
10.5
5.5
6
2.5
2.5
4.5
4.5
2.5
2.5
3.5
3
TCK↓
TCK↓
TCK↓
TCK↓
TCK↓
ns
ns
ns
ns
ns
A or B
TDO
13
4.3
4.9
8.4
8
6.5
7
10.5
10.5
7
13.5
13
A or B
TDO
3
5.9
5
3
8.5
7.5
3
6.5
3
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢃꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢃ ꢈ
ꢀ ꢋꢄ ꢁ ꢆ ꢌꢀ ꢆ ꢍ ꢌ ꢎꢏ ꢋ ꢌꢀ ꢐ ꢏ ꢆꢑ
ꢒꢋ ꢆꢄ ꢓ ꢅ ꢔꢀ ꢆ ꢕꢄ ꢁꢀ ꢋꢌ ꢏ ꢎꢌ ꢕꢀ ꢄꢁ ꢍ ꢕꢌ ꢖꢏ ꢀꢆ ꢌꢕꢀ
SCBS123F − AUGUST 1992 − REVISED APRIL 2004
PARAMETER MEASUREMENT INFORMATION
7 V
S1
500 Ω
Open
GND
From Output
Under Test
TEST
S1
t
t
/t
Open
7 V
PLH PHL
/t
C
= 50 pF
L
t
500 Ω
PLZ PZL
/t
(see Note A)
Open
PHZ PZH
LOAD CIRCUIT
3 V
0 V
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
3 V
0 V
3 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
PLZ
t
t
PHL
PZL
PLH
Output
Waveform 1
S1 at 7 V
V
V
3.5 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
− 0.3 V
OH
1.5 V
1.5 V
Output
9 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 14. Load Circuit and Voltage Waveforms
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
SSOP
Drawing
5962-9458601Q3A
5962-9458601QXA
SN74ABT8646DL
ACTIVE
ACTIVE
ACTIVE
FK
28
28
28
1
1
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB N / A for Pkg Type
JT
DL
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ABT8646DLG4
SN74ABT8646DLR
SN74ABT8646DLRG4
SN74ABT8646DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
DL
DL
28
28
28
28
28
28
28
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
DW
DW
DW
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ABT8646DWE4
SN74ABT8646DWR
SN74ABT8646DWRE4
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54ABT8646FK
SNJ54ABT8646JT
ACTIVE
ACTIVE
LCCC
CDIP
FK
JT
28
28
1
1
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Low Power Wireless www.ti.com/lpw
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2006, Texas Instruments Incorporated
相关型号：
SN74ABT8646DWG4
ABT SERIES, 8-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PDSO28, GREEN, PLASTIC, SOIC-28
TI
©2020 ICPDF网 联系我们和版权申明