SN74ABTH32245MPZEP [TI]
ABT SERIES, QUAD 9-BIT TRANSCEIVER, TRUE OUTPUT, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100;
| 型号： | SN74ABTH32245MPZEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ABT SERIES, QUAD 9-BIT TRANSCEIVER, TRUE OUTPUT, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 信息通信管理 输出元件 逻辑集成电路 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ABTH32245-EP
36-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS758A – JULY 2002 – REVISED AUGUST 2002
Controlled Baseline
State-of-the-Art EPIC-ΙΙB BiCMOS Design
– One Assembly/Test Site, One Fabrication
Site
Significantly Reduces Power Dissipation
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
Extended Temperature Performance of
–55°C to 125°C
= 5 V, T = 25°C
CC A
High-Impedance State During Power Up
and Power Down
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
Enhanced Product Change Notification
†
Qualification Pedigree
High-Drive Outputs (–32-mA I , 64-mA I
OH
)
OL
Members of the Texas Instruments
Widebus+ Family
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life.
100-Pin Plastic Thin Quad Flat (PZ)
Package With 14- × 14-mm Body Using
0.5-mm Lead Pitch
PZ PACKAGE
(TOP VIEW)
1009998 9796 959493 92 9190 89 8887 86 8584 83 8281 8079 7877 76
1A9
2A1
GND
2A2
2A3
2A4
2A5
GND
2A6
2A7
2A8
2A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1B9
2B1
GND
2B2
2B3
2B4
2B5
GND
2B6
2B7
2B8
2B9
V
V
CC
CC
3A1
3A2
3A3
3A4
GND
3A5
3A6
3A7
3A8
GND
3A9
4A1
3B1
3B2
3B3
3B4
GND
3B5
3B6
3B7
3B8
GND
3B9
4B1
26 272829 3031 32 33 343536 3738 3940 4142 43 4445 46 474849 50
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ and EPIC-ΙΙB are trademarks of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABTH32245-EP
36-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS758A – JULY 2002 – REVISED AUGUST 2002
description
The ’ABTH32245 is a 36-bit (quad 9-bit) noninverting 3-state transceiver designed for synchronous two-way
communication between data buses. The control-function implementation minimizes external timing
requirements.
This device can be used as four 9-bit transceivers, two18-bit transceivers, or one 36-bit transceiver. It allows
data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at
the direction-control (DIR) inputs. The output-enable (OE) inputs can be used to disable the device so that the
buses are effectively isolated.
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
–55°C to 125°C
LQFP – PZ
SN74ABTH32245MPZEP
74ABTH32245MEP
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each 9-bit section)
INPUTS
OPERATION
DIR
L
OE
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABTH32245-EP
36-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS758A – JULY 2002 – REVISED AUGUST 2002
logic diagram (positive logic)
90
40
14
1DIR
3DIR
3A1
89
84
39
1OE
1B1
3OE
One of Nine
Channels
One of Nine
Channels
92
1A1
62
3B1
To Eight Other Channels
To Eight Other Channels
86
36
25
2DIR
2A1
4DIR
4A1
87
74
37
2OE
2B1
4OE
One of Nine
Channels
One of Nine
Channels
2
51
4B1
To Eight Other Channels
To Eight Other Channels
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABTH32245-EP
36-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS758A – JULY 2002 – REVISED AUGUST 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
O
Current into any output in the low state, I
O
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Package thermal impedance, θ (see Note 2): PZ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50°C/W
Storage temperature range, T
JA
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
4.5
2
MAX
UNIT
V
V
V
V
V
Supply voltage
5.5
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
V
IL
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
–24
48
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
200
CC
T
Operating free-air temperature
–55
125
A
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABTH32245-EP
36-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS758A – JULY 2002 – REVISED AUGUST 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
V
IK
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= 48 mA
2.5
3
OH
OH
OH
OL
V
OH
V
= 4.5 V
= 4.5 V
2
V
V
0.55
V
OL
100
mV
hys
Control inputs
A or B ports
±1
I
V
V
= 5.5 V,
= 4.5 V
V = V
CC
or GND
µA
µA
I
CC
I
±20
V = 0.8 V
I
100
I
A or B ports
I(hold)
CC
V = 2 V
I
–100
‡
I
I
I
I
V
V
V
V
= 0 to 2.1 V, V = 0.5 V to 2.7 V, OE = X
±50
±50
50
µA
µA
µA
mA
OZPU
OZPD
CEX
CC
CC
CC
CC
O
‡
= 2.1 V to 0, V = 0.5 V to 2.7 V, OE = X
O
= 5.5 V, V = 5.5 V
O
Outputs high
= 2.5 V
§
= 5.5 V,
V
O
–50
–100
–180
3
O
Outputs high
Outputs low
V
I
= 5.5 V,
= 0,
CC
O
I
20
mA
CC
V = V
or GND
I
CC
Outputs disabled
2
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
¶
1
mA
∆I
CC
or GND
CC
Control inputs V = 2.5 V or 0.5 V
C
C
3.5
9.5
pF
pF
i
I
A or B ports
V
O
= 2.5 V or 0.5 V
io
†
‡
§
¶
All typical values are at V
This parameter is specified by characterization.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V or GND.
= 5 V, T = 25°C.
A
CC
CC
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
t
t
t
t
t
t
1
1
5.3
5.3
7.6
8.2
6.7
7.2
PLH
PHL
PZH
PZL
PHZ
PLZ
A or B
B or A
B or A
B or A
ns
1
ns
ns
OE
OE
1.5
0.8
1
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABTH32245-EP
36-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS758A – JULY 2002 – REVISED AUGUST 2002
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Texas Instruments
Post Office Box 655303
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Copyright 2002, Texas Instruments Incorporated
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