SN74AC240QDWRQ1 [TI]
OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS; 八路缓冲器/驱动器,具有三态输出型号: | SN74AC240QDWRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS |
文件: | 总10页 (文件大小:197K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢃ ꢇꢈ ꢉ ꢊ
ꢋ ꢅꢌꢄꢍ ꢎꢏꢐ ꢐ ꢑ ꢒꢓ ꢔꢒ ꢕ ꢖꢑ ꢒ
ꢗ ꢕꢌ ꢘ ꢙ ꢈꢀꢌꢄꢌ ꢑ ꢋ ꢏꢌ ꢚꢏ ꢌꢀ
SCAS785A − OCTOBER 2004 − REVISED JANUARY 2008
DW OR PW PACKAGE
(TOP VIEW)
D
D
D
D
Qualified for Automotive Applications
2-V to 6-V V Operation
CC
Inputs Accept Voltages to 6 V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
Max t of 6.5 ns at 5 V
pd
description/ordering information
This octal buffer and line driver is designed
specifically to improve the performance and density
of 3-state memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
The SN74AC240 device is organized as two 4-bit
buffers/drivers with separate output-enable (OE)
inputs. When OE is low, the device passes inverted
data from the A inputs to the Y outputs. When OE is
high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
†
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
SOIC − DW
TSSOP − PW
Tape and reel SN74AC240QDWRQ1
Tape and reel SN74AC240QPWRQ1
AC240Q
AC240Q
−40°C to 125°C
†
‡
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
L
H
Z
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2008, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢃ ꢇꢈꢉꢊ
ꢋꢅ ꢌꢄ ꢍ ꢎ ꢏ ꢐꢐ ꢑꢒ ꢓꢔ ꢒꢕ ꢖ ꢑꢒ
ꢗꢕ ꢌꢘ ꢙ ꢈꢀꢌꢄꢌ ꢑ ꢋꢏꢌ ꢚ ꢏꢌꢀ
SCAS785A − OCTOBER 2004 − REVISED JANUARY 2008
logic diagram (positive logic)
1
1OE
18
16
2
4
6
1Y1
1Y2
1A1
1A2
1A3
1A4
14
12
1Y3
1Y4
8
19
2OE
9
7
11
13
15
17
2Y1
2Y2
2A1
2A2
5
3
2Y3
2Y4
2A3
2A4
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
JA
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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ꢋ ꢅꢌꢄꢍ ꢎꢏꢐ ꢐ ꢑꢒ ꢓꢔ ꢒ ꢕꢖ ꢑ ꢒ
ꢗ ꢕꢌ ꢘ ꢙ ꢈꢀꢌꢄꢌ ꢑ ꢋ ꢏꢌ ꢚꢏ ꢌꢀ
SCAS785A − OCTOBER 2004 − REVISED JANUARY 2008
recommended operating conditions (see Note 3)
MIN
2
MAX
UNIT
V
Supply voltage
6
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
2.1
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
V
High-level input voltage
V
V
0.9
1.35
1.65
= 4.5 V
= 5.5 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
V
V
I
CC
Output voltage
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
−12
−24
−24
12
= 4.5 V
= 5.5 V
= 3 V
I
High-level output current
Low-level output current
mA
mA
OH
= 4.5 V
= 5.5 V
24
I
OL
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
8
ns/V
T
A
−40
125
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢃ ꢇꢈꢉꢊ
ꢋꢅ ꢌꢄ ꢍ ꢎ ꢏ ꢐꢐ ꢑꢒ ꢓꢔ ꢒꢕ ꢖ ꢑꢒ
ꢗꢕ ꢌꢘ ꢙ ꢈꢀꢌꢄꢌ ꢑ ꢋꢏꢌ ꢚ ꢏꢌꢀ
SCAS785A − OCTOBER 2004 − REVISED JANUARY 2008
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= −40°C
T = −40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
2.9
TYP
MAX
MIN
2.9
4.4
5.4
2.4
3.7
4.7
3.85
MAX
MIN
2.9
MAX
3 V
4.5 V
5.5 V
3 V
4.4
4.4
I
= −50 µA
OH
5.4
5.4
I
I
= −12 mA
= −24 mA
2.56
3.86
4.86
2.46
3.76
4.76
OH
V
OH
V
4.5 V
5.5 V
5.5 V
5.5 V
3 V
OH
†
†
I
I
= −50 mA
OH
= −75 mA
3.85
OH
0.1
0.1
0.1
0.1
0.1
0.1
4.5 V
5.5 V
3 V
I
= 50 µA
OL
0.1
0.1
0.1
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
0.5
0.44
0.44
0.44
OL
V
OL
V
4.5 V
5.5 V
5.5 V
5.5 V
0.5
OL
0.5
†
†
I
I
= 50 mA
1.65
OL
= 75 mA
1.65
1
OL
Data inputs
V = V
or GND
or GND
0.1
0.1
1
1
I
CC
I
5.5 V
5.5 V
µA
µA
I
Control inputs V = V
1
I
CC
V
V
= V or GND,
CC
I(OE)
O
‡
0.25
4
5
2.5
40
I
I
OZ
= V or V
IL IH
V = V
or GND,
or GND
I = 0
O
5.5 V
5 V
80
µA
CC
I
CC
C
V = V
2.5
pF
i
I
CC
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter I includes the input leakage current.
OZ
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
= −40°C
T = −40°C
A
A
T
A
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
TO 125°C
TO 85°C
PARAMETER
UNIT
MIN
1.5
1.5
1.5
1.5
1.5
1.5
TYP
6
MAX
8
MIN
1
MAX
MIN
1
MAX
9
t
t
t
t
t
t
11
10.5
11.5
13
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
ns
ns
ns
5.5
6
8
1
1
8.5
11
10.5
10
1
1
OE
OE
7
1
1
11
7
10
1
12.5
13.5
1
10.5
11.5
7.5
10.5
1
1
4
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ꢗ ꢕꢌ ꢘ ꢙ ꢈꢀꢌꢄꢌ ꢑ ꢋ ꢏꢌ ꢚꢏ ꢌꢀ
SCAS785A − OCTOBER 2004 − REVISED JANUARY 2008
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
= −40°C
T = −40°C
A
A
T
A
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
TO 125°C
TO 85°C
PARAMETER
UNIT
MIN
1.5
1.5
1.5
1.5
2.5
2
TYP
4.5
4.5
5
MAX
MIN
1
MAX
MIN
1
MAX
7
t
t
t
t
t
t
6.5
6
8.5
8
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
ns
ns
ns
1
1
6.5
8
7
1
9
1
OE
OE
5.5
6.5
6.5
8
1
10.5
10.5
11
1
8.5
9.5
9.5
9
1
1
9
1
1
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
C
Power dissipation capacitance per buffer/driver
C
45
pF
pd
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
Open
2 × V
S1
Open
500 Ω
t
t
/t
PLH PHL
/t
From Output
Under Test
t
PLZ PZL
/t
CC
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
Output
Control
(low-level
enabling)
V
LOAD CIRCUIT
CC
50% V
CC
50% V
CC
0 V
t
t
PLZ
PZL
V
CC
Output
≈V
CC
Input
50% V
CC
50% V
CC
Waveform 1
50% V
CC
0 V
V
+ 0.3 V
S1 at 2 × V
(see Note B)
OL
CC
V
OL
t
PLH
t
PHL
t
t
PZH
PHZ
− 0.3 V
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
OH
V
OH
50% V
CC
50% V
Output
50% V
CC
CC
V
≈0 V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Oct-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74AC240QPWRG4Q1
SN74AC240QPWRQ1
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
20
20
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AC240-Q1 :
Catalog: SN74AC240
•
Military: SN54AC240
•
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Oct-2011
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
•
Military - QML certified for Military and Defense Applications
Addendum-Page 2
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