SN74AC373DBLE [TI]
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS; 八路D型透明锁存器带3态输出
| 型号： | SN74AC373DBLE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS |
| 文件： | 总19页 (文件大小：590K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
SN54AC373 . . . J OR W PACKAGE
SN74AC373 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
2-V to 6-V V
Operation
CC
Inputs Accept Voltages to 6 V
Max t of 9.5 ns at 5 V
pd
3-State Noninverting Outputs Drive Bus
Lines Directly
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
D
Full Parallel Access for Loading
description/ordering information
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
GND
SN54AC373 . . . FK PACKAGE
(TOP VIEW)
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
3
2
1
20 19
18
2D
2Q
3Q
3D
4D
8D
7D
7Q
6Q
6D
4
5
6
7
8
17
16
15
14
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines in bus-organized systems without need for
interface or pullup components.
9 10 11 12 13
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube
SN74AC373N
SN74AC373N
Tube
SN74AC373DW
SN74AC373DWR
SN74AC373NSR
SN74AC373DBR
SN74AC373PW
SN74AC373PWR
SNJ54AC373J
SOIC − DW
AC373
Tape and reel
Tape and reel
Tape and reel
Tube
SOP − NS
AC373
AC373
−40°C to 85°C
−55°C to 125°C
SSOP − DB
TSSOP − PW
AC373
Tape and reel
Tube
CDIP − J
CFP − W
LCCC − FK
SNJ54AC373J
SNJ54AC373W
SNJ54AC373FK
Tube
SNJ54AC373W
SNJ54AC373FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆꢈ ꢀꢁ ꢇ ꢃ ꢄꢅꢆ ꢇ ꢆ
ꢉꢅ ꢊꢄ ꢋ ꢌ ꢍꢊ ꢎꢏꢐ ꢊꢑ ꢄꢁ ꢀꢏꢄꢑ ꢐꢁ ꢊ ꢋꢄꢊꢅ ꢒ ꢐꢀ
ꢓꢔ ꢊ ꢒ ꢆ ꢍꢀꢊꢄꢊ ꢐ ꢉꢕꢊ ꢏꢕ ꢊꢀ
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
OE
LE
11
C1
1D
2
1Q
3
1D
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC)
O
Output clamp current, I
(V < 0 or V > V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O
CC)
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢓ ꢔꢊ ꢒ ꢆ ꢍꢀꢊꢄꢊ ꢐ ꢉ ꢕꢊ ꢏꢕ ꢊ
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
recommended operating conditions (see Note 3)
SN54AC373
SN74AC373
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
6
6
V
CC
V
= 3 V
2.1
2.1
CC
CC
CC
CC
CC
CC
V
V
V
V
V
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
3.15
3.85
High-level input voltage
V
V
IH
0.9
1.35
1.65
0.9
1.35
1.65
= 4.5V
= 5.5 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
−12
−24
−24
12
−12
−24
−24
12
= 4.5 V
= 5.5 V
= 3 V
I
High-level output current
Low-level output current
mA
mA
OH
= 4.5 V
= 5.5 V
24
24
I
OL
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
8
8
ns/V
T
A
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
SN54AC373
SN74AC373
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
2.9
4.4
5.4
TYP
MAX
MIN
2.9
4.4
5.4
2.4
3.7
4.7
MAX
MIN
2.9
MAX
3 V
4.5 V
5.5 V
4.4
I
= −50 µA
OH
5.4
V
OH
V
I
I
= −12 mA
= −24 mA
3 V 2.56
4.5 V 3.86
5.5 V 4.86
3 V
2.46
3.76
4.76
OH
OH
0.1
0.1
0.1
0.1
0.5
0.5
0.5
1
0.1
0.1
0.1
0.44
0.44
0.44
1
4.5 V
0.1
0.1
I
= 50 µA
OL
5.5 V
V
OL
V
I
I
= 12 mA
= 24 mA
3 V
0.36
0.36
0.36
0.1
OL
4.5 V
OL
5.5 V
I
I
I
V = V
or GND
5.5 V
µA
µA
µA
pF
I
I
CC
V
= V
O CC
or GND
5.5 V
0.25
4
5
2.5
40
OZ
CC
V = V
or GND,
or GND
I = 0
O
5.5 V
80
I
CC
C
V = V
5 V
4.5
i
I
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆꢈ ꢀꢁ ꢇ ꢃ ꢄꢅꢆ ꢇ ꢆ
ꢉꢅ ꢊꢄ ꢋ ꢌ ꢍꢊ ꢎꢏꢐ ꢊꢑ ꢄꢁ ꢀꢏꢄꢑ ꢐꢁ ꢊ ꢋꢄꢊꢅ ꢒ ꢐꢀ
ꢓꢔ ꢊ ꢒ ꢆ ꢍꢀꢊꢄꢊ ꢐ ꢉꢕꢊ ꢏꢕ ꢊꢀ
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54AC373
SN74AC373
A
UNIT
MIN
5.5
5.5
1
MAX
MIN
6.5
6.5
1
MAX
MIN
6
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
6
1
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54AC373
SN74AC373
A
UNIT
MIN
4
MAX
MIN
5
MAX
MIN
4.5
4.5
1
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
4
5
1
1
switching characteristics over recommended operating free-air temperature range,
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
10
SN54AC373
SN74AC373
TO
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
13.5
13.0
13.5
12.5
11.5
11.5
12.5
11.5
MIN
1
MAX
16.5
16
MIN
1.5
1.5
1.5
1.5
1
MAX
15
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
9.5
10
1
14.5
15
1
16.5
15
LE
OE
OE
ns
9.5
9
1
14
1
14
13
ns
8.5
10
1
13.5
16
1
13
1
1
14.5
12.5
ns
8
1
13
1
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T = 25°C
A
SN54AC373
SN74AC373
TO
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
TYP
7
MAX
9.5
9.5
9.5
9.5
8.5
8.5
11
MIN
1
MAX
11.5
11.5
12
MIN
1.5
1.5
1.5
1.5
1
MAX
10.5
10.5
10.5
10.5
9.5
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
7
1
7.5
7
1
LE
OE
OE
ns
1
11
7
1
10.5
10
ns
6.5
8
1
1
9.5
1
13.5
10.5
1
12.5
10
ns
6.5
8.5
1
1
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
TYP
40
UNIT
C
Power dissipation capacitance
C
pF
pd
L
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢓ ꢔꢊ ꢒ ꢆ ꢍꢀꢊꢄꢊ ꢐ ꢉ ꢕꢊ ꢏꢕ ꢊ
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
t
/t
Open
PLH PHL
/t
500 Ω
Open
From Output
Under Test
t
2 × V
CC
PLZ PZL
t
/t
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
V
CC
50% V
CC
Timing Input
Data Input
0 V
t
w
t
h
t
3 V
0 V
su
V
CC
50% V
50% V
Input
CC
CC
50% V
50% V
CC
CC
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
V
V
CC
CC
Input
50% V
t
50% V
CC
50% V
50% V
CC
CC
CC
0 V
0 V
t
t
t
PZL
PLZ
PHL
PLH
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
50%V
CC
CC
CC
V + 0.3 V
OL
S1 at 2 × V
(see Note B)
CC
V
OL
V
OL
t
t
t
PZH
PHZ
PLH
t
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
V
OH
OH
V
OH
− 0.3 V
Out-of-Phase
Output
50% V
50% V
50% V
CC
CC
CC
≈0 V
V
OL
VOLTAGE WAVEFORMS
includes probe and jig capacitance.
VOLTAGE WAVEFORMS
NOTES: A.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-87555012A
5962-8755501RA
5962-8755501SA
5962-8755501VRA
5962-8755501VSA
SN74AC373DBLE
SN74AC373DBR
ACTIVE
ACTIVE
FK
J
20
20
20
20
20
20
20
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Call TI
ACTIVE
W
J
ACTIVE
CDIP
CFP
A42 SNPB
A42
ACTIVE
W
DB
DB
OBSOLETE
ACTIVE
SSOP
SSOP
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC373DBRE4
SN74AC373DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
DB
DW
DW
DW
DW
N
20
20
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC373DWE4
SN74AC373DWR
SN74AC373DWRE4
SN74AC373N
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74AC373NE4
SN74AC373NSR
SN74AC373NSRE4
SN74AC373PW
N
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
NS
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC373PWE4
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC373PWLE
SN74AC373PWR
OBSOLETE TSSOP
PW
PW
20
20
TBD
Call TI
Call TI
ACTIVE
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC373PWRE4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54AC373FK
SNJ54AC373J
SNJ54AC373W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
(mm)
16
SN74AC373DBR
SN74AC373DWR
SN74AC373NSR
SN74AC373PWR
DB
DW
NS
20
20
20
20
MLA
MLA
MLA
MLA
8.2
10.8
8.2
7.5
13.0
13.0
7.1
2.5
2.7
2.5
1.6
12
12
12
8
16
24
24
16
Q1
Q1
Q1
Q1
24
24
PW
16
6.95
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74AC373DBR
SN74AC373DWR
SN74AC373NSR
SN74AC373PWR
DB
DW
NS
20
20
20
20
MLA
MLA
MLA
MLA
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
28.58
31.75
31.75
28.58
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2007
Pack Materials-Page 3
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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