SN74AC373NSRG4 [TI]
AC SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SOP-20;
| 型号： | SN74AC373NSRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AC SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SOP-20 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总20页 (文件大小：875K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AC373, SN74AC373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
SN54AC373 . . . J OR W PACKAGE
SN74AC373 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
2-V to 6-V V Operation
CC
Inputs Accept Voltages to 6 V
Max t of 9.5 ns at 5 V
pd
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
3-State Noninverting Outputs Drive Bus
Lines Directly
D
Full Parallel Access for Loading
description/ordering information
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
GND
SN54AC373 . . . FK PACKAGE
(TOP VIEW)
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
3
2
1
20 19
18
2D
2Q
3Q
3D
4D
8D
7D
7Q
6Q
6D
4
5
6
7
8
17
16
15
14
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines in bus-organized systems without need for
interface or pullup components.
9 10 11 12 13
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
PDIP − N
Tube
SN74AC373N
SN74AC373N
Tube
SN74AC373DW
SN74AC373DWR
SN74AC373NSR
SN74AC373DBR
SN74AC373PW
SN74AC373PWR
SNJ54AC373J
SOIC − DW
AC373
Tape and reel
Tape and reel
Tape and reel
Tube
SOP − NS
AC373
AC373
−40°C to 85°C
−55°C to 125°C
SSOP − DB
TSSOP − PW
AC373
Tape and reel
Tube
CDIP − J
CFP − W
LCCC − FK
SNJ54AC373J
SNJ54AC373W
SNJ54AC373FK
Tube
SNJ54AC373W
SNJ54AC373FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AC373, SN74AC373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
OE
LE
11
C1
1D
2
1Q
3
1D
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
I
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0 or V > V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC)
Output clamp current, I (V < 0 or V > V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O
O
CC)
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
O
CC
Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
CC
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AC373, SN74AC373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
recommended operating conditions (see Note 3)
SN54AC373
SN74AC373
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
6
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
2.1
2.1
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
3.15
3.85
High-level input voltage
V
V
IH
0.9
1.35
1.65
0.9
1.35
1.65
= 4.5V
= 5.5 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
CC
V
CC
0
0
V
CC
V
CC
V
V
I
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
−12
−24
−24
12
−12
−24
−24
12
= 4.5 V
= 5.5 V
= 3 V
I
High-level output current
Low-level output current
mA
mA
OH
= 4.5 V
= 5.5 V
24
24
I
OL
24
24
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
8
8
ns/V
T
A
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
SN54AC373
SN74AC373
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
2.9
4.4
5.4
TYP
MAX
MIN
2.9
4.4
5.4
2.4
3.7
4.7
MAX
MIN
2.9
MAX
3 V
4.5 V
5.5 V
4.4
I
= −50 μA
OH
5.4
V
V
V
OH
I
I
= −12 mA
= −24 mA
3 V 2.56
4.5 V 3.86
5.5 V 4.86
3 V
2.46
3.76
4.76
OH
OH
0.1
0.1
0.1
0.1
0.5
0.5
0.5
1
0.1
0.1
0.1
0.44
0.44
0.44
1
4.5 V
0.1
0.1
I
OL
= 50 μA
5.5 V
V
OL
I
I
= 12 mA
= 24 mA
3 V
0.36
0.36
0.36
0.1
OL
4.5 V
OL
5.5 V
I
I
V = V or GND
5.5 V
μA
μA
μA
pF
I
CC
I
V
= V or GND
5.5 V
0.25
4
5
2.5
40
OZ
O
CC
I
V = V or GND,
I = 0
O
5.5 V
80
CC
I
CC
C
V = V or GND
5 V
4.5
i
I
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AC373, SN74AC373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V
(unless otherwise noted) (see Figure 1)
T
= 25°C
SN54AC373
SN74AC373
A
UNIT
MIN
5.5
5.5
1
MAX
MIN
6.5
6.5
1
MAX
MIN
6
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
6
1
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V
(unless otherwise noted) (see Figure 1)
T
= 25°C
SN54AC373
SN74AC373
A
UNIT
MIN
4
MAX
MIN
5
MAX
MIN
4.5
4.5
1
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
4
5
1
1
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
10
SN54AC373
SN74AC373
TO
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
13.5
13.0
13.5
12.5
11.5
11.5
12.5
11.5
MIN
1
MAX
16.5
16
MIN
1.5
1.5
1.5
1.5
1
MAX
15
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
9.5
10
1
14.5
15
1
16.5
15
LE
OE
OE
ns
9.5
9
1
14
1
14
13
ns
8.5
10
1
13.5
16
1
13
1
1
14.5
12.5
ns
8
1
13
1
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
T = 25°C
A
SN54AC373
SN74AC373
TO
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
TYP
7
MAX
9.5
9.5
9.5
9.5
8.5
8.5
11
MIN
1
MAX
11.5
11.5
12
MIN
1.5
1.5
1.5
1.5
1
MAX
10.5
10.5
10.5
10.5
9.5
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
7
1
7.5
7
1
LE
OE
OE
ns
1
11
7
1
10.5
10
ns
6.5
8
1
1
9.5
1
13.5
10.5
1
12.5
10
ns
6.5
8.5
1
1
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
C = 50 pF, f = 1 MHz
TYP
40
UNIT
C
Power dissipation capacitance
pF
pd
L
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AC373, SN74AC373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
/t
S1
S1
t
t
Open
PLH PHL
t
500 Ω
Open
From Output
Under Test
/t
2 × V
PLZ PZL
CC
/t
Open
PHZ PZH
C = 50 pF
(see Note A)
L
500 Ω
LOAD CIRCUIT
V
CC
50% V
Timing Input
Data Input
CC
0 V
t
w
t
h
t
3 V
0 V
su
V
CC
50% V
50% V
CC
Input
CC
50% V
50% V
CC
CC
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
V
V
CC
CC
Input
50% V
50% V
50% V
50% V
CC
CC
CC
CC
0 V
0 V
t
t
PLZ
t
t
PZL
PHL
PLH
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
50%V
CC
CC
CC
V
+ 0.3 V
OL
S1 at 2 × V
CC
V
OL
V
OL
(see Note B)
t
t
t
PZH
PHZ
PLH
t
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
V
OH
OL
OH
V
OH
− 0.3 V
Out-of-Phase
Output
50% V
50% V
50% V
CC
CC
CC
≈0 V
V
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
5962-87555012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
87555012A
SNJ54AC
373FK
5962-8755501RA
5962-8755501SA
5962-8755501VRA
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
J
W
J
20
20
20
1
1
TBD
TBD
TBD
A42
A42
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
5962-8755501RA
SNJ54AC373J
5962-8755501SA
SNJ54AC373W
CDIP
20
5962-8755501VR
A
SNV54AC373J
5962-8755501VSA
ACTIVE
CFP
W
20
25
TBD
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8755501VS
A
SNV54AC373W
SN74AC373DBLE
SN74AC373DBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
20
20
Call TI
Call TI
-40 to 85
-40 to 85
2000
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AC373
SN74AC373DW
SN74AC373DWG4
SN74AC373DWR
SN74AC373DWRE4
SN74AC373DWRG4
SN74AC373N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
DW
DW
DW
DW
DW
N
20
20
20
20
20
20
20
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
AC373
25
Green (RoHS
& no Sb/Br)
AC373
2000
2000
2000
20
Green (RoHS
& no Sb/Br)
AC373
Green (RoHS
& no Sb/Br)
AC373
Green (RoHS
& no Sb/Br)
AC373
Pb-Free
(RoHS)
SN74AC373N
SN74AC373N
AC373
SN74AC373NE4
SN74AC373NSR
SN74AC373PW
N
20
Pb-Free
(RoHS)
N / A for Pkg Type
NS
PW
2000
70
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TSSOP
Green (RoHS
& no Sb/Br)
AC373
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
SN74AC373PWLE
SN74AC373PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
20
20
TBD
Call TI
Call TI
-40 to 85
-40 to 85
PW
2000
2000
1
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AC373
SN74AC373PWRG4
SNJ54AC373FK
ACTIVE
ACTIVE
TSSOP
LCCC
PW
FK
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
AC373
TBD
POST-PLATE
-55 to 125
5962-
87555012A
SNJ54AC
373FK
SNJ54AC373J
SNJ54AC373W
ACTIVE
ACTIVE
CDIP
CFP
J
20
20
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-8755501RA
SNJ54AC373J
W
5962-8755501SA
SNJ54AC373W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AC373, SN54AC373-SP, SN74AC373 :
Catalog: SN74AC373, SN54AC373
•
Enhanced Product: SN74AC373-EP, SN74AC373-EP
•
Military: SN54AC373
•
Space: SN54AC373-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AC373DBR
SN74AC373DWR
SN74AC373NSR
SN74AC373PWR
SSOP
SOIC
SO
DB
DW
NS
20
20
20
20
2000
2000
2000
2000
330.0
330.0
330.0
330.0
16.4
24.4
24.4
16.4
8.2
10.8
8.2
7.5
13.0
13.0
7.1
2.5
2.7
2.5
1.6
12.0
12.0
12.0
8.0
16.0
24.0
24.0
16.0
Q1
Q1
Q1
Q1
TSSOP
PW
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74AC373DBR
SN74AC373DWR
SN74AC373NSR
SN74AC373PWR
SSOP
SOIC
SO
DB
DW
NS
20
20
20
20
2000
2000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
45.0
45.0
38.0
TSSOP
PW
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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