SN74ACT08DBRE4_技术文档

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ꢋ ꢌꢄꢍꢎ ꢌꢏꢐ ꢑ ꢒ ꢓꢔꢁ ꢏꢌꢆ ꢏꢕ ꢀꢔ ꢆ ꢔꢖꢑ ꢓꢄꢁ ꢍ ꢗ ꢄꢆꢑ ꢀ

SCAS535C − SEPTEMBER 1995 − REVISED OCTOBER 2003

D

4.5-V to 5.5-V V

Operation

D

Max t of 10 ns at 5 V

pd

Inputs Are TTL-Voltage Compatible

CC

Inputs Accept Voltages to 5.5 V

SN54ACT08 . . . FK PACKAGE

(TOP VIEW)

SN54ACT08 . . . J OR W PACKAGE

SN74ACT08 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

1A

1B

1Y

2A

2B

V

CC

3

2

1

20 19

18

4B

4A

4Y

3B

3A

3Y

4A

NC

4Y

NC

3B

1Y

NC

2A

4

5

6

7

8

17

16

15

14

NC

2B

2Y

GND

9 10 11 12 13

8

NC − No internal connection

description/ordering information

The ’ACT08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean functions

Y = A ꢀ B or Y = A + B in positive logic.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

PDIP − N

SOIC − D

Tube

SN74ACT08N

Tube

SN74ACT08D

ACT08

Tape and reel

Tube

SN74ACT08DR

SN74ACT08NSR

SN74ACT08DBR

SN74ACT08PW

SN74ACT08PWR

SNJ54ACT08J

SNJ54ACT08W

SNJ54ACT08FK

SOP − NS

ACT08

AD08

−40°C to 85°C

SSOP − DB

TSSOP − PW

AD08

Tape and reel

Tube

CDIP − J

CFP − W

LCCC − FK

SNJ54ACT08J

SNJ54ACT08W

SNJ54ACT08FK

Tube

−55°C to 125°C

Tube

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

Y

A

H

L

B

H

X

L

H

L

X

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2003, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃ ꢄꢅ ꢆꢇ ꢈ

ꢋꢌ ꢄ ꢍꢎ ꢌ ꢏꢐ ꢑ ꢒ ꢓꢔ ꢁ ꢏꢌ ꢆ ꢏ ꢕꢀ ꢔ ꢆꢔ ꢖ ꢑꢓ ꢄꢁꢍ ꢗꢄꢆ ꢑꢀ

SCAS535C − SEPTEMBER 1995 − REVISED OCTOBER 2003

logic diagram, each gate (positive logic)

A

Y

B

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

CC

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

I

CC

Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

O

Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

IK

I

CC

Output clamp current, I

(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

OK

O O CC

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Continuous current through V

O

CC

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W

JA

DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W

N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54ACT08

SN74ACT08

UNIT

MIN

4.5

2

MAX

MIN

4.5

2

MAX

V

Supply voltage

5.5

V

CC

IH

IL

High-level input voltage

Low-level input voltage

Input voltage

0.8

V

0

V

0

V

I

CC

Output voltage

V

O

CC

I

High-level output current

Low-level output current

Input transition rise or fall rate

Operating free-air temperature

−24

24

−24

24

8

mA

ns/V

°C

OH

OL

∆t/∆v

8

T

−55

125

−40

85

A

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈ

ꢋ ꢌꢄꢍꢎ ꢌꢏꢐ ꢑ ꢒ ꢓꢔꢁ ꢏꢌꢆ ꢏꢕ ꢀꢔ ꢆ ꢔꢖꢑ ꢓꢄꢁ ꢍ ꢗ ꢄꢆꢑ ꢀ

SCAS535C − SEPTEMBER 1995 − REVISED OCTOBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

T

A

= 25°C

TYP

SN54ACT08

SN74ACT08

PARAMETER

TEST CONDITIONS

V

UNIT

CC

MIN

4.4

MAX

MIN

4.4

MAX

MIN

4.4

MAX

4.5 V

5.5 V

4.5 V

5.5 V

4.5 V

5.5 V

4.5 V

5.5 V

4.49

I

= −50 µA

OH

5.4

5.49

5.4

3.86

4.86

3.7

3.76

4.76

V

OH

= −24 mA

V

OH

4.7

†

I

= −50 mA

3.85

OH

= −75 mA

3.85

OH

0.001

0.1

I

= 50 µA

OL

0.36

0.5

0.44

V

OL

I

= 24 mA

V

0.5

†

I

= 50 mA

1.65

OL

= 75 mA

1.65

"1

20

OL

I

V = V

or GND

or GND,

"0.1

"1

µA

I

CC

V = V

I = 0

O

2

80

CC

I

CC

One input at 3.4 V,

Other inputs at GND or V

‡

DI

CC

5.5 V

0.6

4.5

1.6

1.5

mA

pF

CC

C

VI = V or GND

CC

5 V

i

†

‡

Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.

This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V

.

CC

switching characteristics over recommended operating free-air temperature range,

= 5 V " 0.5 V (unless otherwise noted) (see Figure 1)

V

CC

T

A

= 25°C

TYP

6.5

SN54ACT08

SN74ACT08

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

MIN

1

MAX

MIN

1

MAX

10

MIN

1

MAX

10

t

9

PLH

A or B

Y

ns

1

6.5

1

10

1

10

PHL

operating characteristics, V

= 5 V, T = 25°C

A

CC

PARAMETER

Power dissipation capacitance

TEST CONDITIONS

= 50 pF, f = 1 MHz

L

TYP

UNIT

C

20

pF

pd

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃ ꢄꢅ ꢆꢇ ꢈ

ꢋꢌ ꢄ ꢍꢎ ꢌ ꢏꢐ ꢑ ꢒ ꢓꢔ ꢁ ꢏꢌ ꢆ ꢏ ꢕꢀ ꢔ ꢆꢔ ꢖ ꢑꢓ ꢄꢁꢍ ꢗꢄꢆ ꢑꢀ

SCAS535C − SEPTEMBER 1995 − REVISED OCTOBER 2003

PARAMETER MEASUREMENT INFORMATION

3 V

0 V

Input

(see Note B)

TEST

S1

1.5 V

t

/t

Open

PLH PHL

t

PHL

PLH

2 × V

CC

V

OH

S1

In-Phase

Output

500 Ω

50% V

CC

Open

From Output

Under Test

V

OL

t

PLH

PHL

C

= 50 pF

L

500 Ω

(see Note A)

V

OH

Out-of-Phase

Output

50% V

CC

V

OL

LOAD CIRCUIT

C includes probe and jig capacitance.

L

VOLTAGE WAVEFORMS

NOTES: A.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t v 2.5 ns, t v 2.5 ns.

O

r

f

C. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

18-Jul-2006

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CDIP

CFP

Drawing

5962-89547022A

5962-8954702CA

5962-8954702DA

SN74ACT08D

ACTIVE

FK

J

20

14

1

TBD

POST-PLATE N / A for Pkg Type

A42 SNPB

A42

N / A for Pkg Type

W

D

SOIC

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74ACT08DBLE

SN74ACT08DBR

OBSOLETE

ACTIVE

SSOP

DB

14

TBD

Call TI

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74ACT08DBRE4

SN74ACT08DE4

SN74ACT08DR

ACTIVE

SSOP

SOIC

PDIP

SO

DB

D

14

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74ACT08DRE4

SN74ACT08N

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

N

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN74ACT08NE4

SN74ACT08NSR

SN74ACT08NSRE4

SN74ACT08PW

SN74ACT08PWE4

SN74ACT08PWG4

N

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

NS

PW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74ACT08PWLE

SN74ACT08PWR

OBSOLETE TSSOP

PW

14

TBD

Call TI

ACTIVE

TSSOP

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74ACT08PWRE4

SN74ACT08PWRG4

PW

14

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SNJ54ACT08FK

SNJ54ACT08J

SNJ54ACT08W

ACTIVE

LCCC

CDIP

CFP

FK

J

20

14

1

TBD

POST-PLATE N / A for Pkg Type

A42 SNPB

A42

N / A for Pkg Type

W

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Jul-2006

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

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Applications

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Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

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www.ti.com/automotive

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dsp.ti.com

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Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Low Power Wireless www.ti.com/lpw

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	SN74ACT08DBRE4
厂家：	TEXAS INSTRUMENTS
描述：	QUADRUPLE 2-INPUT POSITIVE-AND GATES 四路2输入正与门逻辑集成电路光电二极管输入元件
文件：	总15页 (文件大小：512K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74ACT08DBRE4 [TI]

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