SN74ACT2235 [TI]
1024 】 9 】 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY; 1024 】 9 】 2异步双向先入先出存储器
| 型号： | SN74ACT2235 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1024 】 9 】 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY |
| 文件： | 总13页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
Independent Asynchronous Inputs and
Outputs
Access Times of 25 ns With a 50-pF Load
Data Rates up to 50 MHz
Low-Power Advanced CMOS Technology
Bidirectional
Fall-Through Times of 22 ns Maximum
High Output Drive for Direct Bus Interface
Dual 1024 by 9 Bits
Package Options Include 44-Pin Plastic
Leaded Chip Carriers (FN) and 64-Pin Thin
Quad Flat (PAG, PM) Packages
Programmable Almost-Full/Almost-Empty
Flag
Empty, Full, and Half-Full Flags
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT2235 is arranged as two 1024 by 9-bit FIFOs for high speed and fast access times.
It processes data at rates up to 50 MHz, with access times of 25 ns in a bit-parallel format.
The SN74ACT2235 consists of bus-transceiver circuits, two 1024 × 9 FIFOs, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable (GAB
and GBA) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are
provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates
the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data.
Figure 2 shows the eight fundamental bus-management functions that can be performed with the
SN74ACT2235.
For more information on this device family, see the application report, 1K × 9 × 2 Asynchronous FIFO
SN74ACT2235, literature number SCAA010.
The SN74ACT2235 is characterized for operation from 0°C to 70°C.
FN PACKAGE
(TOP VIEW)
6 5
4
3
2
1 44 43 42 41 40
39
B2
B3
B4
V
B5
B6
B7
B8
GND
AF/AEB
HFB
A3
A4
7
8
38
37
36
35
34
33
32
31
30
29
V
9
CC
A5
10
11
12
13
14
15
16
17
CC
A6
A7
A8
GND
AF/AEA
HFA
LDCKA
18 19 20 21 22 23 24 25 26 27 28
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
PAG OR PM PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
V
V
NC
V
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CC
A3
2
CC
A4
B3
3
B4
4
CC
GND
GND
A5
GND
GND
5
6
V
7
CC
A6
B5
B6
8
V
9
CC
V
V
10
11
12
13
14
15
16
CC
A7
CC
B7
A8
B8
GND
GND
GND
AF/AEB
HFB
GND
AF/AEA
HFA
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
†
logic symbol
Φ
FIFO
1024 × 9 × 2
SN74ACT2235
44
1
SAB
SBA
1
MODE
0
43
2
GAB
EN1
GBA
EN2
22
21
17
23
RSTA
DAF
Reset A
RESET B
DEF B FLAG
LDCKB
RSTB
DBF
24
28
19
27
20
30
DEF A FLAG
LDCKA
LDCKB
LDCKA
26
18
25
15
UNCKA
FULLA
UNCKB
FULLB
UNCKB
FULL B
UNCKA
FULLA
EMPTYA
AF/AEA
EMPTYA
EMPTYB
EMPTYB
AF/AEB
ALMOST-FULL/
ALMOST-EMPTY A
ALMOST-FULL/
ALMOST-EMPTY A
HALF-FULL B
16
29
HFA
HALF-FULL A
HFB
41
4
0
B0
A0
0
5
40
39
38
37
35
34
33
32
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
A4
A5
A6
A7
A8
6
7
A Data
B Data
8
10
11
12
13
8
8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
logic diagram (positive logic)
SAB
SBA
Φ
FIFO B
1024 × 9
HFB
RSTB
DBF
AF/AEB
EMPTYB
UNCKB
FULLB
LDCKB
B0
Q
D
GBA
One of Nine Channels
To Other Channels
GAB
Φ
FIFO A
1024 × 9
RSTA
DAF
HFA
AF/AEA
EMPTYA
UNCKA
FULLA
LDCKA
Q
D
A0
One of Nine Channels
To Other Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
Terminal Functions
†
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Almost full/almost empty flags. The almost-full/almost-empty A flag (AF/AEA) is defined by the
almost-full/almost-emptyoffset value for FIFO A (X). AF/AEA is high when FIFO A contains X or fewer words
or 1024–X words. AF/AEA is low when FIFO A contains between (X + 1) or (1023 – X) words. The operation
of the almost-full/almost-empty B flag (AF/AEB) is the same as AF/AEA for FIFO B.
AF/AEA
AF/AEB
15
30
O
4–8,
10–13
A0–A8
B0–B8
I/O
I/O
A-data inputs and outputs
B-data inputs and outputs
32–35,
37–41
Define-flag inputs. The high-to-low transition of DAF stores the binary value on A0–A8 as the
almost-full/almost-emptyoffset value for FIFO A (X). The high-to-low transition of DBF stores the binary value
of B0–B8 as the almost-full/almost-empty offset value for FIFO B (Y).
DAF
DBF
21
24
I
EMPTYA
EMPTYB
20
25
Empty flags. EMPTYA and EMPTYB are low when their corresponding memories are empty and high when
they are not empty.
O
O
O
FULLA
FULLB
18
27
Full flags. FULLA and FULLB are low when their corresponding memories are full and high when they are
not full.
HFA
HFB
16
29
Half-full flags. HFA and HFB are high when their corresponding memories contain 512 or more words and
low when they contain 511 or fewer words.
Load clocks. Data on A0–A8 is written into FIFO A on a low-to-high transition of LDCKA. Data on B0–B8 is
written into FIFO B on a low-to-high transition of LDCKB. When the FIFOs are full, LDCKA and LDCKB have
no effect on the data residing in memory.
LDCKA
LDCKB
17
28
I
GAB
GBA
2
43
Output enables. GAB, GBA control the transceiver functions. When GBA is low, A0–A8 are in the
high-impedance state. When GAB is low, B0–B8 are in the high-impedance state.
I
I
RSTA
RSTB
22
23
Reset. A reset is accomplished in each direction by taking RSTA and RSTB low. This sets EMPTYA,
EMPTYB, FULLA, FULLB, and AF/AEB high. Both FIFOs must be reset upon power up.
Select-control inputs. SAB and SBA select whether real-time or stored data is transferred. A low level selects
real-time data and a high level selects stored data. Eight fundamental bus-management functions can be
performed as shown in Figure 2.
SAB
SBA
1
44
I
I
Unload clocks. Data in FIFO A is read to B0–B8 on a low-to-high transition of UNCKB. Data in FIFO B is read
to A0–A8 on a low-to-high transition of UNCKB. When the FIFOs are empty, UNCKA and UNCKB have no
effect on data residing in memory.
UNCKA
UNCKB
19
26
†
Terminals listed are for the FN package.
programming procedure for AF/AEA
The almost-full/almost-empty flags (AF/AEA, AF/AEB) are programmed during each reset cycle. The
almost-full/almost-empty offset value for FIFO A (X) and for FIFO B (Y) is either a user-defined value or the
default values of X = 256 and Y = 256. Below are instructions to program AF/AEA using both methods. AF/AEB
is programmed in the same manner for FIFO B.
user-defined X
Take DAF from high to low. This stores A0–A8 as X.
If RSTA is not already low, take RSTA low.
With DAF held low, take RSTA high. This defines AF/AEA using X.
To retain the current offset for the next reset, keep DAF low.
default X
To redefine AF/AE using the default value of X = 256, hold DAF high during the reset cycle.Figure 1
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RSTA
Don’t Care
DAF
LDCKA
Word
1
Word
2
Word
257
Word
512
Word
768
Word
1024
Don’t Care
A0–A8
X
UNCKA
‡
Word Word Word Word Word Word
Word Word
769 1024
Word
1024
Invalid
Invalid
Word 1
Q0–Q8
2
257
258
513
514
768
EMPTYA
FULLA
HFA
AF/AEA
Set Flag to
Empty + X/Full – X
Set Flag to Empty + 256/
Full – 256 (default)
Empty + 256
Full – 256
Full – 256
Half Full
Empty + 256
Empty
Load X into
Flag Register
Half Full
Full
≤
≤
511)
(0
X
†
‡
Operation of FIFO B is identical to that of FIFO A.
Last valid data stays on outputs when FIFO goes empty due to a read.
†
Figure 1. Timing Diagram for FIFO A
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
FIFO A
Out
FIFO A
Out
In
In
Bus A
Bus B
Bus B
Bus B
Bus A
Bus A
Bus A
Bus A
Bus B
FIFO B
Out
FIFO B
Out
In
In
SAB SBA GAB GBA
SAB SBA GAB GBA
L
X
H
L
X
X
L
L
FIFO A
FIFO A
In
Out
In
Out
Bus A
Bus B
FIFO B
Out
FIFO B
Out
In
In
SAB SBA GAB GBA
SAB SBA GAB GBA
X
L
L
H
H
L
H
H
FIFO A
FIFO A
Out
In
Out
In
Bus A
Bus B
FIFO B
Out
FIFO B
Out
In
In
SAB SBA GAB GBA
SAB SBA GAB GBA
H
X
H
L
L
H
H
H
FIFO A
FIFO A
In Out
In
Out
Bus B
Bus A
Bus B
FIFO B
Out
FIFO B
Out
In
In
SAB SBA GAB GBA
SAB SBA GAB GBA
X
H
L
H
H
H
H
H
Figure 2. Bus-Management Functions
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
SELECT-MODE CONTROL
CONTROL
OPERATION
SAB
L
SBA
L
A BUS
B BUS
Real-time B to A bus
FIFO B to A bus
Real-time A to B bus
Real-time A to B bus
FIFO A to B bus
FIFO A to B bus
L
H
H
L
Real-time B to A bus
FIFO B to A bus
H
H
OUTPUT-ENABLE CONTROL
OPERATION
CONTROL
GAB
GBA
A BUS
B BUS
H
L
H
H
L
A bus enabled
A bus enabled
B bus enabled
Isolation/input to B bus
B bus enabled
H
L
Isolation/input to A bus
L
Isolation/input to A bus Isolation/input to B bus
Figure 2. Bus-Management Functions (Continued)
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V : Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Voltage range applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θ (see Note 1): FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
JA
PAG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
PM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
ACT2235-20
ACT2235-30
ACT2235-40
ACT2235-60
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
CC
V
IH
V
IL
Supply voltage
5.5
5.5
5.5
5.5
V
V
V
High-level input voltage
Low-level input voltage
0.8
–8
–8
16
8
0.8
–8
–8
16
8
0.8
–8
–8
16
8
0.8
–8
–8
16
8
A or B ports
Status flags
A or B ports
Status flags
I
High-level output current
mA
OH
OL
I
Low-level output current
mA
T
A
Operating free-air temperature
0
70
0
70
0
70
0
70
°C
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
= –8 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
I
I
I
2.4
V
OH
CC
CC
CC
CC
CC
OH
OL
OL
Flags
= 8 mA
0.5
0.5
±5
V
OL
I/O ports
= 16 mA
I
I
I
V = V
or 0
µA
µA
µA
mA
pF
pF
I
I
CC
= V or 0
CC
V
±5
OZ
CC
O
‡
V = V
I
– 0.2 V or 0
CC
= 5.5 V,
10
400
1
§
∆I
V
One input at 3.4 V,
f = 1 MHz
Other inputs at V or GND
CC
CC
CC
V = 0,
C
C
4
8
i
I
V
O
= 0,
f = 1 MHz
o
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
I
is tested with outputs open.
CC
This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
timing requirements over recommended operating conditions (unless otherwise noted) (see
Figure 3)
’ACT2235-20 ’ACT2235-30 ’ACT2235-40 ’ACT2235-60
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
16.7
16.7
LDCKA or LDCKB
50
33
25
f
Clock frequency
Pulse duration
MHz
ns
clock
UNCKA or UNCKB
RSTA or RSTB low
LDCKA or LDCKB low
LDCKA or LDCKB high
UNCKA or UNCKB low
UNCKA or UNCKB high
DAF or DBF high
50
33
25
20
8
20
10
10
10
10
10
25
14
14
14
14
10
25
20
20
20
20
10
8
t
w
8
8
10
Data before LDCKA
or LDCKB↑
4
5
7
4
5
7
5
5
7
5
5
7
Define AF/AE:
D0–D8 before DAF or DBF↓
Define AF/AE: DAF or DBF↓
before RSTA or RSTB↑
t
su
Setup time
ns
Define AF/AE (default):
DAF or DBF high before
RSTA or RSTB↑
5
5
5
5
RSTA or RSTB inactive (high)
before LDCKA or LDCKB↑
5
1
0
5
1
0
5
2
0
5
2
0
Data after LDCKA or LDCKB↑
Define AF/AE: D0–D8
after DAF or DBF↓
Define AF/AE: DAF or DBF low
after RSTA or RSTB↑
t
h
Hold time
ns
0
0
0
0
0
0
0
0
Define AF/AE (default):
DAF or DBF high after
RSTA or RSTB↑
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 3)
L
’ACT2235-20
’ACT2235-30 ’ACT2235-40 ’ACT2235-60
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
MIN TYP
MAX
MIN
33
MAX
MIN
25
MAX
MIN
16.7
16.7
MAX
LDCK
UNCK
50
50
f
MHz
max
33
25
LDCK↑,
LDCKB↑
8
22
25
15
8
12
4
22
25
15
8
12
4
24
35
17
8
12
4
26
45
19
t
B or A
ns
ns
pd
UNCKA↑,
UNCKB↑
12
4
17
LDCK↑,
LDCKB↑
EMPTYA,
EMPTYB
t
PLH
UNCKA↑,
UNCKB↑
2
2
4
17
18
15
2
2
4
17
18
15
2
2
4
19
20
17
2
2
4
21
22
19
EMPTYA,
EMPTYB
RSTA↓, RSTB↓
t
t
ns
ns
PHL
LDCK↑,
LDCKB↑
FULLA, FULLB
UNCKA↑,
UNCKB↑
4
2
2
15
15
15
4
2
2
15
15
15
4
2
2
17
17
17
4
2
2
19
19
19
FULLA, FULLB
FULLA, FULLB
RSTA↓, RSTB↓
AF/AEA,
AF/AEB
PLH
LDCK↑,
LDCKB↑
HFA, HFB
HFA, HFB
B or A
2
4
15
18
2
4
15
18
2
4
17
20
2
4
19
22
UNCKA↑,
UNCKB↑
t
t
ns
ns
PHL
RSTA↓, RSTB↓
1
1
1
15
11
11
1
1
1
15
11
11
1
1
1
17
12
12
1
1
1
19
14
14
‡
SAB or SBA
A or B
LDCK↑,
LDCKB↑
2
2
18
18
2
2
18
18
2
2
20
20
2
2
22
22
pd
AF/AEA,
AF/AEB
UNCKA↑,
UNCKB↑
t
t
GBA or GAB
GBA or GAB
A or B
A or B
2
1
11
9
2
1
11
9
2
1
13
11
2
1
15
13
ns
ns
en
dis
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 5 MHz
L
TYP
71
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per 1K bits
C
pF
pd
57
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
7 V
PARAMETER
S1
S1
t
Open
Closed
Open
PZH
t
t
t
en
dis
pd
500 Ω
t
PZL
t
PHZ
From Output
Under Test
Test
Point
t
Closed
Open
PLZ
PLH
PHL
t
t
C
= 50 pF
L
Open
(see Note A)
500 Ω
t
w
LOAD CIRCUIT
3 V
0 V
Input
1.5 V
1.5 V
3 V
0 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
3 V
0 V
3 V
Data
Input
1.5 V
1.5 V
Output
Control
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
≈ 3.5 V
Output
Waveform 1
S1 at 7 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
OL
+ 0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
Output
Waveform 2
S1 at Open
OH
V
V
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
≈ 0 V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTE A: C includes probe and jig capacitance.
L
Figure 3. Load Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148E – DECEMBER 1990 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS
POWER-DISSIPATION CAPACITANCE
PROPAGATION DELAY TIME
vs
vs
SUPPLY VOLTAGE
LOAD CAPACITANCE
typ + 2
typ + 1
typ
typ + 8
typ + 6
typ + 4
typ + 2
typ
V
= 5 V
CC
f = 5 MHz
V
= 5 V
= 25°C
= 500 Ω
CC
i
T
A
T
= 25°C
A
R
L
typ – 1
typ – 2
typ – 3
typ – 2
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
0
50
C
100
150
200
250
300
V
CC
– Supply Voltage – V
– Load Capacitance – pF
L
Figure 4
Figure 5
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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