SN74ACT2236-60PM [TI]
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| 型号： | SN74ACT2236-60PM |
| 厂家： | 
TEXAS INSTRUMENTS |
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SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
D Independent Asynchronous Inputs and
D Access Times of 25 ns With a 50-pF Load
D Data Rates From 0 to 50 MHz
Outputs
D Low-Power Advanced CMOS Technology
D Fall-Through Times of 23 ns Max
D High Output Drive for Direct Bus Interface
D 3-State Outputs
D Bidirectional
D 1024 Words by 9 Bits Each
D Programmable Almost-Full/Almost-Empty
D Available in 44-Pin PLCC (FN) Package
Flag
D Empty, Full, and Half-Full Flags
FN PACKAGE
(TOP VIEW)
6
5
4
3
2 1 44 43 42 41 40
B2
B3
B4
V
B5
B6
B7
B8
GND
AF/AEB
HFB
A3
A4
7
39
38
37
36
35
34
33
32
31
30
29
8
V
9
CC
A5
10
11
12
13
14
15
16
17
CC
A6
A7
A8
GND
AF/AEA
HFA
LDCKA
18 19 20 21 22 23 24 25 26 27 28
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT2236 is arranged as two 1024 by 9-bit FIFOs for high speed and fast access times.
It processes data at rates from 0 to 50 MHz with access times of 25 ns in a bit-parallel format.
The SN74ACT2236 consists of bus-transceiver circuits, two 1024 × 9 FIFOs, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable OE and
DIR inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are
provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates
the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data.
Figure 1 shows the five fundamental bus-management functions that can be performed with the SN74ACT2236.
The SN74ACT2236 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the application report 1K ꢀ 9 ꢀ 2 Asynchronous FIFOs
SN74ACT2235 and SN74ACT2236 in the 1996 High-Performance FIFO Memories Designer’s Handbook,
literature number SCAA012A.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 1995, Texas Instruments Incorporated
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ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢇ ꢈꢉ
ꢊ
ꢋ
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ꢃ
×
ꢌ
×
ꢇ
ꢄ ꢀꢍꢁ ꢅ ꢎ ꢏꢐꢁ ꢐꢑ ꢀ ꢒꢓ ꢔ ꢓ ꢏꢕꢅ ꢆꢓ ꢐ ꢁꢄ ꢖ ꢗꢓ ꢏꢀ ꢆꢘꢓ ꢁꢙ ꢗ ꢓꢏꢀ ꢆꢘꢐ ꢑꢆ ꢚ ꢕꢚ ꢐꢏꢍ
SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
†
logic symbol
Φ
FIFO
1024 × 9 × 2
SN74ACT2236
44
SAB
SBA
OE
1
MODE
1
0
43
3EN1 [BA]
3EN2 [AB]
2
DIR
RSTA
G3
23
24
28
19
27
20
22
RESET B
RSTB
RESET A
DEF A FLAG
21
17
26
18
DEF B FLAG
LDCKB
DBF
DAF
LDCKB
UNCKB
FULLB
EMPTYB
LDCKA
UNCKA
FILLA
LDCKA
UNCKB
FULL B
UNCKA
FULLA
25
15
EMPTYB
EMPTYA
EMPTYA
AF/AEA
30
29
ALMOST-FULL/
ALMOST-FULL/
ALMOST-EMPTY A ALMOST-EMPTY B
AF/AEB
HFB
16
HFA
HALF-FULL A
HALF-FULL B
41
4
1
0
2
0
B0
A0
5
40
39
38
37
35
34
33
32
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
A4
A5
A6
A7
A8
6
7
A Data
B Data
8
10
11
12
13
8
8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
logic diagram (positive logic)
SAB
SBA
Φ
HFB
AF/AEB
EMPTYB
UNCKB
RSTB
FIFO B
1024 × 9
DBF
FULLB
LDCKB
Q
D
B0
One of Nine Channels
To Other Channels
DIR
OE
Φ
RSTA
DAF
HFA
FIFO A
1024 × 9
AF/AEA
EMPTYA
UNCKA
FULLA
LDCKA
Q
A0
D
One of Nine Channels
To Other Channels
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Almost full/almost empty flags. The almost-full/almost-empty A flag (AF/AEA) is defined by the
almost-full/almost-empty offset value for FIFO A (X). AF/AEA is high when FIFO A contains X or less
words or 1024−X words. AF/AEA is low when FIFO A contains between X + 1 or 1023 − X words.
The operation of the almost-full/almost-empty B flag (AF/AEB) is the same as AF/AEA for FIFO B.
AF/AEA,
AF/AEB
15, 30
O
A0−A8
B0−B8
4−8, 10−13
I/O
I/O
A data inputs and outputs
B data inputs and outputs
32−35,
37−41
Define-flag inputs. The high-to-low transition of DAF stores the binary value on A0−A8 as the
almost-full/almost-empty offset value for FIFO A (X). The high-to-low transition of DBF stores the
binary value of B0−B8 as the almost-full/almost-empty offset value for FIFO B (Y).
DAF, DBF
21, 24
I
EMPTYA,
EMPTYB
Empty flags. EMPTYA and EMPTYB are low when their corresponding memories are empty and high
when they are not empty.
20, 25
18, 27
16, 29
O
O
O
FULLA,
FULLB
Full flags. FULLA and FULLB are low when their corresponding memories are full and high when they
are not full.
Half-full flags. HFA and HFB are high when their corresponding memories contain 512 or more
words, and low when they contain 511 or less words.
HFA, HFB
Load clocks. Data on A0−A8 is written into FIFO A on a low-to-high transition of LDCKA. Data on
B0−B8 is written into FIFO B on a low-to-high transition of LDCKB. When the FIFOs are full, LDCKA
and LDCKB have no effect on the data residing in memory.
LDCKA,
LDCKB
17, 28
2, 43
I
I
Enable inputs. DIR and OE control the transceiver functions. When OE is high, both A0−A8 and
B0−B8 are in the high-impedance state and can be used as inputs. With OE low and DIR high, the
A bus is in the high-impedance state and B bus is active. When both OE and DIR are low, the A bus
is active and the B bus is in the high-impedance state.
DIR, OE
Reset. A reset is accomplished in each direction by taking RSTA and RSTB low. This sets EMPTYA,
EMPTYB, FULLA, FULLB, and AF/AEB high. Both FIFOs must be reset upon power up.
RSTA, RSTB
SAB, SBA
22, 23
1, 44
I
I
Select-control inputs. SAB and SBA select whether real-time or stored data is transferred. A low level
selects real-time data, and a high level selects stored data. Eight fundamental bus-management
functions can be performed as shown in Figure 1.
Unload clocks. Data in FIFO A is read to B0−B8 on a low-to-high transition of UNCKB. Data in FIFO
B is read to A0−A8 on a low-to-high transition of UNCKB. When the FIFOs are empty, UNCKA and
UNCKB have no effect on data residing in memory.
UNCKA,
UNCKB
19, 26
I
programming procedure for AF/AEA
The almost-full/almost-empty flags (AF/AEA, AF/AEB) are programmed during each reset cycle. The
almost-full/almost-empty offset value FIFO A (X) and for FIFO B (Y) are either a user-defined value or the default
values of X = 256 and Y = 256. Below are instructions to program AF/AEA using both methods. AF/AEB is
programmed in the same manner for FIFO B.
user-defined X
Take DAF from high to low. This stores A0 thru A8 as X.
If RSTA is not already low, take RSTA high.
With DAF held low, take RSTA high. This defines the AF/AEA flag using X.
To retain the current offset for the next reset, keep DAF low.
default X
To redefine the AF/AE flag using the default value of X = 256, hold DAF high during the reset cycle.
4
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢄ ꢀꢍꢁ ꢅ ꢎ ꢏꢐꢁ ꢐꢑ ꢀ ꢒꢓ ꢔ ꢓ ꢏꢕꢅ ꢆꢓ ꢐ ꢁꢄ ꢖ ꢗꢓ ꢏꢀ ꢆꢘꢓ ꢁꢙ ꢗ ꢓꢏꢀ ꢆꢘꢐ ꢑꢆ ꢚ ꢕꢚ ꢐꢏꢍ
SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
FIFO A
Out
FIFO A
In
In
Out
Bus A
Bus B
Bus A
Bus B
FIFO B
Out
FIFO B
Out
In
In
SAB SBA DIR OE
SAB SBA DIR OE
L
X
H
L
X
X
X
H
FIFO A
Out
FIFO A
In
In
Out
Bus A
Bus B
Bus A
Bus B
FIFO B
Out
FIFO B
Out
In
In
SAB SBA DIR OE
SAB SBA DIR OE
H
X
H
L
X
L
L
L
FIFO A
In
Out
Bus A
Bus B
FIFO B
Out
In
SAB SBA DIR OE
X
H
L
L
Figure 1. Bus-Management Functions
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
SELECT-MODE CONTROL TABLE
OPERATION
CONTROL
SAB
L
SBA
L
A BUS
B BUS
Real-time A to B bus
Real-time B to A bus
FIFO B to A bus
Real-time B to A bus
FIFO B to A bus
L
H
Real-time A to B bus
FIFO A to B bus
FIFO A to B bus
H
L
H
H
OUTPUT-ENABLE CONTROL TABLE
OPERATION
CONTROL
DIR
X
OE
H
A BUS
Input
B BUS
Input
Input
L
L
Output
Input
H
L
Output
Figure 1. Bus-Management Functions (Continued)
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage: Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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×
ꢌ
×
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SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
recommended operating conditions
′ACT2236-20
′ACT2236-30
′ACT2236-40
′ACT2236-60
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
CC
V
IH
V
IL
Supply voltage
5.5
5.5
5.5
5.5
V
V
V
High-level input voltage
Low-level input voltage
0.8
−8
−8
16
8
0.8
0.8
−8
−8
16
8
0.8
−8
A or B ports
Status flags
A or B ports
Status flags
−8
−8
16
8
High-level output cur-
rent
I
I
f
mA
mA
OH
−8
16
Low-level output current
Clock frequency
OL
8
LDCKA or LDCKB
50
50
33
33
25
25
16.7
16.7
MHz
clock
UNCKA or UNCKB
RSTA or RSTB low
20
8
20
10
10
10
10
10
25
14
14
14
14
10
25
20
20
20
20
10
LDCKA or LDCKB low
LDCKA or LDCKB high
UNCKA or UNCKB low
UNCKA or UNCKB high
DAF or DBF high
8
t
w
Pulse duration
ns
8
8
10
Data before LDCKA or
LDCKB↑
4
5
4
5
5
5
5
5
Define AF/AE: D0−D8
before DAF or DBF↓
Define AF/AE: DAF or
DBF↓ before RSTA or
RSTB↑
7
5
5
7
5
5
7
5
5
7
5
5
t
su
Setup time
ns
Define AF/AE (default):
DAF or DBF high before
RSTA or RSTB↑
RSTA or RSTB inactive
(high) before LDCKA or
LDCKB↑
Data after LDCKA or
LDCKB↑
1
0
1
0
2
0
2
0
Define AF/AE: D0−D8
after DAF or DBF↓
Define AF/AE: DAF or
DBF low after RSTA or
RSTB↑
t
h
Hold time
ns
0
0
0
0
Define AF/AE (default):
DAF or DBF high after
RSTA or RSTB↑
0
0
0
0
0
0
0
0
T
A
Operating free-air temperature
70
70
70
70
°C
8
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ꢀ
ꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢇꢈ ꢉ
ꢃ × ꢌ ×
ꢊ
ꢋ
ꢇ
ꢚ
ꢇ
ꢍ
ꢄ
ꢀ
ꢍ
ꢁ
ꢅ
ꢎ
ꢏ
ꢐꢁ
ꢐ
ꢑ
ꢀ
ꢒ
ꢓ
ꢔ
ꢓ
ꢏꢕ
ꢅ
ꢆ
ꢓ
ꢐ
ꢁ
ꢄꢖ
ꢗ
ꢓꢏ
ꢀ
ꢆꢘ
ꢓ
ꢁꢙ
ꢗ
ꢓꢏ
ꢀ
ꢆꢘ
ꢐ
ꢑꢆ
ꢕꢚ
ꢐ
ꢏ
SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
= − 8 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
I
I
I
2.4
V
OH
CC
CC
CC
CC
CC
OH
OL
OL
Flags
= 8 mA
0.5
0.5
5
V
OL
I/O ports
= 16 mA
I
I
I
V = V
CC
or 0
or 0
µA
µA
µA
I
I
V
= V
O CC
5
OZ
CC
‡
V = V
I CC
− 0.2 V or 0
10
400
2
DIR, OE
§
V
CC
= 5.5 V,
One input at 3.4 V,
Other inputs at V
CC
or GND
mA
∆I
CC
Other inputs
1
C
C
V = 0,
f = 1 MHz
f = 1 MHz
4
8
pF
pF
i
I
V
O
= 0,
o
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
I
tested with outputs open.
CC
This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figures 4 and 5)
L
′ACT2236-20
′ACT2236-30
′ACT2236-40
′ACT2236-60
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
MIN TYP
MAX
MIN
33
33
8
MAX
MIN
25
25
8
MAX
MIN
16.7
16.7
8
MAX
LDCK
UNCK
50
50
8
f
t
t
MHz
ns
max
LDCK↑, LDCKB↑
B or A
B or A
23
25
23
25
25
35
27
45
pd
UNCKA↑,
UNCKB↑
10
4
17
10
4
10
4
10
4
ns
pd
EMPTYA,
EMPTYB
t
LDCK↑, LDCKB↑
15
17
15
17
17
19
19
21
ns
ns
PLH
PHL
UNCKA↑,
UNCKB↑
EMPTYA,
EMPTYB
t
2
2
2
2
EMPTYA,
EMPTYB
t
t
t
2
4
4
18
15
15
2
4
4
18
15
15
2
4
4
20
17
17
2
4
4
22
19
19
ns
ns
ns
RSTA↓, RSTB↓
PHL
PHL
PLH
LDCK↑, LDCKB↑
FULLA, FULLB
UNCKA↑,
UNCKB↑
FULLA, FULLB
t
t
t
RSTA↓, RSTB↓
RSTA↓, RSTB↓
LDCK↑, LDCKB↑
FULLA, FULLB
AF/AEA, AF/AEB
HFA, HFB
2
2
2
15
15
15
2
2
2
15
15
15
2
2
2
17
17
17
2
2
2
19
19
19
ns
ns
ns
PLH
PLH
PLH
UNCKA↑,
UNCKB↑
t
HFA, HFB
4
19
4
19
4
21
4
23
ns
PHL
t
t
t
t
RSTA↓, RSTB↓
HFA, HFB
B or A
1
1
1
2
15
11
11
19
1
1
1
2
15
11
11
19
1
1
1
2
17
13
13
21
1
1
1
2
19
15
15
23
ns
ns
ns
ns
PHL
¶
SAB or SBA
A or B
pd
B or A
pd
LDCK↑, LDCKB↑ AF/AEA, AF/AEB
pd
UNCKA↑,
t
pd
AF/AEA, AF/AEB
UNCKB↑
2
19
2
19
2
23
2
23
ns
t
t
DIR, OE
DIR, OE
A or B
A or B
2
1
12
10
2
1
12
10
2
1
14
12
2
1
16
14
ns
ns
en
dis
†
¶
All typical values are at V
CC
= 5 V, T = 25°C.
A
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
ꢃ
×
ꢌ
×
ꢇ
ꢄ ꢀꢍꢁ ꢅ ꢎ ꢏꢐꢁ ꢐꢑ ꢀ ꢒꢓ ꢔ ꢓ ꢏꢕꢅ ꢆꢓ ꢐ ꢁꢄ ꢖ ꢗꢓ ꢏꢀ ꢆꢘꢓ ꢁꢙ ꢗ ꢓꢏꢀ ꢆꢘꢐ ꢑꢆ ꢚ ꢕꢚ ꢐꢏꢍ
SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 5 MHz
TYP
71
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per 1K bits
C
pF
pd
L
57
TYPICAL CHARACTERISTICS
POWER DISSIPATION CAPACITANCE
PROPAGATION DELAY TIME
vs
vs
SUPPLY VOLTAGE
LOAD CAPACITANCE
typ + 2
typ + 1
typ
typ + 8
V
= 5 V
V
T
R
= 5 V
= 25°C
= 500 Ω
CC
CC
A
L
f = 5 MHz
i
T
= 25°C
A
typ + 6
typ + 4
typ + 2
typ − 1
typ
typ − 2
typ − 3
typ − 2
0
50
100
150
200
250
300
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
C
− Load Capacitance − pF
V
CC
− Supply Voltage − V
L
Figure 2
Figure 3
calculating power dissipation
The maximum power dissipation (P ) can be calculated by:
T
2
2
P = V
× [I
+ (N × ∆I
× dc)] + Σ(C × V
× f ) + Σ(C × V
× f )
T
CC
CC
CC
pd
CC
i
L
CC
o
where:
I
N
∆I
dc
C
C
= power-down I
= number of inputs driven by a TTL device
= increase in supply current
= duty cycle of inputs at a TTL high level of 3.4 V
= power dissipation capacitance
= output capacitive load
maximum
CC
CC
CC
pd
L
f
f
= data input frequency
= data output frequency
i
o
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢇꢈ ꢉ
ꢃ × ꢌ ×
ꢊ
ꢋ
ꢇ
ꢚ
ꢇ
ꢍ
ꢄꢀ
ꢍ
ꢁꢅ
ꢎ
ꢏ
ꢐ
ꢁ
ꢐꢑ
ꢀ
ꢒꢓ
ꢔꢓ
ꢏꢕ
ꢅ
ꢆ
ꢓ
ꢐ
ꢁ
ꢄꢖ
ꢗ
ꢓꢏ
ꢀ
ꢆ
ꢘ
ꢓ
ꢁꢙ
ꢗ
ꢓꢏ
ꢀ
ꢆ
ꢘ
ꢐ
ꢑꢆ
ꢕꢚ
ꢐ
ꢏ
SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
3 V
Input
1.5 V
From Output
Under Test
GND
t
pd
t
R
L
= 500 Ω
C = 50 pF
L
pd
3 V
0 V
Output
1.5 V
LOAD CIRCUIT
TOTEM-POLE OUTPUTS
Figure 4. Standard CMOS Outputs (All Flags)
3 V
0 V
1.5 V
1.5 V
Input
Output
Output
V
CC
t
t
PZL
PLZ
≈ V
CC
S1
S2
0.3 V
1.5 V
R
L
From Output
Under Test
V
OL
t
PHZ
t
PZH
C
L
V
OH
1.5 V
0.3 V
≈ 0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
†
PARAMETER
R
C
S1
S2
L
L
t
Open
Closed
Open
Closed
Open
Closed
Open
Closed
Open
Open
PZH
t
500 Ω
50 pF
en
t
PZL
t
PHZ
t
500 Ω
50 pF
50 pF
dis
t
PLZ
t
or t
−
pd
t
†
Includes probe and test-fixture capacitance
Figure 5. 3-State Outputs (A0ā−āA8, B0ā−āB8)
11
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
PLCC
PLCC
PLCC
PLCC
Drawing
SN74ACT2236-20FN
SN74ACT2236-30FN
SN74ACT2236-40FN
SN74ACT2236-60FN
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
FN
44
44
44
44
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
FN
FN
FN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
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