SN74ACT373-EP [TI]
OCTAL D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS; 八路D型透明锁存器带3态输出
| 型号： | SN74ACT373-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS |
| 文件： | 总9页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢂꢇ ꢈꢉ ꢊ
ꢋ ꢅꢆꢄꢌ ꢍꢈꢆ ꢎꢊ ꢉ ꢆ ꢏꢄꢁꢀ ꢊꢄꢏꢉ ꢁꢆ ꢌꢄꢆꢅ ꢐ
ꢑ ꢒꢆ ꢐ ꢇ ꢈꢀꢆꢄꢆ ꢉ ꢋ ꢓꢆ ꢊ ꢓꢆꢀ
SCAS726 − OCTOBER 2003
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
D
Inputs Accept Voltages to 5.5 V
Max t of 10 ns at 5 V
pd
Inputs Are TTL-Voltage Compatible
D
D
Extended Temperature Performance of
−55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
D
D
D
Enhanced Product-Change Notification
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
†
Qualification Pedigree
4.5-V to 5.5-V V
Operation
CC
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
GND
description/ordering information
This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow
the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
in bus-organized systems without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
T
A
PACKAGE
−55°C to 125°C
SOIC − DW
Tape and reel
SN74ACT373MDWREP
SACT373MEP
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢂ ꢇꢈꢉ ꢊ
ꢋꢅ ꢆꢄ ꢌ ꢍ ꢈꢆ ꢎꢊꢉ ꢆꢏ ꢄꢁ ꢀꢊꢄꢏ ꢉꢁ ꢆ ꢌꢄꢆꢅ ꢐ
ꢑꢒ ꢆ ꢐ ꢇ ꢈꢀꢆꢄꢆ ꢉ ꢋꢓꢆ ꢊꢓ ꢆꢀ
SCAS726 − OCTOBER 2003
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
OE
LE
11
C1
1D
2
1Q
3
1D
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC)
O
Output clamp current, I
(V < 0 or V > V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O
CC)
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Package thermal impedance, θ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
JA
Storage temperature range, T (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. Long-term high−temperature storage and/or extended use at maximum recommended operating conditions may result in a
reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢂꢇ ꢈꢉ ꢊ
ꢋ ꢅꢆꢄꢌ ꢍꢈꢆ ꢎꢊ ꢉ ꢆ ꢏꢄꢁꢀ ꢊꢄꢏꢉ ꢁꢆ ꢌꢄꢆꢅ ꢐ
ꢑ ꢒꢆ ꢐ ꢇ ꢈꢀꢆꢄꢆ ꢉ ꢋ ꢓꢆ ꢊꢓ ꢆꢀ
SCAS726 − OCTOBER 2003
recommended operating conditions (see Note 4)
MIN
4.5
2
MAX
UNIT
V
V
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
V
0.8
V
0
0
V
V
V
I
CC
Output voltage
V
O
CC
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−24
24
mA
mA
ns/V
°C
OH
OL
I
∆t/∆v
8
T
−55
125
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
4.4
MAX
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
4.49
4.4
5.4
3.7
4.7
I
I
I
I
= −50 µA
= −24 mA
= 50 µA
OH
OH
OL
OL
5.4
5.49
V
V
V
OH
3.86
4.86
0.1
0.1
0.1
0.1
0.44
0.44
5
V
OL
0.36
0.36
0.25
0.1
= 24 mA
I
I
I
V
= V
O CC
or GND
µA
µA
µA
OZ
V = V
or GND
or GND,
1
I
I
CC
V = V
I = 0
O
4
80
CC
I
CC
One input at 3.4 V,
Other inputs at GND or V
†
∆I
CC
5.5 V
0.6
4.5
1.5
mA
pF
CC
C
V = V or GND
I CC
5 V
i
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V
.
CC
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
A
MIN
MAX
UNIT
MIN
7
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
8.5
8.5
1
ns
ns
ns
7
0
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢂ ꢇꢈꢉ ꢊ
ꢋꢅ ꢆꢄ ꢌ ꢍ ꢈꢆ ꢎꢊꢉ ꢆꢏ ꢄꢁ ꢀꢊꢄꢏ ꢉꢁ ꢆ ꢌꢄꢆꢅ ꢐ
ꢑꢒ ꢆ ꢐ ꢇ ꢈꢀꢆꢄꢆ ꢉ ꢋꢓꢆ ꢊꢓ ꢆꢀ
SCAS726 − OCTOBER 2003
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
8.5
8
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
ns
MIN
2.5
2
MAX
10
10
11
t
t
t
t
t
t
t
t
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
12.5
12.5
12.5
11.5
11.5
11
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
2.5
2
8.5
8
LE
OE
OE
ns
10
9.5
9
2
8
ns
2
7.5
9
2.5
1.5
11
14
ns
7.5
8.5
11
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
C
40
pF
pd
L
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢂꢇ ꢈꢉ ꢊ
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ꢑ ꢒꢆ ꢐ ꢇ ꢈꢀꢆꢄꢆ ꢉ ꢋ ꢓꢆ ꢊꢓ ꢆꢀ
SCAS726 − OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
Open
2 × V
S1
Open
500 Ω
t
t
/t
PLH PHL
/t
From Output
Under Test
t
PLZ PZL
CC
Open
/t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
3 V
0 V
1.5 V
Timing Input
Data Input
LOAD CIRCUIT
t
h
t
su
3 V
0 V
1.5 V
1.5 V
t
w
3 V
VOLTAGE WAVEFORMS
1.5 V
1.5 V
Input
Output
Control
(low-level
enabling)
0 V
3 V
0 V
VOLTAGE WAVEFORMS
1.5 V
1.5 V
t
t
PZL
PLZ
Output
Waveform 1
≈V
3 V
CC
Input
50% V
1.5 V
1.5 V
CC
CC
S1 at 2 × V
(see Note B)
CC
V
V
+ 0.3 V
OL
V
OL
0 V
t
t
t
t
PZH
PHZ
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
OH
Output
− 0.3 V
OH
50% V
CC
50% V
50% V
CC
V
≈0 V
OL
VOLTAGE WAVEFORMS
includes probe and jig capacitance.
VOLTAGE WAVEFORMS
NOTES: A.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN74ACT373MDWREP
V62/04619-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74ACT373-EP :
Catalog: SN74ACT373
Military: SN54ACT373
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications
•
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74ACT373MDWREP
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 20
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
SN74ACT373MDWREP
2000
Pack Materials-Page 2
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