SN74ACT7203L-25DV [TI]
2KX9 OTHER FIFO, 25ns, PDSO28;
| 型号： | SN74ACT7203L-25DV |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2KX9 OTHER FIFO, 25ns, PDSO28 时钟 先进先出芯片 光电二极管 内存集成电路 |
| 文件： | 总22页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
DV OR NP PACKAGE
Reads and Writes Can Be Asynchronous
or Coincident
(TOP VIEW)
Organization:
W
D8
D3
D2
D1
D0
XI
V
CC
D4
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
– SN74ACT7203L – 2048 × 9
– SN74ACT7204L – 4096 × 9
– SN74ACT7205L – 8192 × 9
– SN74ACT7206L – 16383 × 9
D5
D6
D7
FL/RT
RS
Fast Data Access Times of 15 ns
Read and Write Frequencies up to 40 MHz
Bit-Width and Word-Depth Expansion
Fully Compatible With the IDT7203/7204
Retransmit Capability
FF
Q0
EF
XO/HF
Q1 10
19 Q7
Q2
Q3
Q6
Q5
11
12
18
17
Empty, Full, and Half-Full Flags
TTL-Compatible Inputs
Q8 13
16 Q4
15
GND 14
R
Available in 28-Pin Plastic DIP (NP), Plastic
Small-Outline (DV), and 32-Pin Plastic
J-Leaded Chip-Carrier (RJ) Packages
RJ PACKAGE
(TOP VIEW)
description
These devices are constructed with dual-port
SRAM and have internal write and read address
counters to provide data throughput on a first-in,
first-out (FIFO) basis. Write and read operations
are independent and can be asynchronous or
coincident. Empty and full status flags prevent
underflow and overflow of memory, and
depth-expansion logic allows combining the
storage cells of two or more devices into one
FIFO. Word-width expansion is also possible.
4
3
2
1
32 31 30
29
5
6
7
8
9
D2
D1
D0
XI
D6
D7
NC
FL/RT
RS
28
27
26
25
FF
Q0 10
24 EF
Q1
NC
Q2
XO/HF
Q7
Q6
11
12
13
23
22
21
Data is loaded into memory by the write-enable
(W) input and unloaded by the read-enable (R)
input. Read and write cycle times of 25 ns
(40 MHz) are possible with data access times of
15 ns.
14 15 16 17 18 19 20
NC – No internal connection
These devices are particularly suited for providing a data channel between two buses operating at
asynchronous rates. Applications include use as rate buffers from analog-to-digital converters in
data-acquisition systems, temporary storage elements between buses and magnetic or optical memories, and
queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus
a parity bit or packet-framing information. The read pointer can be reset independently of the write pointer for
retransmitting previously read data when a device is not used in depth expansion.
The SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, and SN74ACT7206L are characterized for operation
from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
†
SN74ACT7203L logic symbol
FIFO 2048 × 9
Φ
SN74ACT7203L
22
2,4 CT = 0 (RST)
RS
W
8
1
2(CT = 2047) G6
4(CT = 2047) G6
(CT = 2048) G6
FF
6 (WR PNTR)
6 C1
G2
7
21
20
(EXPAND)
XI
(CT = 0) G5
EF
23
(1ST LOAD)
2,4 (REXMIT)
FL/RT
XO/HF
(EXPAND)
CT > 1024
15
5 (RD PNTR)
R
5EN3
G4
(CT = WR PNTR – RD PNTR)
6
9
10
11
12
16
17
18
19
13
D0
D1
D2
D3
D4
D5
D6
D7
D8
1D
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
5
4
3
27
26
25
24
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
†
SN74ACT7204L logic symbol
FIFO 4096 × 9
Φ
SN74ACT7204L
22
1
2,4 CT = 0 (RST)
RS
W
8
2(CT = 4095) G6
4(CT = 4095) G6
(CT = 4096) G6
FF
6 (WR PNTR)
6 C1
G2
7
21
20
(EXPAND)
XI
(CT = 0) G5
EF
23
(1ST LOAD)
2,4 (REXMIT)
FL/RT
XO/HF
(EXPAND)
CT > 2048
15
5 (RD PNTR)
R
5EN3
G4
(CT = WR PNTR – RD PNTR)
6
9
10
11
12
16
17
18
19
13
D0
D1
D2
D3
D4
D5
D6
D7
D8
1D
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
5
4
3
27
26
25
24
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
†
SN74ACT7205L logic symbol
FIFO 8192 × 9
Φ
SN74ACT7205L
22
2,4 CT = 0 (RST)
RS
W
8
1
2(CT = 8191) G6
4(CT = 8191) G6
(CT = 8192) G6
FF
6 (WR PNTR)
6 C1
G2
7
21
20
(EXPAND)
XI
(CT = 0) G5
EF
23
(1ST LOAD)
2,4 (REXMIT)
FL/RT
XO/HF
(EXPAND)
CT > 4096
15
5 (RD PNTR)
R
5EN3
G4
(CT = WR PNTR – RD PNTR)
6
9
10
11
12
16
17
18
19
13
D0
D1
D2
D3
D4
D5
D6
D7
D8
1D
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
5
4
3
27
26
25
24
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
†
SN74ACT7206L logic symbol
FIFO 16384 × 9
Φ
SN74ACT7206L
22
1
2,4 CT = 0 (RST)
RS
W
8
2(CT = 16383) G6
4(CT = 16383) G6
(CT = 16384) G6
FF
6 (WR PNTR)
6 C1
G2
7
21
20
(EXPAND)
XI
(CT = 0) G5
EF
23
(1ST LOAD)
2,4 (REXMIT)
FL/RT
XO/HF
(EXPAND)
CT > 8192
15
5 (RD PNTR)
R
5EN3
G4
(CT = WR PNTR – RD PNTR)
6
9
10
11
12
16
17
18
19
13
D0
D1
D2
D3
D4
D5
D6
D7
D8
1D
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
5
4
3
27
26
25
24
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
functional block diagram
9
D0–D8
W
Location 1
Location 2
2048 × 9 or
4096 × 9 or
8192 × 9 or
16384 × 9
Write
Control
Write
Pointer
Read
Pointer
†
RAM
•
9
•
Q0–Q8
RS
Reset
Logic
FL/RT
Status-
Flag
Logic
FF
EF
Read
Control
R
Expansion
Logic
XO/HF
XI
†
2048 × 9 for SN74ACT7203L; 4096 × 9 for SN74ACT7204L; 8192 × 9 for SN74ACT7205L; 16384 × 9 for SN74ACT7206L
RESET AND RETRANSMIT FUNCTION TABLE
(single-device depth; single-or multiple-device width)
INPUTS
INTERNAL TO DEVICE
OUTPUTS
FUNCTION
RS
L
FL/RT
XI
L
READ POINTER
WRITE POINTER
Location zero
Unchanged
EF
L
FF
H
XO/HF
X
L
Location zero
Location zero
H
X
X
Reset device
Retransmit
Read/write
H
L
X
X
H
H
L
Increment if EF high Increment if FF high
X
X
RESET AND FIRST-LOAD FUNCTION TABLE
(multiple-device depth; single-or multiple-device width)
INPUTS
INTERNAL TO DEVICE
OUTPUTS
EF FF
FUNCTION
RS
L
FL/RT
XI
READ POINTER
WRITE POINTER
Location zero
Location zero
X
‡
L
H
X
Location zero
Location zero
X
L
L
H
H
X
Reset first device
Reset all other devices
Read/write
‡
‡
L
H
X
‡
XI is connected to XO/HF of the previous device in the daisy chain (see Figure 15).
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
D0–D8
I
Data inputs
Empty-flag output. EF is low when the read pointer is equal to the write pointer, inhibiting any operation initiated by a read
cycle. When the FIFO is empty, a data word can be read automatically at Q0–Q8 by holding R low when loading the data
word with a low-level pulse on W.
EF
O
O
Full-flag output. FF is low when the write pointer is one location less than the read pointer, indicating that the device is
full and inhibiting any operation initiated by a write cycle. FF goes low when the number of writes after reset exceeds the
number of reads by 2048 for the SN74ACT7203L, 4096 for the SN74ACT7204L, 8192 for the SN74ACT7205L, and
16384 for the SN74ACT7206L. When the FIFO is full, a data word can be written automatically into memory by holding
W low while reading out another data word with a low-level pulse on R.
FF
First-load/retransmitinput. FL/RT performs two separate functions. When cascading two or more devices for word-depth
expansion, FL/RT is tied to ground on the first device in the daisy chain to indicate that it is the first device loaded and
unloaded; it is tied high on all other devices in the depth-expansion chain.
A device is not used in depth expansion when its expansion-in (XI) input is tied to ground. In that case, FL/RT acts as
a retransmit enable. A retransmit operation is initiated when FL/RT is pulsed low. This sets the internal read pointer to
the first location and does not affect the write pointer. R and W must be at a high logic level during the low-level FL/RT
retransmit pulse. Retransmit should be used only when less than 2048/4096 writes are performed between resets;
otherwise, an attempt to retransmit can cause the loss of unread data. The retransmit function can affect XO/HF
depending on the relative locations of the read and write pointers.
FL/RT
I
GND
Ground
Q0–Q8
O
I
Data outputs. Q0–Q8 are in the high-impedance state when R is high or the FIFO is empty.
Read-enable input. A read cycle begins on the falling edge of R if EF is high. This activates Q0–Q8 and shifts the next
data value to this bus. The data outputs return to the high-impedance state as R goes high. As the last stored word is
read by the falling edge of R, EF transitions low but Q0–Q8 remain active until R returns high. When the FIFO is empty,
the internal read pointer is unchanged by a pulse on R.
R
Reset input. A reset is performed by taking RS low. This initializes the internal read and write pointers to the first location
and sets EF low, FF high, and HF high. Both R and W must be held high for a reset during the window shown in Figure 7.
A reset is required after power up before a write operation can take place.
RS
I
V
CC
Supply voltage
Write-enable input. A write cycle begins on the falling edge of W if FF is high. The value on D0–D8 is stored in memory
as W returns high. When the FIFO is full, FF is low inhibiting W from performing any operation on the device.
W
I
I
Expansion-in input. XI performs two functions. XI is tied to ground to indicate that the device is not used in depth
expansion.When the device is used in depth expansion, XI is connected to the expansion-out (XO) output of the previous
device in the depth-expansion chain.
XI
Expansion-out/half-full-flagoutput. XO/HF performs two functions. When the device is not used in depth expansion (i.e.,
when XI is tied to ground), XO/HF indicates when half the memory locations are filled. After half of the memory is filled,
the falling edge on W for the next write operation drives XO/HF low. XO/HF remains low until a rising edge of R reduces
the number of words stored to exactly half of the total memory.
XO/HF
O
Whenthedeviceisusedindepthexpansion, XO/HFis connected to XI of the next device in the daisy chain. XO/HFdrives
the daisy chain by sending a pulse to the next device when the previous device reaches the last memory location.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range (any input), V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
O
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
Supply voltage
4.5
2.6
2
5
5.5
V
CC
XI
High-level input voltage
V
IH
Other inputs
Low-level input voltage
0.8
–2
8
V
IL
I
I
High-level output current
Low-level output current
Operating free-air temperature
mA
mA
°C
OH
OL
T
A
0
70
electrical characteristics over recommended operating free-air temperature range, V
(unless otherwise noted)
= 5.5 V
CC
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
I
I
= – 2 mA
= 8 mA
2.4
OH
CC
OH
0.4
±10
±10
1
V
OL
CC
OL
I
= V
,
R ≥ V
R ≥ V
µA
µA
µA
mA
mA
mA
pF
OZH
OZL
I
O
O
CC
= 0.4 V,
IH
IH
I
I
V = 0 to 5.5 V
I
–1
‡
I
f
= 20 MHz
120
12
CC1
CC2
CC3
clock
R, W, RS, and FL/RT at V
‡
‡
I
IH
I
V = V
I
– 0.2 V
2
CC
§
C
C
V = 0,
I
T
= 25°C,
T = 25°C,
A
f = 1 MHz
f = 1 MHz
10
i
A
§
V
O
= 0,
10
pF
o
‡
§
I
= supply current; I
= standby current; I
= power-down current. I
measurements are made with outputs open (only capacitive
CC
CC1
loading).
CC2
CC3
This parameter is sampled and not 100% tested.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
′ACT7203L-15
′ACT7204L-15
′ACT7205L-15
′ACT7206L-15
′ACT7203L-25
′ACT7204L-25
′ACT7205L-25
′ACT7206L-25
′ACT7203L-50
′ACT7204L-50
′ACT7205L-50
′ACT7206L-50
FIGURE
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Clock frequency, R or W
Cycle time, read
40
28.5
15
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clock
1(a)
1(b)
7
25
25
25
25
15
15
10
10
15
15
15
10
11
15
15
10
10
0
35
35
35
35
25
25
10
10
25
25
25
10
15
25
25
10
10
0
65
65
65
65
50
50
15
15
50
50
50
10
30
50
50
15
15
5
c(R)
Cycle time, write
c(W)
Cycle time, reset
c(RS)
c(RT)
Cycle time, retransmit
Pulse duration, R low
Pulse duration, W low
Pulse duration, R high
Pulse duration, W high
Pulse duration, FL/RT low
Pulse duration, RS low
Pulse duration, XI low
Pulse duration, XI high
Setup time, data before W↑
Setup time, R and W high before FL/RT↑
4
1(a)
1(b)
1(a)
1(b)
4
w(RL)
w(WL)
w(RH)
w(WH)
w(RT)
w(RS)
w(XIL)
w(XIH)
su(D)
7
10
10
1(b), 6
4
†
su(RT)
su(RS)
su(XI-R)
su(XI-W)
h(D)
†
Setup time, R and W high before RS↑
Setup time, XI low before R↓
Setup time, XI low before W↓
Hold time, data after W↑
7
10
10
1(b), 6
5, 11
6, 12
4
Hold time, R low after EF↑
15
15
10
10
25
25
10
10
50
50
15
15
h(E-R)
h(F-W)
h(RT)
h(RS)
Hold time, W low after FF↑
Hold time, R and W high after FL/RT↑
Hold time, R and W high after RS↑
7
†
These values are characterized but not currently tested.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 13)
′ACT7203L-15
′ACT7204L-15
′ACT7205L-15
′ACT7206L-15
′ACT7203L-25
′ACT7204L-25
′ACT7205L-25
′ACT7206L-25
′ACT7203L-50
′ACT7204L-50
′ACT7205L-50
′ACT7206L-50
PARAMETER
FIGURE
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
t
t
1(a), 3, 5
1(a)
15
25
50
ns
ns
Access time, R↓ or EF↑ to data out valid
Valid time, data out valid after R↑
Enable time, R↓ to Q outputs at
a
5
5
5
5
5
v(RH)
t
t
t
t
t
1(a)
5
10
ns
ns
ns
ns
ns
en(R-QX)
en(W-QX)
dis(R)
†
low impedance
Enable time, W↑ to Q outputs at
†‡
low impedance
5
5
15
Disable time, R↑ to Q outputs at
1(a)
6
15
15
15
18
25
25
30
45
45
†
high impedance
Pulse duration, FF high in
automatic-write mode
w(FH)
Pulse duration, EF high in
automatic-read mode
5
w(EH)
t
t
t
2
2, 6, 12
7
15
15
25
25
25
35
45
45
65
ns
ns
ns
Propagation delay time, W↓ to FF low
Propagation delay time, R↑ to FF high
Propagation delay time, RS↓ to FF high
pd(W-F)
pd(R-F)
pd(RS-F)
Propagation delay time, RS↓ to XO/HF
high
t
7
25
35
65
ns
pd(RS-HF)
t
t
t
3, 5, 11
15
15
25
25
25
35
45
45
65
ns
ns
ns
Propagation delay time, W↑ to EF high
Propagation delay time, R↓ to EF low
Propagation delay time, RS↓ to EF low
pd(W-E)
pd(R-E)
pd(RS-E)
3
7
Propagation delay time, W↓ to XO/HF
low
t
t
t
t
t
t
t
8
8
9
9
9
9
4
25
25
15
15
15
15
25
35
35
25
25
25
25
35
65
65
50
50
50
50
65
ns
ns
ns
ns
ns
ns
ns
pd(W-HF)
pd(R-HF)
Propagation delay time, R↑ to XO/HF
high
Propagation delay time, R↓ to XO/HF
low
pd(R-XOL)
pd(W-XOL)
pd(R-XOH)
pd(W-XOH)
pd(RT-FL)
Propagation delay time, W↓ to XO/HF
low
Propagation delay time, R↑ to XO/HF
high
Propagation delay time, W↑ to XO/HF
high
Propagation delay time,
FL/RT↓ to HF, EF, FF valid
†
‡
These values are characterized but not currently tested.
Only applies when data is automatically read
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
t
t
w(RL)
c(R)
t
w(RH)
t
a
t
a
R
t
t
t
dis(R)
en(R-QX)
w(RH)
Q0 –Q8
Valid
Valid
(a) READ
t
c(W)
t
t
w(WH)
w(WL)
W
t
t
h(D)
su(D)
D0 –D8
Valid
Valid
(b) WRITE
Figure 1. Asynchronous Waveforms
Ignored
First Read
Write
Last Write
Additional Reads
R
W
t
t
pd(R-F)
pd(W-F)
FF
Figure 2. Full-Flag Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
Ignored
Read
Last Read
First Write
Additional Writes
W
R
t
t
pd(R-E)
pd(W-E)
EF
t
a
D0 –D8
Valid
Figure 3. Empty-Flag Waveforms
t
c(RT)
t
w(RT)
FL/RT
W, R
t
t
h(RT)
su(RT)
XO/HF, EF, FF
Valid Flag
t
pd(RT-FL)
NOTE A: The EF, FF, and XO/HF status flags are valid after completion of the retransmit cycle.
Figure 4. Retransmit Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
W
R
t
h(E-R)
EF
t
w(EH)
t
t
a
pd(W-E)
t
en(W-QX)
Q0 –Q8
Valid
Figure 5. Automatic-Read Waveforms
R
t
h(F-W)
W
t
pd(R-F)
FF
t
w(FH)
t
h(D)
D0 –D8
Valid
t
su(D)
Figure 6. Automatic-Write Waveforms
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
t
c(RS)
t
w(RS)
RS
W
R
EF
t
t
h(RS)
su(RS)
t
pd(RS-E)
XO/HF, FF
t
pd(RS-HF)
t
pd(RS-F)
Figure 7. Master-Reset Waveforms
Half Full or Less
More Than Half Full
Half Full or Less
W
R
t
pd(R-HF)
t
pd(W-HF)
XO/HF
Figure 8. Half-Full Flag Waveforms
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
Write to Last
Physical Location
W
R
Read From Last
Physical Location
t
pd(W-XOH)
t
t
pd(W-XOL)
pd(R-XOH)
t
pd(R-XOL)
XO/HF
Figure 9. Expansion-Out Waveforms
t
t
w(XIH)
w(XIL)
XI
t
su(XI-W)
Write to First
Physical Location
W
R
t
su(XI-R)
Read From First
Physical Location
Figure 10. Expansion-In Waveforms
W
t
pd(W-E)
EF
R
t
h(E-R)
Figure 11. Minimum Timing for an Empty-Flag Coincident-Read Pulse
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
R
t
pd(R-F)
FF
W
t
h(F-W)
Figure 12. Minimum Timing for a Full-Flag Coincident-Write Pulse
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
5 V
1100 Ω
From Output
Under Test
30 pF
(see Note A)
680 Ω
LOAD CIRCUIT
3 V
3 V
Timing
Input
High-Level
Input
1.5 V
1.5 V
1.5 V
1.5 V
GND
GND
3 V
t
h
t
t
su
w
Data,
Enable
Input
3 V
1.5 V
1.5 V
Low-Level
Input
1.5 V
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
GND
t
PLZ
t
PZL
≈ 3 V
3 V
Low-Level
Output
1.5 V
1.5 V
1.5 V
Input
V
V
OL
GND
t
PZH
t
t
pd
pd
OH
High-Level
Output
V
V
OH
1.5 V
In-Phase
Output
1.5 V
1.5 V
≈ 0 V
OL
t
PHZ
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTE A: Includes probe and jig capacitance
Figure 13. Load Circuit and Voltage Waveforms
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
APPLICATION INFORMATION
Combining two or more devices to create one FIFO with a greater number of memory bits is accomplished in two
different ways. Width expansion increases the number of bits in each word by connecting FIFOs with the same depth
in parallel. Depth expansion uses the built-in expansion logic to daisy-chain two or more devices for applications
requiring more than 2048, 4096, 8192, or 16384 words of storage. Width expansion and depth expansion can beused
together.
width expansion
Word-width expansion is achieved by connecting the corresponding input control to multiple devices with the
same depth. Status flags (EF, FF, and HF) can be monitored from any one device. Figure 14 shows two FIFOs
in a width-expansion configuration. Both devices have their expansion-in (XI) inputs tied to ground. This
disables the depth-expansion function of the device, allowing the first-load/retransmit (FL/RT) input to function
as a retransmit (RT) input and the expansion-out/half-full (XO/HF) output to function as a half-full (HF) flag.
depth expansion
The SN74ACT7203L/7204L/7205L/7206L are easily expanded in depth. Figure 15 shows the connections
used to depth expand three SN74ACT7203L/7204L/7205L/7206L devices. Any depth can be attained by
adding additional devices to the chain. The SN74ACT7203L/7204L/7205L/7206L operate in depth expansion
under the following conditions:
The first device in the chain is designated by connecting FL to ground.
All other devices have their FL inputs at a high logic level.
XO of each device must be connected to XI of the next device.
External logic is needed to generate a composite FF and EF. All FF outputs must be ORed together,
and all EF outputs must be ORed together.
RT and HF functions are not available in the depth-expanded configuration.
combined depth and width expansion
Both expansion techniques can be used together to increase depth and width. This is done by creating
depth-expanded units and then connecting them in a width-expanded configuration (see Figure 16).
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
APPLICATION INFORMATION
SN74ACT7203L/7204L/7205L/7206L
D0 – D8
9
Q0 – Q8
9
18
18
Q0–Q18
EF
D0–D8 Q0–Q8
W
D0–D18
W
R
R
EF
RT
RS
FF
HF
FL/RT
RS
FF
XO/HF
XI
SN74ACT7203L/7204L/7205L/7206L
D9 – D18
9
Q9 – Q18
9
D0–D8 Q0–Q8
W
R
EF
EF
FF
HF
FL/RT
RS
FF
XO/HF
XI
Figure 14. Word-Width Expansion: 2048/4096 Words × 18 Bits
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
APPLICATION INFORMATION
SN74ACT7203L/7204L/7205L/7206L
9
9
9
9
D0–D8
Q0–Q8
D0–D8 Q0–Q8
W
W
R
R
XO/HF
RS
EF
FF
RS
FL/RT
XI
SN74ACT7203L/7204L/7205L/7206L
9
9
D0–D8 Q0–Q8
W
EF
FF
R
XO/HF
RS
EF
FF
FL/RT
V
CC
XI
SN74ACT7203L/7204L/7205L/7206L
9
9
D0–D8 Q0–Q8
W
R
XO/HF
RS
EF
FF
FL/RT
XI
Figure 15. Word-Depth Expansion: 6144/12288/24576/49152 Words × 9 Bits
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L
2048 × 9, 4096 × 9, 8192 × 9, 16384 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS226A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
APPLICATION INFORMATION
Q0–Q17
18
Q0–Q26
27
9
9
9
Q0–Q8
Q9–Q17
Q18–Q26
′ACT7203L
or
′ACT7204L
or
′ACT7203L
or
′ACT7204L
or
′ACT7203L
or
′ACT7204L
or
′ACT7205L
or
′ACT7206L
Depth-
Expansion
Block
′ACT7205L
or
′ACT7206L
Depth-
Expansion
Block
′ACT7205L
or
′ACT7206L
Depth-
Expansion
Block
W, R, RS
9
9
9
D0–D8
18
D9–D26
D9–D17
D18–D26
27
D0–D26
Figure 16. Word-Depth Plus Word-Width Expansion
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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