SN74ACT7802-25FNR [TI]
1KX18 OTHER FIFO, 30ns, PQCC68, GREEN, PLASTIC, LCC-68;
| 型号： | SN74ACT7802-25FNR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1KX18 OTHER FIFO, 30ns, PQCC68, GREEN, PLASTIC, LCC-68 先进先出芯片 |
| 文件： | 总16页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
Member of the Texas Instruments
Widebus Family
Fast Access Times of 30 ns With a 50-pF
Load
Low-Power Advanced CMOS Technology
Fall-Through Time Is 20 ns Typical
Data Rates up to 40 MHz
Load and Unload Clocks Can Be
Asynchronous or Coincident
High-Output Drive for Direct Bus Interface
3-State Outputs
1024 Words × 18 Bits
Programmable Almost-Full/Almost-Empty
Flag
Package Options Include 68-Pin (FN) and
80-Pin Thin Quad Flat (PN) Packages
Empty, Full, and Half-Full Flags
FN PACKAGE
(TOP VIEW)
9
8
7
6
5 4 3 2 1 68 67 66 65 64 63 62 61
D14
D13
D12
D11
D10
D9
V
CC
10
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Q14
Q13
GND
Q12
Q11
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
V
V
CC
CC
D8
GND
D7
D6
D5
D4
D3
D2
D1
Q10
Q9
GND
Q8
Q7
V
CC
Q6
Q5
GND
Q4
D0
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
PN PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC
GND
GND
Q16
V
V
NC
Q3
Q2
GND
Q1
Q0
V
HF
FULL
GND
GND
AF/AE
V
NC
CC
CC
2
3
4
5
Q17
6
V
CC
7
EMPTY
GND
8
9
V
CC
CC
10
11
12
13
14
15
16
17
18
19
20
RESET
OE
NC
NC
UNCK
GND
D17
D16
D15
NC
CC
NC
LDCK
GND
NC
NC
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC – No internal connection
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7802 is a 1024-word by 18-bit FIFO for high-speed applications. It processes data
in a bit-parallel format at rates up to 40 MHz and access times of 30 ns.
Data is written into the FIFO memory on a low-to-high transition on the load-clock (LDCK) input and is read out
on a low-to-high transition on the unload-clock (UNCK) input. The memory is full when the number of words
clocked in exceeds by 1024 the number of words clocked out. When the memory is full, LDCK has no effect on
the data in the memory; when the memory is empty, UNCK has no effect.
A low level on the reset (RESET) input resets the FIFO internal clock stack pointers and sets full (FULL) high,
almost full/almost empty (AF/AE) high, half full (HF) low, and empty (EMPTY) low. The Q outputs are not reset
to any specific logic level. The FIFO must be reset upon power up. The Q outputs are noninverting and are in
the high-impedance state when the output-enable (OE) input is low.
When writing to the FIFO after a reset pulse or when the FIFO is empty, the first active transition on LDCK drives
EMPTY high and causes the first word written to the FIFO to appear on the Q outputs. An active transition on
UNCK is not required to read the first word written to the FIFO. Each subsequent read from the FIFO requires
an active transition on UNCK.
The SN74ACT7802 can be cascaded in the word-width direction but not in the word-depth direction.
The SN74ACT7802 is characterized for operation from 0°C to 70°C.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
†
logic symbol
Φ
FIFO 1024 × 18
SN74ACT7802
1
RESET
LDCK
UNCK
RESET
LDCK
UNCK
EN1
29
5
35
FULL
HALF FULL
FULL
HF
36
33
66
2
ALMOST FULL/EMPTY
EMPTY
AF/AE
EMPTY
OE
27
DAF
DEF ALMOST FULL
26
25
24
23
22
21
20
19
17
15
14
13
12
11
10
9
38
39
41
42
44
46
47
49
50
52
53
55
56
58
59
61
63
64
D0
D1
0
0
Q0
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
D8
Q8
Data
1
Data
D9
Q9
D10
D11
D12
D13
D14
D15
D16
D17
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
8
7
17
17
†
ThissymbolisinaccordancewithANSI/IEEEStd91-1984andIECPublication617-12.
Pin numbers shown are for the FN package.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
functional block diagram
OE
D0–D17
Location 1
Location 2
Write
Control
Read
Pointer
LDCK
UNCK
1024 × 18 RAM
Write
Pointer
Read
Control
Location 1023
Location 1024
Q0–Q17
Reset
Logic
RESET
DAF
Status-
Flag
Logic
EMPTY
FULL
HF
AF/AE
Terminal Functions
TERMINAL
I/O
DESCRIPTION
†
NAME
NO.
Almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AE, or the default value
of 256 can be used for the almost-empty almost-full offset (X). AF/AE is high when memory contains X
or fewer words or (1024 – X) or more words. AF/AE is high after reset.
AF/AE
33
O
Define almost-full flag. The high-to-low transition of DAF stores the binary value of data inputs as the
AF/AE offset value (X). With DAF held low, a low pulse on RESET defines AF/AE using X.
27
I
I
DAF
7–15, 17,
19–26
D0–D17
18-bit data input port
EMPTY
FULL
HF
66
35
36
29
2
O
O
O
I
Empty flag. EMPTY is low when the FIFO is empty. A FIFO reset also causes EMPTY to go low.
Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.
Half-full flag. HF is high when the FIFO memory contains 512 or more words. HF is low after reset.
Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high.
Output enable. When OE is low, the data outputs are in the high-impedance state.
LDCK
OE
I
38–39, 41–42,
44, 46–47,
49–50, 52–53,
55–56, 58–59,
61, 63–64
Q0–Q17
O
18-bit data-output port
1
5
I
I
Reset. A low level on RESET resets the FIFO and drives AF/AE and FULL high and HF and EMPTY low.
Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.
RESET
UNCK
†
Terminal numbers listed are for the FN package.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
offset value values for AF/AE
The FIFO memory status is monitored by the FULL, EMPTY, HF, and AF/AE flags. The FULL output is low when
the memory is full; the EMPTY output is low when the memory is empty. The HF output is high when the memory
contains 512 or more words and low when it contains fewer than 512 words. The level of the AF/AE flag is
determined by both the number of words in the FIFO and a user-definable offset X. AF/AE is high when the FIFO
is almost full or almost empty, i.e., when it contains X or fewer words or (1024 – X) or more words. The AF/AE
offsetvalueiseitheruser-definedorthedefaultvalueof256;itisprogrammedduringeachresetcycleasfollows:
user-defined X:
Take DAF from high to low.
If RESET is not already low, take RESET low.
With DAF held low, take RESET high. This defines the AF/AE flag using X.
default X:
To redefine the AF/AE flag using the default value of X = 256, hold DAF high during the reset cycle.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RESET
DAF
Don’t Care
LDCK
D0–D17
UNCK
W1
W2
WX+1
W512
W1024–X
W1024
X
Don’t Care
OE
Q0–Q17
W1
W2
WX+2 W513
W514 W1024–X
W1025–X W1023
W1024
WX+1
EMPTY
AF/AE
HF
FULL
Define the AF/AE Offset Value (X)
Using the Data on D0 – D8
Define the AF/AE Offset Value (X)
Using the Default Value of 256
Figure 1. Write, Read, and Flag Timing Reference
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Package thermal impedance, θ (see Note 1): FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
JA
PN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62°C/W
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
’ACT7802-25 ’ACT7802-40 ’ACT7802-60
UNIT
MIN
MAX
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
Supply voltage
4.5
2
5.5
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.8
–8
16
70
0.8
–8
16
70
0.8
–8
16
70
V
IL
I
I
mA
mA
°C
OH
OL
T
A
0
0
0
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
= –8 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
I
I
2.4
OH
CC
CC
CC
CC
OH
= 16 mA
0.5
±5
V
OL
OL
I
I
I
V = V
or 0
µA
µA
µA
mA
pF
pF
I
I
CC
= V or 0
CC
V
±5
OZ
CC
O
§
V = V
I
– 0.2 V or 0
CC
= 5.5 V,
400
1
§
∆I
CC
V
One input at 3.4 V,
f = 1 MHz
Other inputs at V or GND
CC
CC
V = 0,
C
C
4
8
i
I
V
O
= 0,
f = 1 MHz
o
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
tested with outputs open
I
CC
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
timing requirements over recommended operating conditions (see Figures 1 and 2)
’ACT7802-25 ’ACT7802-40 ’ACT7802-60
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
40
25
16.7
MHz
clock
LDCK high or low
10
10
10
20
4
14
14
10
25
5
20
20
10
25
5
UNCK high or low
ns
ns
ns
w
DAF high
RESET low
D0–D7 before LDCK↑
RESET inactive (high) before LDCK↑
Define AF/AE: D0–D8 before DAF↓
Define AF/AE: DAF↓ before RESET↑
Define AF/AE (default): DAF high before RESET↑
D0–D7 after LDCK↑
5
5
5
t
su
Setup time
Hold time
5
5
5
7
7
7
5
5
5
1
2
2
Define AF/AE: D0–D8 after DAF↓
Define AF/AE: DAF low after RESET↑
Define AF/AE (default): DAF high after RESET↑
0
0
0
t
h
0
0
0
0
0
0
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (see Figures 1 and 2)
L
’ACT7802-25
’ACT7802-40 ’ACT7802-60
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
†
MIN TYP
MAX
MIN
25
8
MAX
MIN
16.7
8
MAX
f
t
LDCK or UNCK
LDCK↑
UNCK↑
UNCK↑
LDCK↑
UNCK↑
RESET↓
LDCK↑
UNCK↑
RESET↓
LDCK↑
UNCK↑
RESET↓
LDCK↑
UNCK↑
RESET↓
OE
40
max
8
20
21
30
30
35
35
45
45
Any Q
pd
12
12
12
‡
t
t
Any Q
ns
ns
pd
4
2
2
4
4
2
2
2
2
2
2
2
2
2
18
18
18
18
17
17
20
20
17
18
18
17
12
14
4
2
2
4
4
2
2
2
2
2
2
2
2
2
20
20
20
20
19
19
22
22
19
20
20
19
14
16
4
2
2
4
4
2
2
2
2
2
2
2
2
2
22
22
22
22
21
21
24
24
21
22
22
21
16
18
EMPTY
PLH
EMPTY
FULL
t
ns
PHL
t
t
t
t
ns
ns
ns
ns
FULL
PLH
AF/AE
pd
AF/AE
HF
PLH
PHL
HF
t
t
Any Q
Any Q
ns
ns
en
OE
dis
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
This parameter is measured with C = 30 pF (see Figure 3).
L
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 5 MHz
TYP
UNIT
C
Power dissipation capacitance per channel
C
65
pF
pd
L
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATIONFigure 1
7 V
PARAMETER
S1
S1
t
Open
Closed
Open
Closed
Open
Open
PZH
t
t
t
en
dis
pd
500 Ω
t
PZL
t
PHZ
From Output
Under Test
Test
Point
t
PLZ
PLH
PHL
t
t
C
= 50 pF
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
3 V
0 V
Input
1.5 V
1.5 V
3 V
0 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
3 V
0 V
3 V
0 V
Data
Input
1.5 V
1.5 V
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
≈ 3.5 V
Output
Waveform 1
S1 at 7 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
OL
+ 0.3 V
V
OL
t
PHZ
t
t
PHL
PLH
t
PZH
V
Output
Waveform 2
S1 at Open
OH
V
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
≈ 0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTE A: C includes probe and jig capacitance.
L
Figure 2. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS
POWER DISSIPATION CAPACITANCE
PROPAGATION DELAY TIME
vs
vs
SUPPLY VOLTAGE
LOAD CAPACITANCE
typ + 3
typ + 2
typ + 1
typ
typ + 8
typ + 6
typ + 4
typ + 2
f = 5 MHz
V
R
T
A
= 5 V
= 500 Ω
= 25°C
CC
L
T
C
= 25°C
= 50 pF
A
L
typ – 1
typ – 2
typ – 3
typ
typ – 2
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
0
50
100
150
200
250
300
C
– Load Capacitance – pF
V
CC
– Supply Voltage – V
L
Figure 3
Figure 4
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
APPLICATION INFORMATION
SN74ACT7802
LDCK
FULL
LDCK
FULL
UNCK
UNCK
EMPTY
EMPTY
OE
OE
D0–D17
Q0–Q17
D18–D35
Q18–Q35
SN74ACT7802
LDCK
UNCK
EMPTY
FULL
OE
D0–D17
D0–D17
Q0–Q17
Q0–Q17
Figure 5. Word-Width Expansion: 1024 × 36 Bit
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
1M7802-60PNG4
SN74ACT7802-25FN
SN74ACT7802-25PN
SN74ACT7802-40FN
SN74ACT7802-40PN
SN74ACT7802-60PN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
PLCC
LQFP
PLCC
LQFP
LQFP
PN
FN
PN
FN
PN
PN
80
68
80
68
80
80
119
18
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
Purchase Samples
Purchase Samples
Purchase Samples
Purchase Samples
119
18
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
119
119
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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28-Aug-2010
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Addendum-Page 2
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
M
0,08
41
61
40
0,13 NOM
80
21
1
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
0,05 MIN
0°–7°
14,20
SQ
13,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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