SN74AHC123APWRG4 [TI]
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS;
| 型号： | SN74AHC123APWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS 时钟 输入元件 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总23页 (文件大小：638K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢄ ꢊ ꢀꢁꢋ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢄ
ꢌꢍꢄ ꢎ ꢏꢐ ꢑꢏꢒ ꢓ ꢓꢐ ꢏꢄꢔꢎ ꢐ ꢕ ꢖꢁ ꢖꢀ ꢑꢄꢔꢎ ꢐ ꢕ ꢍꢎꢑ ꢒꢗ ꢒ ꢔꢏ ꢄꢑꢖ ꢏꢀ
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
SN54AHC123A . . . J OR W PACKAGE
SN74AHC123A . . . D, DB, DGV, N, OR PW PACKAGE
(TOP VIEW)
D
D
Operating Range 2-V to 5.5-V V
CC
Schmitt-Trigger Circuitry On A, B, and CLR
Inputs for Slow Input Transition Rates
1A
1B
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
D
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
1R /C
ext ext
1CLR
1Q
1C
1Q
ext
D
D
D
D
Retriggerable for Very Long Output Pulses
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset On Outputs
2Q
12 2Q
11
10
9
2C
2CLR
2B
ext
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
2R /C
ext ext
GND
2A
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54AHC123A . . . FK PACKAGE
(TOP VIEW)
− 1000-V Charged-Device Model (C101)
description/ordering information
The ’AHC123A devices are dual retriggerable
monostable multivibrators designed for 2-V to
3
2
1 20 19
18
1C
1Q
1CLR
1Q
5.5-V V
operation.
4
5
6
7
8
ext
CC
17
16
These edge-triggered multivibrators feature
output pulse-duration control by three methods. In
NC
NC
15 2Q
14
9 10 11 12 13
2Q
the first method, the A input is low, and the B input
goes high. In the second method, the B input is
high, and the A input goes low. In the third method,
the A input is low, the B input is high, and the clear
(CLR) input goes high.
2CLR
2C
ext
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube
SN74AHC123AN
SN74AHC123AN
Tube
SN74AHC123AD
AHC123A
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tube
SN74AHC123ADR
SN74AHC123ADBR
SN74AHC123APWR
SN74AHC123ADGVR
SNJ54AHC123AJ
SNJ54AHC123AW
SNJ54AHC123AFK
−40°C to 85°C
SSOP − DB
TSSOP − PW
TVSOP − DGV
CDIP − J
HA123A
HA123A
HA123A
SNJ54AHC123AJ
CFP − W
Tube
SNJ54AHC123AW
SNJ54AHC123AFK
−55°C to 125°C
LCCC − FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2005, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢌ ꢍꢄꢎ ꢏ ꢐꢑ ꢏ ꢒꢓꢓ ꢐ ꢏꢄꢔ ꢎꢐ ꢕꢖ ꢁꢖ ꢀꢑꢄꢔ ꢎꢐ ꢕ ꢍꢎꢑ ꢒꢗ ꢒꢔꢏꢄꢑꢖ ꢏꢀ
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
description/ordering information (continued)
The output pulse durationis programmed by selecting external resistance and capacitance values. The external
timing capacitor must be connected between C and R /C (positive) and an external resistor connected
ext
ext ext
between R /C and V . To obtain variable pulse durations, connect an external variable resistance between
ext ext
CC
R
/C and V . The output pulse duration also can be reduced by taking CLR low.
ext ext
CC
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR input can be used to override
A or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early
clearing.
The variance in output pulse duration from device to device typically is less than 0.5% for given external timing
components. An example of this distribution for the ’AHC123A is shown in Figure 10. Variations in output pulse
duration versus supply voltage and temperature are shown in Figure 6.
During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free,
without applying a reset pulse.
For additional application information on multivibrators, see the application report Designing With the
SN74AHC123A and SN74AHCT123A, literature number SCLA014.
FUNCTION TABLE
(each multivibrator)
INPUTS
OUTPUTS
CLR
L
A
X
H
X
L
B
X
X
L
Q
Q
L
H
†
L
†
X
H
H
†
L
†
X
H
↑
H
#
H
H
↑
L
†
These outputs are based on the
assumption that the indicated
steady-state conditions at the A and
B inputs have been set up long enough to
complete any pulse started before the
setup.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢄ ꢊ ꢀꢁꢋ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢄ
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SCLS352H − JULY 1997 − REVISED OCTOBER 2005
logic diagram, each multivibrator (positive logic)
R
C
/C
ext ext
A
B
ext
Q
Q
CLR
R
input/output timing diagram
t
rr
A
B
CLR
R
/C
ext ext
Q
Q
t
t
t
+ t
w
w
w
rr
3
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SCLS352H − JULY 1997 − REVISED OCTOBER 2005
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Output voltage range in high or low state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Output voltage range in power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to the network ground terminal.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54AHC123A SN74AHC123A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
2.1
3.85
1.5
2.1
3.85
= 3 V
High-level input voltage
V
V
IH
= 5.5 V
= 2 V
0.5
0.9
0.5
0.9
= 3 V
V
IL
Low-level input voltage
= 5.5 V
1.65
5.5
1.65
5.5
V
V
Input voltage
0
0
0
0
V
V
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−4
−8
50
4
−50
−4
−8
50
4
mA
= 3.3 V 0.3 V
= 5 V 0.5 V
= 2 V
I
High-level output current
OH
mA
mA
= 3.3 V 0.3 V
= 5 V 0.5 V
= 2 V
I
Low-level output current
External timing resistance
OL
mA
8
8
5k
1k
5k
1k
R
Ω
ext
> 3 V
∆t/∆V
CC
Power-up ramp rate
1
1
ms/V
T
A
Operating free-air temperature
−55
125
−40
85
°C
NOTE 4: Unused R /C
ext ext
terminals should be left unconnected. All remaining unused inputs of the device must be held at V
proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
or GND to ensure
CC
4
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ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢄ ꢊ ꢀꢁꢋ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢄ
ꢌꢍꢄ ꢎ ꢏꢐ ꢑꢏꢒ ꢓ ꢓꢐ ꢏꢄꢔꢎ ꢐ ꢕ ꢖꢁ ꢖꢀ ꢑꢄꢔꢎ ꢐ ꢕ ꢍꢎꢑ ꢒꢗ ꢒ ꢔꢏ ꢄꢑꢖ ꢏꢀ
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54AHC123A SN74AHC123A
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP MAX
MIN
1.9
MAX
MIN
1.9
MAX
2 V
3 V
1.9
2.9
2
3
2.9
2.9
I
= −50 mA
OH
4.5 V
3 V
4.4
4.5
4.4
4.4
V
V
OH
I
I
= −4 mA
= −8 mA
2.58
3.94
2.48
3.8
2.48
3.8
OH
4.5 V
2 V
OH
0.1
0.1
0.1
0.1
0.1
0.5
0.5
2.5
0.1
0.1
3 V
I
= 50 mA
OL
4.5 V
3 V
0.1
0.1
V
V
OL
I
I
= 4 mA
= 8 mA
0.36
0.36
0.25
0.44
0.44
2.5
OL
4.5 V
5.5 V
OL
†
V = V
I
or GND
or GND
or GND,
R
/C
ext ext
CC
CC
CC
I
I
mA
mA
I
V = V
I
0 V to 5.5 V
5.5 V
3 V
0.1
4
1*
40
1
40
A, B, and CLR
Quiescent
V = V
I
= 0
CC
CC
I
O
160
280
360
1.9
250
500
750
10
280
650
975
280
650
975
10
Active state
(per circuit)
V = V
R
or GND,
= 0.5 V
I
CC
ext ext
4.5 V
5.5 V
5 V
I
mA
/C
CC
C
V = V
CC
or GND
pF
i
I
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
This test is performed with the terminal in the off-state condition.
= 0 V.
CC
†
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
A
= 25°C
SN54AHC123A SN74AHC123A
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CLR
5
5
5
Pulse
duration
t
t
ns
w
A or B trigger
5
‡
5
‡
5
‡
R
R
= 1 kΩ, C
= 1 kΩ, C
= 100 pF
76
ns
ext
ext
ext
Pulse retrigger time
rr
‡
‡
‡
= 0.01 mF
1.8
ms
ext
‡
See retriggering data in the application information section.
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
A
= 25°C
SN54AHC123A SN74AHC123A
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CLR
5
5
5
Pulse
duration
t
t
ns
w
A or B trigger
5
‡
5
‡
5
‡
R
R
= 1 kΩ, C
= 1 kΩ, C
= 100 pF
59
ns
ext
ext
ext
Pulse retrigger time
rr
‡
‡
‡
= 0.01 mF
1.5
ms
ext
‡
See retriggering data in the application information section.
5
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ꢌ ꢍꢄꢎ ꢏ ꢐꢑ ꢏ ꢒꢓꢓ ꢐ ꢏꢄꢔ ꢎꢐ ꢕꢖ ꢁꢖ ꢀꢑꢄꢔ ꢎꢐ ꢕ ꢍꢎꢑ ꢒꢗ ꢒꢔꢏꢄꢑꢖ ꢏꢀ
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T = 25°C
A
SN54AHC123A SN74AHC123A
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
UNIT
ns
MIN
TYP
MAX
MIN
1*
1*
1*
1*
1*
1*
1
MAX
24*
MIN
1
MAX
24
t
t
t
t
t
t
t
t
t
t
t
t
9.5* 20.6*
10.2* 20.6*
7.5* 15.8*
9.3* 15.8*
10* 22.4*
10.6* 22.4*
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
C
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
A or B
CLR
Q or Q
Q or Q
Q or Q
Q or Q
Q or Q
Q or Q
L
L
L
L
L
24*
1
24
18.5*
18.5*
26*
1
18.5
18.5
26
ns
1
1
ns
CLR trigger
A or B
26*
1
26
10.5
11.8
8.9
24.1
24.1
19.3
19.3
25.9
25.9
27.5
27.5
22
1
27.5
27.5
22
ns
1
1
1
1
ns
CLR
10.5
11
1
22
1
22
1
29.5
29.5
1
29.5
29.5
= 50 pF
= 50 pF,
ns
CLR trigger
L
12.3
1
1
C
L
C
R
= 28 pF,
182
100
240
110
1.1
300
110
1.1
300
110
1.1
ns
ext
= 2 kΩ
ext
C
= 50 pF,
= 0.01 µF,
L
†
C
90
90
90
ms
t
w
Q or Q
ext
R
= 10 kΩ
ext
C
= 50 pF,
L
C
R
= 0.1 µF,
= 10 kΩ
0.9
1
1
0.9
0.9
ms
%
ext
ext
‡
∆t
w
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
t
= Pulse duration at Q and Q outputs
w
∆t = Output pulse-duration variation (Q and Q) between circuits in same package
w
6
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ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢄ ꢊ ꢀꢁꢋ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢄ
ꢌꢍꢄ ꢎ ꢏꢐ ꢑꢏꢒ ꢓ ꢓꢐ ꢏꢄꢔꢎ ꢐ ꢕ ꢖꢁ ꢖꢀ ꢑꢄꢔꢎ ꢐ ꢕ ꢍꢎꢑ ꢒꢗ ꢒ ꢔꢏ ꢄꢑꢖ ꢏꢀ
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
6.5*
SN54AHC123A SN74AHC123A
FROM
(NPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
UNIT
ns
MIN
MAX
12*
MIN
1*
1*
1*
1*
1*
1*
1
MAX
14*
14*
11*
11*
15*
15*
16
MIN
1
MAX
14
14
11
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
C
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
A or B
CLR
Q or Q
Q or Q
Q or Q
Q or Q
Q or Q
Q or Q
L
L
L
L
L
7.1*
12*
1
5.3*
9.4*
9.4*
1
ns
6.5*
1
11
6.9* 12.9*
7.4* 12.9*
1
15
15
16
16
13
13
17
17
ns
CLR trigger
A or B
1
7.3
8.3
6.3
7.4
7.6
8.7
14
14
1
ns
1
16
1
11.4
11.4
14.9
14.9
1
13
1
ns
CLR
1
13
1
1
17
1
= 50 pF
= 50 pF,
ns
CLR trigger
L
1
17
1
C
L
C
R
= 28 pF,
167
100
200
110
1.1
240
110
1.1
240
110
1.1
ns
ext
= 2 kΩ
ext
C
= 50 pF,
= 0.01 µF,
L
†
C
90
90
90
ms
t
w
Q or Q
ext
R
= 10 kΩ
ext
C
= 50 pF,
L
C
R
= 0.1 µF,
= 10 kΩ
0.9
1
1
0.9
0.9
ms
%
ext
ext
‡
∆t
w
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
t
= Pulse duration at Q and Q outputs
w
∆t = Output pulse-duration variation (Q and Q) between circuits in same package
w
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
29
pF
pd
7
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ꢌ ꢍꢄꢎ ꢏ ꢐꢑ ꢏ ꢒꢓꢓ ꢐ ꢏꢄꢔ ꢎꢐ ꢕꢖ ꢁꢖ ꢀꢑꢄꢔ ꢎꢐ ꢕ ꢍꢎꢑ ꢒꢗ ꢒꢔꢏꢄꢑꢖ ꢏꢀ
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
t
w
V
CC
C
L
Inputs or
Outputs
(see Note A)
50% V
50% V
CC
CC
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
V
CC
Input A
(see Note B)
50% V
CC
0 V
V
V
CC
Input CLR
(see Note B)
50% V
CC
50% V
CC
CC
Input B
0 V
50% V
(see Note B)
CC
t
t
t
0 V
PLH
PHL
t
t
V
PLH
OH
In-Phase
Output
V
V
OH
50% V
50% V
CC
CC
V
In-Phase
Output
50% V
CC
OL
OL
t
PHL
PLH
PHL
V
V
V
OH
OH
Out-of-Phase
Output
Out-of-Phase
Output
50% V
50% V
50% V
CC
CC
CC
V
OL
OL
VOLTAGE WAVEFORMS
DELAY TIMES
VOLTAGE WAVEFORMS
DELAY TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: Z = 50 Ω, t + 3 ns, t + 3 ns.
O
r
f
C. The outputs are measured one at a time, with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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ꢌꢍꢄ ꢎ ꢏꢐ ꢑꢏꢒ ꢓ ꢓꢐ ꢏꢄꢔꢎ ꢐ ꢕ ꢖꢁ ꢖꢀ ꢑꢄꢔꢎ ꢐ ꢕ ꢍꢎꢑ ꢒꢗ ꢒ ꢔꢏ ꢄꢑꢖ ꢏꢀ
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
APPLICATION INFORMATION
caution in use
To prevent malfunctions due to noise, connect a high-frequency capacitor between V
and GND, and keep
CC
the wiring between the external components and C and R /C terminals as short as possible.
ext
ext ext
power-down considerations
Large values of C can cause problems when powering down the ’AHC123A devices because of the amount
ext
of energy stored in the capacitor. When a system containing this device is powered down, the capacitor can
discharge from V
must be limited to 30 mA; therefore, the turn-off time of the V
through the protection diodes at pin 2 or pin 14. Current through the input protection diodes
CC
power supply must not be faster than
CC
t = V
× C /30 mA. For example, if V
= 5 V and C = 15 pF, the V
supply must turn off no faster than
CC
ext
CC
ext
CC
t = (5 V) × (15 pF)/30 mA = 2.5 ns. Usually, this is not a problem because power supplies are heavily filtered
and cannot discharge at this rate. When a more rapid decrease of V to zero occurs, the ’AHC123A devices
CC
can sustain damage. To avoid this possibility, use external clamping diodes.
output pulse duration
The output pulse duration, t , is determined primarily by the values of the external capacitance (C ) and timing
w
T
resistance (R ). The timing components are connected as shown in Figure 2.
T
V
CC
R
T
C
T
To R /C
ext ext
Terminal
To C
ext
Terminal
Figure 2. Timing-Component Connections
The pulse duration is given by:
tw + K RT CT
(1)
if C is ≥1000 pF, K = 1.0 or
T
if C is <1000 pF, K can be determined from Figure 9
T
where:
t
= pulse duration in ns
w
R
C
K
= external timing resistance in kΩ
= external capacitance in pF
= multiplier factor
T
T
Equation 1 and Figure 3 can be used to determine values for pulse duration, external resistance, and external
capacitance.
9
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ꢌ ꢍꢄꢎ ꢏ ꢐꢑ ꢏ ꢒꢓꢓ ꢐ ꢏꢄꢔ ꢎꢐ ꢕꢖ ꢁꢖ ꢀꢑꢄꢔ ꢎꢐ ꢕ ꢍꢎꢑ ꢒꢗ ꢒꢔꢏꢄꢑꢖ ꢏꢀ
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
APPLICATION INFORMATION
retriggering data
The minimum input retriggering time (t
) is the minimum time required after the initial signal before retriggering
MIR
the input. After t
, the device retriggers the output. Experimentally, it also can be shown that to retrigger the
MIR
output pulse, the two adjacent input signals should be t
duration is calculated as shown in Figure 3.
apart, where t
= 0.30 × t . The retrigger pulse
MIR
MIR w
t
MIR
Input
t
= t + t
w PLH
= (K × R × C ) + t
PLH
RT
T
T
Where:
t
t
RT
PLH
t
t
t
t
= Minimum Input Retriggering Time
= Propagation Delay
= Retrigger Time
t
MIR
PLH
RT
w
Output
= Output Pulse Duration Before Retriggering
w
Figure 3. Retrigger Pulse Duration
The minimum value from the end of the input pulse to the beginning of the retriggered output should be
approximately 15 ns to ensure a retriggered output (see Figure 4).
Input
t
MRT
Output
t
t
= Minimum Time Between the End of the Second Input Pulse and the Beginning of the Retriggered Output
= 15 ns
MRT
MRT
Figure 4. Input/Output Requirements
10
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ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢄ ꢊ ꢀꢁꢋ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢄ
ꢌꢍꢄ ꢎ ꢏꢐ ꢑꢏꢒ ꢓ ꢓꢐ ꢏꢄꢔꢎ ꢐ ꢕ ꢖꢁ ꢖꢀ ꢑꢄꢔꢎ ꢐ ꢕ ꢍꢎꢑ ꢒꢗ ꢒ ꢔꢏ ꢄꢑꢖ ꢏꢀ
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
†
APPLICATION INFORMATION
1.00E+09
V
T
A
= 5 V
CC
= 25°C
1.00E+08
1.00E+07
R
= 200k Ω
T
R
= 150k Ω
T
1.00E+06
1.00E+05
1.00E+04
1.00E+03
1.00E+02
1.00E+01
1.00E+00
R
= 80k Ω
R
= 10k Ω
T
T
R
= 5k Ω
T
R
= 1k Ω
T
2
10
3
10
4
10
5
10
6
10
7
10
1
10
C
− External Timing Capacitance − pF
T
Figure 5. Output Pulse Duration vs External Timing Capacitance
14%
t
= 866 ns at:
= 5 V
= 10 kΩ
= 50 pF
= 25°C
w
CC
T
T
A
V
R
C
12%
10%
V
CC
= 2.5 V
V
V
= 3 V
CC
CC
T
= 3.5 V
8%
6%
4%
2%
V
CC
V
CC
V
CC
V
CC
= 4 V
= 5 V
= 6 V
= 7 V
0%
−2%
−4%
−6%
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
Temperature − °C
Figure 6. Variations in Output Pulse Duration vs Temperature
†
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
11
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ꢌ ꢍꢄꢎ ꢏ ꢐꢑ ꢏ ꢒꢓꢓ ꢐ ꢏꢄꢔ ꢎꢐ ꢕꢖ ꢁꢖ ꢀꢑꢄꢔ ꢎꢐ ꢕ ꢍꢎꢑ ꢒꢗ ꢒꢔꢏꢄꢑꢖ ꢏꢀ
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
†
APPLICATION INFORMATION
OUTPUT PULSE-DURATION CONSTANT
MINIMUM TRIGGER TIME
vs
vs
SUPPLY VOLTAGE
V
CHARACTERISTICS
CC
10.00
1.00
0.10
1.20
1.15
R
T
= 10 kΩ
= 25°C
R
T
= 1 kΩ
= 25°C
T
A
T
A
t
= K × C × R
W
T T
C
= 0.01 µF
T
1.10
1.05
1.00
C
= 1000 pF
T
C
= 1000 pF
T
C
= 0.01 µF
T
C
= 100 pF
T
0.95
0.90
C
= 0.1 µF
T
0.01
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
1
2
3
4
5
6
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 8
Figure 7
DISTRIBUTION OF UNITS
vs
OUTPUT PULSE DURATION
EXTERNAL CAPACITANCE
vs
V
= 5 V
MULTIPLIER FACTOR
CC
T
= 25°C
= 50 pF
= 10 kW
0.001
A
For Capacitor Values of
0.001 µF or Greater,
K = 1.0
C
R
T
T
(K is Independent of R)
Mean = 856 ns
Median = 856 ns
Std. Dev. = 3.5 ns
0.0001
T
V
= 25°C
A
= 5 V
CC
−3 Std. Dev.
+3 Std. Dev.
0.00001
Median
1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50
Multiplier Factor − K
99% of Data Units
t
− Output Pulse Duration
w
Figure 9
Figure 10
†
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9860801Q2A
5962-9860801QEA
5962-9860801QFA
SN74AHC123AD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
16
16
16
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
D
SOIC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AHC123ADBR
SN74AHC123ADBRE4
SN74AHC123ADE4
SN74AHC123ADG4
SN74AHC123ADGVR
SN74AHC123ADGVRE4
SN74AHC123ADR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
DB
DB
D
16
16
16
16
16
16
16
16
16
16
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TVSOP
SOIC
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AHC123ADRE4
SN74AHC123ADRG4
SN74AHC123AN
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74AHC123ANE4
SN74AHC123APWR
SN74AHC123APWRE4
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TSSOP
TSSOP
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54AHC123AFK
SNJ54AHC123AJ
SNJ54AHC123AW
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
16
16
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2007
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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