SN74AHC126DG4 [TI]
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS; 具有三态输出翻两番总线缓冲器GATES
| 型号： | SN74AHC126DG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| 文件： | 总21页 (文件大小：625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AHC126, SN74AHC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS257L – DECEMBER 1995 – REVISED JULY 2003
SN54AHC126 . . . J OR W PACKAGE
SN74AHC126 . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
Operating Range 2-V to 5.5-V V
CC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
1
2
3
4
5
6
7
14
13
12
11
10
9
1OE
1A
1Y
2OE
2A
2Y
V
CC
4OE
description/ordering information
4A
4Y
3OE
3A
3Y
The ’AHC126 devices are quadruple bus buffer
gates featuring independent line drivers with
3-state outputs. Each output is disabled when the
associated output-enable (OE) input is low. When
OE is high, the respective gate passes the data
from the A input to its Y output.
8
GND
To ensure the high-impedance state during power
up or power down, OE should be tied to GND
through a pulldown resistor; the minimum value of
the resistor is determined by the current-sourcing
capability of the driver.
SN54AHC126 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
18 4A
1Y
NC
4
5
6
7
8
17
16
15
14
NC
4Y
2OE
NC
NC
3OE
2A
9 10 11 12 13
NC – No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
SOIC – D
Tube
SN74AHC126N
SN74AHC126N
Tube
SN74AHC126D
AHC126
Tape and reel
Tape and reel
Tape and reel
Tube
SN74AHC126DR
SN74AHC126NSR
SN74AHC126DBR
SN74AHC126PW
SN74AHC126PWR
SN74AHC126DGVR
SNJ54AHC126J
SNJ54AHC126W
SNJ54AHC126FK
SOP – NS
AHC126
HA126
–40°C to 85°C
SSOP – DB
TSSOP – PW
HA126
Tape and reel
Tape and reel
Tube
TVSOP – DGV
CDIP – J
HA126
SNJ54AHC126J
–55°C to 125°C
CFP – W
Tube
SNJ54AHC126W
SNJ54AHC126FK
LCCC – FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC126, SN74AHC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS257L – DECEMBER 1995 – REVISED JULY 2003
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
H
H
L
H
L
X
Z
logic diagram (positive logic)
1
10
1OE
3OE
3A
2
3
6
9
8
1A
1Y
2Y
3Y
4Y
4
13
12
2OE
4OE
4A
5
11
2A
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC126, SN74AHC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS257L – DECEMBER 1995 – REVISED JULY 2003
recommended operating conditions (see Note 3)
SN54AHC126 SN74AHC126
UNIT
MIN
MAX
MIN
MAX
V
V
Supply voltage
2
5.5
2
5.5
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
2.1
3.85
1.5
2.1
3.85
High-level input voltage
= 3 V
IH
= 5.5 V
= 2 V
0.5
0.9
0.5
0.9
V
IL
Low-level input voltage
= 3 V
V
= 5.5 V
1.65
5.5
1.65
5.5
V
V
Input voltage
0
0
0
0
V
V
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
–50
–4
–8
50
4
–50
–4
–8
50
4
A
I
High-level output current
Low-level output current
= 3.3 V ± 0.3 V
= 5 V ± 0.5 V
= 2 V
OH
OL
mA
A
I
= 3.3 V ± 0.3 V
= 5 V ± 0.5 V
= 3.3 V ± 0.3 V
= 5 V ± 0.5 V
mA
8
8
100
20
125
100
20
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
–55
–40
°C
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
2
SN54AHC126 SN74AHC126
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
1.9
MAX
MIN
1.9
MAX
MIN
1.9
MAX
2 V
3 V
I
= –50
A
2.9
3
2.9
2.9
OH
4.5 V
3 V
4.4
4.5
4.4
4.4
V
V
OH
OL
2.58
3.94
2.48
3.8
2.48
3.8
I
I
= –4 mA
OH
4.5 V
2 V
= –8 mA
OH
0.1
0.1
0.1
0.1
0.1
0.5
0.5
±1*
±2.5
40
0.1
0.1
I
= 50
A
3 V
OL
4.5 V
3 V
0.1
0.1
V
V
0.36
0.36
±0.1
±0.25
4
0.44
0.44
±1
I
I
= 4 mA
= 8 mA
OL
4.5 V
0 V to 5.5 V
5.5 V
5.5 V
5 V
OL
I
I
I
V = 5.5 V or GND
A
A
I
I
V
= V or GND
CC
±2.5
40
OZ
CC
O
V = V
or GND,
or GND
I = 0
O
A
I
CC
CC
C
V = V
4
10
10
pF
i
I
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
CC
= 0 V.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC126, SN74AHC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS257L – DECEMBER 1995 – REVISED JULY 2003
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
5.6*
5.6*
5.4*
5.4*
7*
SN54AHC126 SN74AHC126
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
ns
MIN
MAX
8*
MIN
1*
MAX
9.5*
9.5*
9.5*
9.5*
MIN
1
MAX
9.5
9.5
9.5
9.5
11.5
11.5
13
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
Y
Y
Y
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
L
L
L
L
L
8*
1*
1
8*
1*
1
ns
OE
OE
A
8*
1*
1
9.7*
9.7*
11.5
11.5
11.5
11.5
13.2
13.2
1* 11.5*
1* 11.5*
1
ns
7*
1
8.1
1
1
1
1
1
1
13
13
13
13
15
15
1
ns
8.1
1
13
7.9
1
13
ns
OE
OE
7.9
1
13
9.5
1
15
C
C
= 50 pF
= 50 pF
ns
ns
L
L
9.5
1
15
t
1.5**
1.5
sk(o)
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
3.8*
3.8*
3.6*
3.6*
4.6*
4.6*
5.3
SN54AHC126 SN74AHC126
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
ns
MIN
MAX
5.5*
5.5*
5.1*
5.1*
6.8*
6.8*
7.5
MIN
1*
1*
1*
1*
1*
1*
1
MAX
6.5*
6.5*
6*
MIN
1
MAX
6.5
6.5
6
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
Y
Y
Y
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
L
L
L
L
L
1
1
ns
OE
OE
A
6*
1
6
8*
1
8
ns
8*
1
8
8.5
8.5
8
1
8.5
8.5
8
ns
5.3
7.5
1
1
5.1
7.1
1
1
ns
OE
OE
5.1
7.1
1
8
1
8
6.1
8.8
1
10
10
1
10
10
C
C
= 50 pF
= 50 pF
ns
ns
L
L
6.1
8.8
1
1
t
1**
1
sk(o)
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC126, SN74AHC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS257L – DECEMBER 1995 – REVISED JULY 2003
noise characteristics, V
= 5 V, C = 50 pF, T = 25°C (see Note 4)
CC
L
A
SN74AHC126
UNIT
PARAMETER
MIN
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
0.8
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.8
OL
4.4
3.5
OH
1.5
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
14
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC126, SN74AHC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS257L – DECEMBER 1995 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
50% V
CC
Input
CC
50% V
50% V
CC
Data Input
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
t
Input
CC
CC
CC
CC
0 V
0 V
t
PZL
t
t
t
PLZ
PLH
PHL
Output
Waveform 1
V
OH
≈V
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
V
OL
+ 0.3 V
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
– 0.3 V
50% V
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9686201Q2A
5962-9686201QCA
5962-9686201QDA
SN74AHC126D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
14
14
14
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
D
SOIC
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AHC126DBLE
SN74AHC126DBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
14
14
TBD
Call TI
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AHC126DBRE4
SN74AHC126DBRG4
SN74AHC126DE4
SN74AHC126DG4
SN74AHC126DGVR
SN74AHC126DGVRE4
SN74AHC126DGVRG4
SN74AHC126DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
TVSOP
TVSOP
TVSOP
SOIC
SOIC
SOIC
PDIP
DB
DB
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGV
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AHC126DRE4
SN74AHC126DRG4
SN74AHC126N
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74AHC126NE4
SN74AHC126NSR
SN74AHC126NSRE4
SN74AHC126NSRG4
SN74AHC126PW
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SO
NS
NS
NS
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AHC126PWE4
SN74AHC126PWG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AHC126PWLE
SN74AHC126PWR
OBSOLETE TSSOP
PW
PW
14
14
TBD
Call TI
Call TI
ACTIVE
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AHC126PWRE4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74AHC126PWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54AHC126FK
SNJ54AHC126J
SNJ54AHC126W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
(mm)
16
SN74AHC126DBR
SN74AHC126DGVR
SN74AHC126DR
DB
DGV
D
14
14
14
14
14
MLA
MLA
MLA
MLA
MLA
8.2
6.8
6.5
8.2
7.0
6.6
4.0
2.5
1.6
2.1
2.5
1.6
12
8
16
16
16
16
12
Q1
Q1
Q1
Q1
Q1
12
16
9.0
8
SN74AHC126NSR
SN74AHC126PWR
NS
16
10.5
5.6
12
8
PW
12
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74AHC126DBR
SN74AHC126DGVR
SN74AHC126DR
DB
DGV
D
14
14
14
14
14
MLA
MLA
MLA
MLA
MLA
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
33.0
29.0
33.0
33.0
29.0
SN74AHC126NSR
SN74AHC126PWR
NS
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
Pack Materials-Page 3
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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