SN74AHC138DRE4 [TI]
3 线至 8 线解码器/多路解复用器 | D | 16 | -40 to 85;
| 型号： | SN74AHC138DRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3 线至 8 线解码器/多路解复用器 | D | 16 | -40 to 85 驱动 输入元件 光电二极管 逻辑集成电路 复用器 解复用器 解码器 驱动器 |
| 文件： | 总9页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUARY 2000
SN54AHC138 . . . J OR W PACKAGE
SN74AHC138 . . . D, DB, DGV, N, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Process
Operating Range 2-V to 5.5-V V
CC
A
B
V
CC
15 Y0
Designed Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
1
2
3
4
5
6
7
8
16
14
13
12
11
10
9
C
Y1
Y2
Y3
Y4
Y5
Y6
G2A
G2B
G1
Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Y7
GND
ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
SN54AHC138 . . . FK PACKAGE
(TOP VIEW)
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
3
2
1 20 19
18
Y1
C
G2A
NC
4
5
6
7
8
17 Y2
16
NC
15
Y3
G2B
G1
description
14
Y4
9 10 11 12 13
The ’AHC138 decoders/demultiplexers are
designed for high-performance memory-decoding
and data-routing applications that require very
NC – No internal connection
short
propagation-delay
times.
In
high-performance memory systems, these
decoders can be used to minimize the effects of
system decoding. When employed with
high-speed memories utilizing a fast enable
circuit, the delay times of these decoders and the
enable time of the memory are usually less than
thetypicalaccesstimeofthememory. Thismeans
that the effective system delay introduced by the
decoders is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
TheSN54AHC138 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AHC138 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUARY 2000
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1
G2A
H
X
X
L
G2B
C
X
X
X
L
B
X
X
X
L
A
X
X
X
L
Y0
H
H
H
L
Y1
H
H
H
H
L
Y2
H
H
H
H
H
L
Y3
H
H
H
H
H
H
L
Y4
H
H
H
H
H
H
H
L
Y5
H
H
H
H
H
H
H
H
L
Y6
H
H
H
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
H
H
H
L
X
X
L
X
H
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
L
H
H
H
H
L
H
H
†
logic symbols (alternatives)
BIN/OCT
1
DMUX
15
14
13
12
11
10
9
15
14
13
12
11
10
9
1
2
3
0
1
2
3
4
5
6
7
Y0
0
1
2
3
4
5
6
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A
B
C
1
2
4
A
B
C
0
2
2
3
0
7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
G
&
&
6
4
6
4
G1
G2A
G2B
G1
G2A
G2B
EN
5
5
7
7
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUARY 2000
logic diagram (positive logic)
15
Y0
1
A
14
Y1
13
Y2
2
3
Select
Inputs
B
C
12
Y3
Data
Outputs
11
Y4
10
Y5
9
Y6
4
5
6
7
G2A
G2B
Y7
Enable
Inputs
G1
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUARY 2000
recommended operating conditions (see Note 3)
SN54AHC138 SN74AHC138
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
V
V
V
V
V
= 2 V
1.5
2.1
3.85
1.5
2.1
3.85
CC
CC
CC
CC
CC
CC
High-level input voltage
= 3 V
V
V
IH
= 5.5 V
= 2 V
0.5
0.9
0.5
0.9
V
IL
Low-level input voltage
= 3 V
= 5.5 V
1.65
5.5
1.65
5.5
V
V
Input voltage
0
0
0
0
V
V
A
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
–50
–4
–8
50
4
–50
–4
–8
50
4
I
High-level output current
Low-level output current
= 3.3 V ± 0.3 V
= 5 V ± 0.5 V
= 2 V
OH
OL
mA
A
I
= 3.3 V ± 0.3 V
= 5 V ± 0.5 V
= 3.3 V ± 0.3 V
= 5 V ± 0.5 V
mA
8
8
100
20
125
100
20
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
A
–55
–40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
2
SN54AHC138 SN74AHC138
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
1.9
MAX
MIN
1.9
MAX
MIN
1.9
MAX
2 V
3 V
I
= –50
A
2.9
3
2.9
2.9
OH
4.5 V
3 V
4.4
4.5
4.4
4.4
V
V
V
OH
OL
2.58
3.94
2.48
3.8
2.48
3.8
I
I
= –4 mA
OH
4.5 V
2 V
= –8 mA
OH
0.1
0.1
0.1
0.1
0.1
0.5
0.5
±1*
40
0.1
0.1
0.1
0.44
0.44
±1
I
= 50
A
3 V
OL
4.5 V
3 V
0.1
V
0.36
0.36
±0.1
4
I
I
= 4 mA
= 8 mA
OL
4.5 V
0 V to 5.5 V
5.5 V
5 V
OL
I
I
V = V
or GND
or GND,
or GND
A
A
I
I
CC
CC
CC
V = V
I = 0
O
40
CC
I
C
V = V
2
10
10
pF
i
I
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
CC
= 0 V.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
T = 25°C
A
SN54AHC138 SN74AHC138
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
ns
MIN
TYP
MAX
MIN
1*
MAX
13*
13*
15*
15*
MIN
1
MAX
13
t
t
t
t
t
t
t
t
t
t
t
t
8.2* 11.4*
8.2* 11.4*
8.1* 12.8*
8.1* 12.8*
8.2* 11.4*
8.2* 11.4*
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
A, B, C
G1
Any Y
Any Y
Any Y
Any Y
Any Y
Any Y
C
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
= 50 pF
L
L
L
L
L
L
1*
1
13
1*
1
15
ns
1*
1
15
1* 13.5*
1* 13.5*
1
13.5
13.5
18
ns
G2A, G2B
A, B, C
1
10
10
15.8
15.8
16.3
16.3
14.9
14.9
1
1
1
1
1
1
18
18
1
ns
1
18
10.6
10.6
10.7
10.7
18.5
18.5
17
1
18.5
18.5
17
G1
ns
1
1
ns
G2A, G2B
17
1
17
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
5.7*
5.7*
5.6*
5.6*
5.8*
5.8*
7.2
SN54AHC138 SN74AHC138
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
ns
MIN
MAX
8.1*
8.1*
8.1*
8.1*
8.1*
8.1*
10.1
10.1
10.1
10.1
10.1
10.1
MIN
1*
1*
1*
1*
1*
1*
1
MAX
9.5*
9.5*
9.5*
9.5*
9.5*
9.5*
11.5
11.5
11.5
11.5
11.5
11.5
MIN
1
MAX
9.5
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
A, B, C
G1
Any Y
Any Y
Any Y
Any Y
Any Y
Any Y
C
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
= 50 pF
L
L
L
L
L
L
1
9.5
1
9.5
ns
1
9.5
1
9.5
ns
G2A, G2B
A, B, C
1
9.5
1
11.5
11.5
11.5
11.5
11.5
11.5
ns
7.2
1
1
7.1
1
1
G1
ns
7.1
1
1
7.3
1
1
ns
G2A, G2B
7.3
1
1
*
On products compliant to MIL-PRF-38535, this parameter is not production tested.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
13
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
50% V
CC
Input
CC
50% V
50% V
CC
Data Input
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
t
Input
CC
CC
CC
CC
0 V
0 V
t
PZL
t
t
t
PLZ
PLH
PHL
Output
Waveform 1
V
OH
≈V
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
V
OL
+ 0.3 V
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
– 0.3 V
50% V
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUARY 2000
APPLICATION INFORMATION
SN74AHC138
BIN/OCT
15
14
13
12
11
10
9
1
2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
2
3
4
6
4
5
&
V
CC
EN
7
SN74AHC138
BIN/OCT
15
14
13
12
11
10
9
1
2
0
1
2
3
4
5
6
7
8
A0
A1
A2
1
2
9
10
11
12
13
14
15
3
4
6
4
5
&
A3
A4
EN
7
SN74AHC138
BIN/OCT
15
14
13
12
11
10
9
1
2
0
1
2
3
4
5
6
7
16
17
18
19
20
21
22
23
1
2
3
4
6
4
5
&
EN
7
Figure 2. 24-Bit Decoding Scheme
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUARY 2000
APPLICATION INFORMATION
SN74AHC138
BIN/OCT
15
14
13
12
11
10
9
1
2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
A0
A1
A2
1
2
3
4
6
4
5
&
V
CC
A3
EN
A4
7
SN74AHC138
BIN/OCT
15
14
13
12
11
10
9
1
2
0
1
2
3
4
5
6
7
8
1
2
9
10
11
12
13
14
15
3
4
6
4
5
&
EN
7
SN74AHC138
BIN/OCT
15
14
13
12
11
10
9
1
2
0
1
2
3
4
5
6
7
16
17
18
19
20
21
22
23
1
2
3
4
6
4
5
&
EN
7
SN74AHC138
BIN/OCT
15
14
13
12
11
10
9
1
2
0
1
2
3
4
5
6
7
24
25
26
27
28
29
30
31
1
2
3
4
6
4
5
&
EN
7
Figure 3. 32-Bit Decoding Scheme
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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